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[/] [or1k/] [tags/] [rel-0-3-0-rc1/] [or1ksim/] [peripheral/] [gpio.c] - Blame information for rev 1724

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Line No. Rev Author Line
1 444 erez
/* gpio.h -- GPIO code simulation
2
   Copyright (C) 2001 Erez Volk, erez@mailandnews.comopencores.org
3
 
4
   This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
   This program is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 2 of the License, or
9
   (at your option) any later version.
10
 
11
   This program is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
18
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
*/
20 1308 phoenix
#include <string.h>
21 444 erez
 
22 1350 nogj
#include "config.h"
23
 
24
#ifdef HAVE_INTTYPES_H
25
#include <inttypes.h>
26
#endif
27
 
28
#include "port.h"
29
#include "arch.h"
30 1308 phoenix
#include "abstract.h"
31 444 erez
#include "gpio.h"
32
#include "sim-config.h"
33
#include "pic.h"
34
#include "vapi.h"
35 1308 phoenix
#include "debug.h"
36 1374 nogj
#include "sched.h"
37 444 erez
 
38 1489 nogj
DEFAULT_DEBUG_CHANNEL(gpio);
39
 
40 1724 nogj
 
41
/*
42
 * The various VAPI IDs each GPIO device has
43
 */
44
enum { GPIO_VAPI_DATA = 0,
45
       GPIO_VAPI_AUX,
46
       GPIO_VAPI_CLOCK,
47
       GPIO_VAPI_RGPIO_OE,
48
       GPIO_VAPI_RGPIO_INTE,
49
       GPIO_VAPI_RGPIO_PTRIG,
50
       GPIO_VAPI_RGPIO_AUX,
51
       GPIO_VAPI_RGPIO_CTRL,
52
       GPIO_NUM_VAPI_IDS };
53
 
54
/*
55
 * Implementatino of GPIO Code Registers and State
56
 */
57
struct gpio_device
58
{
59
  /* Is peripheral enabled */
60
  int enabled;
61
 
62
  /* Base address in memory */
63
  oraddr_t baseaddr;
64
 
65
  /* Which IRQ to generate */
66
  int irq;
67
 
68
  /* Which GPIO is this? */
69
  unsigned gpio_number;
70
 
71
  /* VAPI IDs */
72
  unsigned long base_vapi_id;
73
 
74
  /* Auxiliary inputs */
75
  unsigned long auxiliary_inputs;
76
 
77
  /* Visible registers */
78
  struct
79
  {
80
    unsigned long in;
81
    unsigned long out;
82
    unsigned long oe;
83
    unsigned long inte;
84
    unsigned long ptrig;
85
    unsigned long aux;
86
    unsigned long ctrl;
87
    unsigned long ints;
88
 
89
    int external_clock;
90
  } curr, next;
91
};
92
 
93 1366 nogj
static void gpio_vapi_read( unsigned long id, unsigned long data, void *dat );
94 1374 nogj
static void gpio_external_clock( unsigned long value, struct gpio_device *gpio );
95 444 erez
static void gpio_device_clock( struct gpio_device *gpio );
96 1564 nogj
static void gpio_clock( void *dat );
97 444 erez
 
98
/* Initialize all parameters and state */
99 1649 nogj
static void gpio_reset( void *dat )
100 444 erez
{
101 1374 nogj
  struct gpio_device *gpio = dat;
102 444 erez
 
103 1374 nogj
  if ( gpio->baseaddr != 0 ) {
104
    /* Possibly connect to VAPI */
105
    if ( gpio->base_vapi_id ) {
106
      vapi_install_multi_handler( gpio->base_vapi_id, GPIO_NUM_VAPI_IDS, gpio_vapi_read, dat );
107 444 erez
    }
108
  }
109 1564 nogj
  SCHED_ADD(gpio_clock, dat, 1);
110 444 erez
}
111
 
112
 
113
/* Dump status */
114 1649 nogj
static void gpio_status( void *dat )
115 444 erez
{
116 1374 nogj
  struct gpio_device *gpio = dat;
117 444 erez
 
118 1374 nogj
  if ( gpio->baseaddr == 0 )
119
    return;
120 444 erez
 
121 1374 nogj
  PRINTF( "\nGPIO at 0x%"PRIxADDR":\n", gpio->baseaddr );
122
  PRINTF( "RGPIO_IN     : 0x%08lX\n", gpio->curr.in );
123
  PRINTF( "RGPIO_OUT    : 0x%08lX\n", gpio->curr.out );
124
  PRINTF( "RGPIO_OE     : 0x%08lX\n", gpio->curr.oe );
125
  PRINTF( "RGPIO_INTE   : 0x%08lX\n", gpio->curr.inte );
126
  PRINTF( "RGPIO_PTRIG  : 0x%08lX\n", gpio->curr.ptrig );
127
  PRINTF( "RGPIO_AUX    : 0x%08lX\n", gpio->curr.aux );
128
  PRINTF( "RGPIO_CTRL   : 0x%08lX\n", gpio->curr.ctrl );
129
  PRINTF( "RGPIO_INTS   : 0x%08lX\n", gpio->curr.ints );
130 444 erez
}
131
 
132
 
133
/* Wishbone read */
134 1649 nogj
static uint32_t gpio_read32( oraddr_t addr, void *dat )
135 444 erez
{
136 1374 nogj
  struct gpio_device *gpio = dat;
137 444 erez
 
138
  switch( addr ) {
139 502 erez
  case RGPIO_IN: return gpio->curr.in | gpio->curr.out;
140 444 erez
  case RGPIO_OUT: return gpio->curr.out;
141
  case RGPIO_OE: return gpio->curr.oe;
142
  case RGPIO_INTE: return gpio->curr.inte;
143
  case RGPIO_PTRIG: return gpio->curr.ptrig;
144
  case RGPIO_AUX: return gpio->curr.aux;
145
  case RGPIO_CTRL: return gpio->curr.ctrl;
146 502 erez
  case RGPIO_INTS: return gpio->curr.ints;
147 444 erez
  }
148 1374 nogj
 
149
  return 0;
150 444 erez
}
151
 
152
 
153
/* Wishbone write */
154 1649 nogj
static void gpio_write32( oraddr_t addr, uint32_t value, void *dat )
155 444 erez
{
156 1374 nogj
  struct gpio_device *gpio = dat;
157 444 erez
 
158
  switch( addr ) {
159 1489 nogj
  case RGPIO_IN: TRACE( "GPIO: Cannot write to RGPIO_IN\n" ); break;
160 444 erez
  case RGPIO_OUT: gpio->next.out = value; break;
161
  case RGPIO_OE: gpio->next.oe = value; break;
162
  case RGPIO_INTE: gpio->next.inte = value; break;
163
  case RGPIO_PTRIG: gpio->next.ptrig = value; break;
164
  case RGPIO_AUX: gpio->next.aux = value; break;
165
  case RGPIO_CTRL: gpio->next.ctrl = value; break;
166 1715 nogj
  case RGPIO_INTS:
167
    if ( gpio->next.ints && !value )
168
      clear_interrupt( gpio->irq );
169
    gpio->next.ints = value;
170
    break;
171 444 erez
  }
172
}
173
 
174
 
175
/* Input from "outside world" */
176 1649 nogj
static void gpio_vapi_read( unsigned long id, unsigned long data, void *dat )
177 444 erez
{
178
  unsigned which;
179 1374 nogj
  struct gpio_device *gpio = dat;
180 444 erez
 
181 1489 nogj
  TRACE( "GPIO: id %08lx, data %08lx\n", id, data );
182 444 erez
 
183 1374 nogj
  which = id - gpio->base_vapi_id;
184 444 erez
 
185
  switch( which ) {
186 477 erez
  case GPIO_VAPI_DATA:
187 1489 nogj
    TRACE( "GPIO: Next input from VAPI = 0x%08lx (RGPIO_OE = 0x%08lx)\n",
188 1350 nogj
           data, gpio->next.oe );
189 477 erez
    gpio->next.in = data;
190
    break;
191
  case GPIO_VAPI_AUX:
192
    gpio->auxiliary_inputs = data;
193
    break;
194
  case GPIO_VAPI_RGPIO_OE:
195
    gpio->next.oe = data;
196
    break;
197
  case GPIO_VAPI_RGPIO_INTE:
198
    gpio->next.inte = data;
199
    break;
200
  case GPIO_VAPI_RGPIO_PTRIG:
201
    gpio->next.ptrig = data;
202
    break;
203
  case GPIO_VAPI_RGPIO_AUX:
204
    gpio->next.aux = data;
205
    break;
206
  case GPIO_VAPI_RGPIO_CTRL:
207
    gpio->next.ctrl = data;
208
    break;
209
  case GPIO_VAPI_CLOCK:
210 1374 nogj
    gpio_external_clock( data, gpio );
211 477 erez
    break;
212 444 erez
  }
213 1564 nogj
}
214 444 erez
 
215 1564 nogj
/* System Clock. */
216
static void gpio_clock( void *dat )
217
{
218
  struct gpio_device *gpio = dat;
219
 
220 1374 nogj
  /* Clock the device */
221
  if ( !(gpio->curr.ctrl & RGPIO_CTRL_ECLK) )
222
    gpio_device_clock( gpio );
223 1564 nogj
  SCHED_ADD(gpio_clock, dat, 1);
224 444 erez
}
225
 
226
/* External Clock. */
227 1374 nogj
static void gpio_external_clock( unsigned long value, struct gpio_device *gpio )
228 444 erez
{
229 1374 nogj
  int use_external_clock = ((gpio->curr.ctrl & RGPIO_CTRL_ECLK) == RGPIO_CTRL_ECLK);
230
  int negative_edge = ((gpio->curr.ctrl & RGPIO_CTRL_NEC) == RGPIO_CTRL_NEC);
231 444 erez
 
232 477 erez
  /* "Normalize" clock value */
233 444 erez
  value = (value != 0);
234
 
235 1374 nogj
  gpio->next.external_clock = value;
236 444 erez
 
237 1374 nogj
  if ( use_external_clock && (gpio->next.external_clock != gpio->curr.external_clock) && (value != negative_edge) )
238
    /* Make sure that in vapi_read, we don't clock the device */
239
    if ( gpio->curr.ctrl & RGPIO_CTRL_ECLK )
240 444 erez
      gpio_device_clock( gpio );
241
}
242
 
243 1374 nogj
/* Report an interrupt to the sim */
244 1649 nogj
static void gpio_do_int( void *dat )
245 1374 nogj
{
246
  struct gpio_device *gpio = dat;
247 477 erez
 
248 1374 nogj
  report_interrupt( gpio->irq );
249
}
250
 
251 444 erez
/* Clock as handld by one device. */
252 1374 nogj
static void gpio_device_clock( struct gpio_device *gpio )
253 444 erez
{
254 445 erez
  /* Calculate new inputs and outputs */
255
  gpio->next.in &= ~gpio->next.oe; /* Only input bits */
256
  /* Replace requested output bits with aux input */
257
  gpio->next.out = (gpio->next.out & ~gpio->next.aux) | (gpio->auxiliary_inputs & gpio->next.aux);
258
  gpio->next.out &= gpio->next.oe; /* Only output-enabled bits */
259
 
260 444 erez
  /* If any outputs changed, notify the world (i.e. vapi) */
261 477 erez
  if ( gpio->next.out != gpio->curr.out ) {
262 1489 nogj
    TRACE( "GPIO: New output 0x%08lx, RGPIO_OE = 0x%08lx\n", gpio->next.out,
263 1350 nogj
           gpio->next.oe );
264 477 erez
    if ( gpio->base_vapi_id )
265
      vapi_send( gpio->base_vapi_id + GPIO_VAPI_DATA, gpio->next.out );
266
  }
267 444 erez
 
268 445 erez
  /* If any inputs changed and interrupt enabled, generate interrupt */
269 477 erez
  if ( gpio->next.in != gpio->curr.in ) {
270 1489 nogj
    TRACE( "GPIO: New input 0x%08lx\n", gpio->next.in );
271 477 erez
 
272
    if ( gpio->next.ctrl & RGPIO_CTRL_INTE ) {
273
      unsigned changed_bits = gpio->next.in ^ gpio->curr.in; /* inputs that have changed */
274
      unsigned set_bits = changed_bits & gpio->next.in; /* inputs that have been set */
275
      unsigned cleared_bits = changed_bits & gpio->curr.in; /* inputs that have been cleared */
276
      unsigned relevant_bits = (gpio->next.ptrig & set_bits) | (~gpio->next.ptrig & cleared_bits);
277
 
278
      if ( relevant_bits & gpio->next.inte ) {
279 1489 nogj
        TRACE( "GPIO: Reporting interrupt %d\n", gpio->irq );
280 502 erez
        gpio->next.ctrl |= RGPIO_CTRL_INTS;
281
        gpio->next.ints |= relevant_bits & gpio->next.inte;
282 1374 nogj
        /* Since we can't report an interrupt during a readmem/writemem
283
         * schedule the scheduler to do it.  Read the comment above
284
         * report_interrupt in pic/pic.c */
285 1390 nogj
        SCHED_ADD( gpio_do_int, gpio, 1 );
286 477 erez
      }
287 444 erez
    }
288
  }
289
 
290
  /* Switch to values for next clock */
291
  memcpy( &(gpio->curr), &(gpio->next), sizeof(gpio->curr) );
292
}
293 1358 nogj
 
294
/*---------------------------------------------------[ GPIO configuration ]---*/
295 1649 nogj
static void gpio_baseaddr(union param_val val, void *dat)
296 1358 nogj
{
297 1374 nogj
  struct gpio_device *gpio = dat;
298
  gpio->baseaddr = val.addr_val;
299 1358 nogj
}
300
 
301 1649 nogj
static void gpio_irq(union param_val val, void *dat)
302 1358 nogj
{
303 1374 nogj
  struct gpio_device *gpio = dat;
304
  gpio->irq = val.int_val;
305 1358 nogj
}
306
 
307 1649 nogj
static void gpio_base_vapi_id(union param_val val, void *dat)
308 1358 nogj
{
309 1374 nogj
  struct gpio_device *gpio = dat;
310
  gpio->base_vapi_id = val.int_val;
311 1358 nogj
}
312
 
313 1649 nogj
static void gpio_enabled(union param_val val, void *dat)
314 1461 nogj
{
315
  struct gpio_device *gpio = dat;
316
  gpio->enabled = val.int_val;
317
}
318
 
319 1649 nogj
static void *gpio_sec_start(void)
320 1374 nogj
{
321
  struct gpio_device *new = malloc(sizeof(struct gpio_device));
322
 
323
  if(!new) {
324 1383 nogj
    fprintf(stderr, "Peripheral gpio: Run out of memory\n");
325 1374 nogj
    exit(-1);
326
  }
327
 
328
  new->auxiliary_inputs = 0;
329
  memset(&new->curr, 0, sizeof(new->curr));
330
  memset(&new->next, 0, sizeof(new->next));
331
 
332 1461 nogj
  new->enabled = 1;
333
 
334 1374 nogj
  return new;
335
}
336
 
337 1649 nogj
static void gpio_sec_end(void *dat)
338 1374 nogj
{
339
  struct gpio_device *gpio = dat;
340 1486 nogj
  struct mem_ops ops;
341 1374 nogj
 
342 1461 nogj
  if(!gpio->enabled) {
343
    free(dat);
344
    return;
345
  }
346
 
347 1486 nogj
  memset(&ops, 0, sizeof(struct mem_ops));
348
 
349
  ops.readfunc32 = gpio_read32;
350
  ops.writefunc32 = gpio_write32;
351
  ops.write_dat32 = dat;
352
  ops.read_dat32 = dat;
353
 
354
  /* FIXME: Correct delays? */
355
  ops.delayr = 2;
356
  ops.delayw = 2;
357
 
358 1374 nogj
  /* Register memory range */
359 1486 nogj
  reg_mem_area( gpio->baseaddr, GPIO_ADDR_SPACE, 0, &ops );
360 1374 nogj
 
361
  reg_sim_reset(gpio_reset, dat);
362
  reg_sim_stat(gpio_status, dat);
363
}
364
 
365 1358 nogj
void reg_gpio_sec(void)
366
{
367 1383 nogj
  struct config_section *sec = reg_config_sec("gpio", gpio_sec_start, gpio_sec_end);
368 1358 nogj
 
369 1461 nogj
  reg_config_param(sec, "enabled", paramt_int, gpio_enabled);
370 1358 nogj
  reg_config_param(sec, "baseaddr", paramt_addr, gpio_baseaddr);
371
  reg_config_param(sec, "irq", paramt_int, gpio_irq);
372
  reg_config_param(sec, "base_vapi_id", paramt_int, gpio_base_vapi_id);
373
}

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