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[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [cuc/] [verilog.c] - Blame information for rev 1555

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1 1244 hpanther 
/* verilog.c -- OpenRISC Custom Unit Compiler, verilog generator
2 
 *    Copyright (C) 2002 Marko Mlinar, markom@opencores.org
3 
 *
4 
 *    This file is part of OpenRISC 1000 Architectural Simulator.
5 
 *
6 
 *    This program is free software; you can redistribute it and/or modify
7 
 *    it under the terms of the GNU General Public License as published by
8 
 *    the Free Software Foundation; either version 2 of the License, or
9 
 *    (at your option) any later version.
10 
 *
11 
 *    This program is distributed in the hope that it will be useful,
12 
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 
 *    GNU General Public License for more details.
15 
 *
16 
 *    You should have received a copy of the GNU General Public License
17 
 *    along with this program; if not, write to the Free Software
18 
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19 
 
20 
#include <stdio.h>
21 
#include <stdlib.h>
22 
#include <stdarg.h>
23 
#include <assert.h>
24 1308 phoenix 
 
25 1350 nogj 
#include "config.h"
26 
 
27 
#ifdef HAVE_INTTYPES_H
28 
#include <inttypes.h>
29 
#endif
30 
 
31 
#include "port.h"
32 
#include "arch.h"
33 1308 phoenix 
#include "abstract.h"
34 1244 hpanther 
#include "cuc.h"
35 
#include "insn.h"
36 
#include "profiler.h"
37 
#include "sim-config.h"
38 1555 nogj 
#include "misc.h"
39 1244 hpanther 
 
40 
/* Shortcut */
41 
#define GEN(x...) fprintf (fo, x)
42 
 
43 
/* Find index of load/store/call */
44 
int find_lsc_index (cuc_func *f, int ref)
45 
{
46 
  int c = 0;
47 
  int i;
48 
  int load;
49 
 
50 
  if (f->INSN(ref).index == II_CALL) {
51 
    for (i = 0; i < f->nmsched; i++) {
52 
      if (f->msched[i] == ref) break;
53 
      if (f->mtype[i] & MT_CALL) c++;
54 
    }
55 
  } else {
56 
    load = II_IS_LOAD (f->INSN(ref).index);
57 
    for (i = 0; i < f->nmsched; i++) {
58 
      if (f->msched[i] == ref) break;
59 
      if (load && (f->mtype[i] & MT_LOAD)
60 
       || !load && (f->mtype[i] & MT_STORE)) c++;
61 
    }
62 
  }
63 
  return c;
64 
}
65 
 
66 
/* Print out dependencies as verilog expression */
67 
void print_deps (FILE *fo, cuc_func *f, int b, dep_list *t, int registered)
68 
{
69 
  if (t) {
70 
    int first = 0;
71 
    while (t) {
72 
      if (f->INSN(t->ref).type & IT_MEMORY) {
73 
        GEN ("%s%c_end[%i]", first ? " && " : "",
74 
                  II_IS_LOAD (f->INSN(t->ref).index) ? 'l' : 's', find_lsc_index (f, t->ref));
75 
      } else if (f->INSN(t->ref).index == II_CALL) {
76 
        GEN ("%sf_end[%i]", first ? " && " : "", find_lsc_index (f, t->ref));
77 
      } else {
78 1308 phoenix 
        PRINTF ("print_deps: err %lx\n", t->ref);
79 1244 hpanther 
        assert (0);
80 
      }
81 
      first = 1;
82 
      t = t->next;
83 
    }
84 
  } else {
85 
    if (registered) GEN ("bb_start_r[%i]", b);
86 
    else GEN ("bb_start[%i]", b);
87 
  }
88 
}
89 
 
90 
char *print_op_v (cuc_func *f, char *s, int ref, int j)
91 
{
92 
  unsigned long op = f->INSN(ref).op[j];
93 
  unsigned long opt = f->INSN(ref).opt[j];
94 
  switch (opt & ~OPT_DEST) {
95 
    case OPT_NONE: assert (0); break;
96 
    case OPT_CONST: if (f->INSN(ref).type & IT_COND && (f->INSN(ref).index == II_CMOV
97 
                     || f->INSN(ref).index == II_ADD)) {
98 
                      assert (op == 0 || op == 1);
99 1308 phoenix 
                      sprintf (s, "1'b%lx", op);
100 
                    } else sprintf (s, "32'h%lx", op);
101 1244 hpanther 
                    break;
102 
    case OPT_REGISTER:
103 
                    if (opt & OPT_DEST) sprintf (s, "t%x_%x", REF_BB(ref), REF_I(ref));
104 1308 phoenix 
                    else sprintf (s, "r%li_%c", op, opt & OPT_DEST ? 'o' : 'i');
105 1244 hpanther 
                    break;
106 
#if 0
107 
    case OPT_FREG:  assert (opt & OPT_DEST);
108 
                    sprintf (s, "fr%i_o", op);
109 
                    break;
110 
#endif
111 1308 phoenix 
    case OPT_REF:   sprintf (s, "t%lx_%lx", REF_BB(op), REF_I(op)); break;
112 1244 hpanther 
  }
113 
  return s;
114 
}
115 
 
116 
/* Prints out specified instruction */
117 
void print_insn_v (FILE *fo, cuc_func *f, int b, int i)
118 
{
119 
  cuc_insn *ii = &f->bb[b].insn[i];
120 
  char *s = known[ii->index].rtl;
121 
  char tmp[200] = "";
122 
 
123 
  assert (s);
124 
  while (*s) {
125 
    if (*s <= MAX_OPERANDS) {
126 
      char t[30];
127 
      sprintf (tmp, "%s%s", tmp, print_op_v (f, t, REF(b, i), *s - 1));
128 
    } else if (*s == '\b') sprintf (tmp, "%s%i", b);
129 
    else sprintf (tmp, "%s%c", tmp, *s);
130 
    s++;
131 
  }
132 
  GEN ("%-40s /* %s */\n", tmp, ii->disasm);
133 
  if (ii->type & IT_MEMORY) {
134 1308 phoenix 
    int nls = find_lsc_index (f, REF (b, i));
135 1244 hpanther 
    if (II_IS_LOAD (ii->index)) {
136 
      int nm;
137 
      for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;
138 
      assert (nm < f->nmsched);
139 
 
140 
      GEN ("  if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
141 
      switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {
142 
        case 1: GEN ("l_dat_i & 32'hff;\n");
143 
                break;
144 
        case 2: GEN ("l_dat_i & 32'hffff;\n");
145 
                break;
146 
        case 4 | MT_SIGNED:
147 
        case 4: GEN ("l_dat_i;\n");
148 
                break;
149 
        case 1 | MT_SIGNED:
150 
                GEN ("{24{l_dat_i[7]}, l_dat_i[7:0]};\n");
151 
                break;
152 
        case 2 | MT_SIGNED:
153 
                GEN ("{16{l_dat_i[15]}, l_dat_i[15:0]};\n");
154 
                break;
155 
        default: assert (0);
156 
      }
157 
    }
158 
  } else if (ii->index == II_LRBB) {
159 
    GEN ("  if (rst) t%x_%x <= #Tp 1'b0;\n", b, i);
160 
    assert (f->bb[b].prev[0] >= 0);
161 
    if (f->bb[b].prev[0] == BBID_START)
162 
      GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp start_i;\n", b, b, i);
163 
    else
164 
      GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp bb_stb[%i];\n", b, b, i, f->bb[b].prev[0]);
165 
  } else if (ii->index == II_REG) {
166 
    assert (ii->opt[1] == OPT_REF);
167 
    GEN ("  if (");
168 
    if (f->bb[b].mdep) print_deps (fo, f, b, f->bb[b].mdep, 0);
169 
    else GEN ("bb_stb[%i]", b);
170 1308 phoenix 
    GEN (") t%x_%x <= #Tp t%lx_%lx;\n",  b, i,
171 1244 hpanther 
                    REF_BB (ii->op[1]), REF_I (ii->op[1]));
172 
  }
173 
}
174 
 
175 
/* Outputs binary number */
176 
static char *bin_str (unsigned long x, int len)
177 
{
178 
  static char bx[33];
179 
  char *s = bx;
180 
  while (len > 0) *s++ = '0' + ((x >> --len) & 1);
181 
  *s = '\0';
182 
  return bx;
183 
}
184 
 
185 
/* Returns index of branch instruction inside a block b */
186 
static int branch_index (cuc_bb *bb)
187 
{
188 
  int i;
189 
  for (i = bb->ninsn - 1; i >= 0; i--)
190 
    if (bb->insn[i].type & IT_BRANCH) return i;
191 
  return -1;
192 
}
193 
 
194 
static void print_turn_off_dep (FILE *fo, cuc_func *f, dep_list *dep)
195 
{
196 
  while (dep) {
197 
    assert (f->INSN(dep->ref).type & IT_MEMORY || f->INSN(dep->ref).index == II_CALL);
198 
    GEN ("      %c_stb[%i] <= #Tp 1'b0;\n", f->INSN(dep->ref).index == II_CALL ? 'f'
199 
            : II_IS_LOAD (f->INSN(dep->ref).index) ? 'l' : 's', find_lsc_index (f, dep->ref));
200 
    dep = dep->next;
201 
  }
202 
}
203 
 
204 
static int func_index (cuc_func *f, int ref)
205 
{
206 
  int i;
207 
  unsigned long addr;
208 
  assert (f->INSN(ref).index == II_CALL && f->INSN(ref).opt[0] & OPT_CONST);
209 
  addr = f->INSN(ref).op[0];
210 
  for (i = 0; i < f->nfdeps; i++)
211 
    if (f->fdeps[i]->start_addr == addr) return i;
212 
 
213 
  assert (0);
214 
  return -1;
215 
}
216 
 
217 
/* Generates verilog file out of insn dataflow */
218 
void output_verilog (cuc_func *f, char *filename, char *funcname)
219 
{
220 
  FILE *fo;
221 
  int b, i, j;
222 
  int ci = 0, co = 0;
223 
  int nloads = 0, nstores = 0, ncalls = 0;
224 
  char tmp[256];
225 
  sprintf (tmp, "%s.v", filename);
226 
 
227 
  log ("Generating verilog file \"%s\"\n", tmp);
228 
  PRINTF ("Generating verilog file \"%s\"\n", tmp);
229 
  if ((fo = fopen (tmp, "wt+")) == NULL) {
230 
    fprintf (stderr, "Cannot open '%s'\n", tmp);
231 
    exit (1);
232 
  }
233 
 
234 
  /* output header */
235 
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
236 
  GEN ("   (C) 2002 Opencores\n");
237 
  GEN ("   function   \"%s\"\n", funcname);
238 1308 phoenix 
  GEN ("   at         %08lx - %08lx\n", f->start_addr, f->end_addr);
239 1244 hpanther 
  GEN ("   num BBs    %i */\n\n", f->num_bb);
240 
 
241 
  GEN ("`include \"timescale.v\"\n\n");
242 
  GEN ("module %s (clk, rst,\n", filename);
243 
  GEN ("              l_adr_o, l_dat_i, l_req_o,\n");
244 
  GEN ("              l_sel_o, l_linbrst_o, l_rdy_i,\n");
245 
  GEN ("              s_adr_o, s_dat_o, s_req_o,\n");
246 
  GEN ("              s_sel_o, s_linbrst_o, s_rdy_i,\n");
247 
 
248 
  GEN ("/* inputs */  ");
249 
  for (i = 0; i < MAX_REGS; i++)
250 
    if (f->used_regs[i]) {
251 
      GEN ("r%i_i, ", i);
252 
      ci++;
253 
    }
254 
  if (!ci) GEN ("/* NONE */");
255 
 
256 
  GEN ("\n/* outputs */ ");
257 
  for (i = 0; i < MAX_REGS; i++)
258 
    if (f->lur[i] >= 0 && !f->saved_regs[i]) {
259 
      GEN ("r%i_o, ", i);
260 
      co++;
261 
    }
262 
 
263 
  if (!co) GEN ("/* NONE */");
264 
  if (f->nfdeps) {
265 
    GEN ("\n/* f. calls */, fstart_o, %sfend_i, fr11_i, ",
266 
                    log2_int (f->nfdeps) > 0 ? "fid_o, " : "");
267 
    for (i = 0; i < 6; i++) GEN ("fr%i_o, ", i + 3);
268 
  }
269 
  GEN ("\n              start_i, end_o, busy_o);\n\n");
270 
 
271 
  GEN ("parameter Tp = 1;\n\n");
272 
 
273 
  GEN ("input         clk, rst;\n");
274 
  GEN ("input         start_i;\t/* Module starts when set to 1 */ \n");
275 
  GEN ("output        end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n");
276 
  GEN ("output        busy_o;\t/* Set when module should not be interrupted */\n");
277 
  GEN ("\n/* Bus signals */\n");
278 
  GEN ("output        l_req_o, s_req_o;\n");
279 
  GEN ("input         l_rdy_i, s_rdy_i;\n");
280 
  GEN ("output  [3:0] l_sel_o, s_sel_o;\n");
281 
  GEN ("output [31:0] l_adr_o, s_adr_o;\n");
282 
  GEN ("output        l_linbrst_o, s_linbrst_o;\n");
283 
  GEN ("input  [31:0] l_dat_i;\n");
284 
  GEN ("output [31:0] s_dat_o;\n\n");
285 
 
286 
  GEN ("reg           l_req_o, s_req_o;\n");
287 
  GEN ("reg    [31:0] l_adr_o, s_adr_o;\n");
288 
  GEN ("reg     [3:0] l_sel_o, s_sel_o;\n");
289 
  GEN ("reg    [31:0] s_dat_o;\n");
290 
  GEN ("reg           l_linbrst_o, s_linbrst_o;\n");
291 
 
292 
  if (ci || co) GEN ("\n/* module ports */\n");
293 
  if (ci) {
294 
    int first = 1;
295 
    GEN ("input  [31:0]");
296 
    for (i = 0; i < MAX_REGS; i++)
297 
      if (f->used_regs[i]) {
298 
        GEN ("%sr%i_i", first ? " " : ", ", i);
299 
        first = 0;
300 
      }
301 
    GEN (";\n");
302 
  }
303 
 
304 
  if (co) {
305 
    int first = 1;
306 
    GEN ("output [31:0]");
307 
    for (i = 0; i < MAX_REGS; i++)
308 
      if (f->lur[i] >= 0 && !f->saved_regs[i]) {
309 
        GEN ("%sr%i_o", first ? " " : ", ", i);
310 
        first = 0;
311 
      }
312 
    GEN (";\n");
313 
  }
314 
 
315 
  if (f->nfdeps) {
316 
    GEN ("\n/* Function calls */\n");
317 
    GEN ("output [31:0] fr3_o");
318 
    for (i = 1; i < 6; i++) GEN (", fr%i_o", i + 3);
319 
    GEN (";\n");
320 
    GEN ("input  [31:0] fr11_i;\n");
321 
    if (log2_int(f->nfdeps) > 0) GEN ("output [%i:0] fid_o;\n", log2_int(f->nfdeps));
322 
    GEN ("output        fstart_o;\n");
323 
    GEN ("input         fend_i;\n");
324 
  }
325 
 
326 
  /* Count loads & stores */
327 
  for (i = 0; i < f->nmsched; i++)
328 
    if (f->mtype[i] & MT_STORE) nstores++;
329 
    else if (f->mtype[i] & MT_LOAD) nloads++;
330 
    else if (f->mtype[i] & MT_CALL) ncalls++;
331 
 
332 
  /* Output internal registers for loads */
333 
  if (nloads) {
334 
    int first = 1;
335 
    int num = 0;
336 
    GEN ("\n/* internal registers for loads */\n");
337 
    for (i = 0; i < f->nmsched; i++)
338 
      if (f->mtype[i] & MT_LOAD) {
339 
        GEN ("%st%x_%x", first ? "reg    [31:0] " : ", ",
340 
                REF_BB(f->msched[i]), REF_I(f->msched[i]));
341 
 
342 
        if (num >= 8) {
343 
          GEN (";\n");
344 
          first = 1;
345 
          num = 0;
346 
        } else {
347 
          first = 0;
348 
          num++;
349 
        }
350 
      }
351 
    if (!first) GEN (";\n");
352 
  }
353 
 
354 
  /* Internal register for function return value */
355 
  if (f->nfdeps) {
356 
    GEN ("\n/* Internal register for function return value */\n");
357 
    GEN ("reg     [31:0] fr11_r;\n");
358 
  }
359 
 
360 
  GEN ("\n/* 'zero or one' hot state machines */\n");
361 
  if (nloads) GEN ("reg     [%i:0] l_stb; /* loads */\n", nloads - 1);
362 
  if (nstores) GEN ("reg     [%i:0] s_stb; /* stores */\n", nstores - 1);
363 
  GEN ("reg     [%i:0] bb_stb; /* basic blocks */\n", f->num_bb - 1);
364 
 
365 
  {
366 
    int first = 2;
367 
    int num = 0;
368 
    for (b = 0; b < f->num_bb; b++)
369 
      for (i = 0; i < f->bb[b].ninsn; i++)
370 
        if (f->bb[b].insn[i].type & IT_COND
371 
         && f->bb[b].insn[i].index != II_REG
372 
         && f->bb[b].insn[i].index != II_LRBB) {
373 
          if (first == 2) GEN ("\n/* basic block condition wires */\n");
374 
          GEN ("%st%x_%x", first ? "wire          " : ", ", b, i);
375 
          if (num >= 8) {
376 
            GEN (";\n");
377 
            first = 1;
378 
            num = 0;
379 
          } else {
380 
            first = 0;
381 
            num++;
382 
          }
383 
        }
384 
    if (!first) GEN (";\n");
385 
 
386 
    GEN ("\n/* forward declaration of normal wires */\n");
387 
    num = 0;
388 
    first = 1;
389 
    for (b = 0; b < f->num_bb; b++)
390 
      for (i = 0; i < f->bb[b].ninsn; i++)
391 
        if (!(f->bb[b].insn[i].type & (IT_COND | IT_BRANCH))
392 
         && f->bb[b].insn[i].index != II_REG
393 
         && f->bb[b].insn[i].index != II_LRBB) {
394 
          /* Exclude loads */
395 
          if (f->bb[b].insn[i].type & IT_MEMORY && II_IS_LOAD (f->bb[b].insn[i].index)) continue;
396 
          GEN ("%st%x_%x", first ? "wire   [31:0] " : ", ", b, i);
397 
          if (num >= 8) {
398 
            GEN (";\n");
399 
            first = 1;
400 
            num = 0;
401 
          } else {
402 
            first = 0;
403 
            num++;
404 
          }
405 
        }
406 
    if (!first) GEN (";\n");
407 
 
408 
    GEN ("\n/* forward declaration registers */\n");
409 
    num = 0;
410 
    first = 1;
411 
    for (b = 0; b < f->num_bb; b++)
412 
      for (i = 0; i < f->bb[b].ninsn; i++)
413 
        if (f->bb[b].insn[i].index == II_REG
414 
         && f->bb[b].insn[i].index != II_LRBB) {
415 
          GEN ("%st%x_%x", first ? "reg    [31:0] " : ", ", b, i);
416 
          if (num >= 8) {
417 
            GEN (";\n");
418 
            first = 1;
419 
            num = 0;
420 
          } else {
421 
            first = 0;
422 
            num++;
423 
          }
424 
        }
425 
    if (!first) GEN (";\n");
426 
 
427 
    num = 0;
428 
    first = 1;
429 
    for (b = 0; b < f->num_bb; b++)
430 
      for (i = 0; i < f->bb[b].ninsn; i++)
431 
        if (f->bb[b].insn[i].index != II_REG
432 
         && f->bb[b].insn[i].index == II_LRBB) {
433 
          GEN ("%st%x_%x", first ? "reg           " : ", ", b, i);
434 
          if (num >= 8) {
435 
            GEN (";\n");
436 
            first = 1;
437 
            num = 0;
438 
          } else {
439 
            first = 0;
440 
            num++;
441 
          }
442 
        }
443 
    if (!first) GEN (";\n");
444 
  }
445 
 
446 
  if (nloads || nstores) GEN ("\n/* dependencies */\n");
447 
  if (nloads) GEN ("wire    [%i:0] l_end = l_stb & {%i{l_rdy_i}};\n",
448 
                  nloads - 1, nloads);
449 
  if (nstores) GEN ("wire    [%i:0] s_end = s_stb & {%i{s_rdy_i}};\n",
450 
                  nstores - 1, nstores);
451 
  if (ncalls) GEN ("wire    [%i:0] f_end = f_stb & {%i{fend_i}};\n",
452 
                  ncalls - 1, ncalls);
453 
 
454 
  GEN ("\n/* last dependency */\n");
455 
  GEN ("wire   end_o = ");
456 
  for (b = 0; b < f->num_bb; b++) {
457 
    for (i = 0; i < 2; i++) if (f->bb[b].next[i] == BBID_END) {
458 
      GEN ("bb_stb[%i]", b);
459 
      if (f->bb[b].mdep) {
460 
        GEN (" && ");
461 
        print_deps (fo, f, b, f->bb[b].mdep, 0);
462 
      }
463 
      /* Is branch to BBID_END conditional? */
464 
      if (f->bb[b].next[1 - i] >= 0) {
465 
        int bidx = branch_index (&f->bb[b]);
466 
        char t[30];
467 
        print_op_v (f, t, REF (b, bidx), 1);
468 
        GEN (" && %s%s", i ? "" : "!", t);
469 
      }
470 
    }
471 
  }
472 
  GEN (";\n");
473 
  GEN ("wire   busy_o = |bb_stb;\n");
474 
 
475 
 
476 
  GEN ("\n/* Basic block triggers */\n");
477 
  GEN ("wire   [%2i:0] bb_start = {\n", f->num_bb - 1);
478 
  for (b = f->num_bb - 1; b >= 0; b--) {
479 
    GEN ("    /* bb_start[%2i] */ ", b);
480 
    for (i = 0; i < 2; i++) if (f->bb[b].prev[i] >= 0 && f->bb[b].prev[i] != BBID_START) {
481 
      cuc_bb *prev = &f->bb[f->bb[b].prev[i]];
482 
      int t;
483 
      if (i) GEN ("\n                    || ");
484 
      if (prev->mdep) {
485 
        print_deps (fo, f, f->bb[b].prev[i], prev->mdep, 0);
486 
        GEN (" && ");
487 
      }
488 
      GEN ("bb_stb[%i]", f->bb[b].prev[i]);
489 
      if (prev->next[0] >= 0 && prev->next[0] != BBID_END
490 
       && prev->next[1] >= 0 && prev->next[1] != BBID_END) {
491 
        int bi = REF (f->bb[b].prev[i], branch_index (&f->bb[f->bb[b].prev[i]]));
492 
        int ci;
493 
        assert (bi >= 0);
494 
        ci = f->INSN(bi).op[1];
495 
        t = prev->next[0] == b;
496 
        GEN (" && ");
497 
        if (f->INSN(bi).opt[1] & OPT_REF) {
498 
          GEN ("%st%x_%x", t ? "" : "!", REF_BB(ci), REF_I(ci));
499 
        } else {
500 
          cucdebug (5, "%x!%x!%x\n", bi, ci, f->INSN(bi).opt[1]);
501 
          assert (f->INSN(bi).opt[1] & OPT_CONST);
502 
          GEN ("%s%i", t ? "" : "!", ci);
503 
        }
504 
      }
505 
    } else break;
506 
    if (!i) GEN ("start_i");
507 
    if (b == 0) GEN ("};\n");
508 
    else GEN (",\n");
509 
  }
510 
 
511 
  GEN ("\n/* Register the bb_start */\n");
512 
  GEN ("reg   [%2i:0] bb_start_r;\n\n", f->num_bb - 1);
513 
  GEN ("always @(posedge rst or posedge clk)\n");
514 
  GEN ("begin\n");
515 
  GEN ("  if (rst) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
516 
  GEN ("  else if (end_o) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
517 
  GEN ("  else bb_start_r <= #Tp bb_start;\n");
518 
  GEN ("end\n");
519 
 
520 
  GEN ("\n/* Logic */\n");
521 
  /* output body */
522 
  for (b = 0; b < f->num_bb; b++) {
523 
    GEN ("\t\t/* BB%i */\n", b);
524 
    for (i = 0; i < f->bb[b].ninsn; i++)
525 
      print_insn_v (fo, f, b, i);
526 
    GEN ("\n");
527 
  }
528 
 
529 
  if (co) {
530 
    GEN ("\n/* Outputs */\n");
531 
    for (i = 0; i < MAX_REGS; i++)
532 
      if (f->lur[i] >= 0 && !f->saved_regs[i])
533 
        GEN ("assign r%i_o = t%x_%x;\n", i, REF_BB(f->lur[i]),
534 
                        REF_I(f->lur[i]));
535 
  }
536 
 
537 
  if (nstores) {
538 
    int cur_store;
539 
    GEN ("\n/* Memory stores */\n");
540 
    GEN ("always @(s_stb");
541 
    for (i = 0; i < f->nmsched; i++)
542 
      if (f->mtype[i] & MT_STORE) {
543 
        char t[30];
544 
        unsigned long opt = f->INSN(f->msched[i]).opt[0];
545 
        if ((opt & ~OPT_DEST) != OPT_CONST) {
546 
          GEN (" or %s", print_op_v (f, t, f->msched[i], 0));
547 
        }
548 
      }
549 
 
550 
    cur_store = 0;
551 
    GEN (")\nbegin\n");
552 
    for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_STORE) {
553 
      char t[30];
554 
      GEN ("  %sif (s_stb[%i]) s_dat_o = %s;\n", cur_store == 0 ? "" : "else ", cur_store,
555 
                      print_op_v (f, t, f->msched[i], 0));
556 
      cur_store++;
557 
      //PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
558 
    }
559 
    GEN ("  else s_dat_o = 32'hx;\n");
560 
    GEN ("end\n");
561 
  }
562 
 
563 
  /* Generate load and store state machine */
564 
#if 0
565 
  GEN ("\n/* Load&store state machine */\n");
566 
  GEN ("always @(posedge clk or posedge rst)\n");
567 
  GEN ("  if (rst) begin\n");
568 
  if (nloads) GEN ("    l_stb <= #Tp %i'h0;\n", nloads);
569 
  if (nstores) GEN ("    s_stb <= #Tp %i'h0;\n", nstores);
570 
  GEN ("  end else begin\n");
571 
  for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_LOAD || f->mtype[i] & MT_STORE) {
572 
    int cur = 0;
573 
    dep_list *dep = f->INSN(f->msched[i]).dep;
574 
    assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
575 
    GEN ("    if (");
576 
    print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
577 
    GEN (") begin\n");
578 
    print_turn_off_dep (fo, f, dep);
579 
    GEN ("      %c_stb[%i] <= #Tp 1'b1;\n", f->mtype[i] & MT_LOAD ? 'l' : 's', cur++);
580 
    GEN ("    end\n");
581 
  }
582 
  GEN ("    if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
583 
  GEN ("  end\n");
584 
#endif
585 
 
586 
  /* Generate state generator machine */
587 
  for (j = 0; j < 2; j++) {
588 
    char c;
589 
    char *s;
590 
 
591 
    switch (j) {
592 
      case 0: c = 'l'; s = "Load"; break;
593 
      case 1: c = 's'; s = "Store"; break;
594 
      case 2: c = 'c'; s = "Calls"; break;
595 
    }
596 
    if (j == 0 && nloads
597 
     || j == 1 && nstores
598 
     || j == 2 && ncalls) {
599 
      int cur = 0;
600 
      char t[30];
601 
 
602 
      GEN ("\n/* %s state generator machine */\n", s);
603 
      GEN ("always @(");
604 
      for (i = 0; i < f->nmsched; i++) {
605 
        print_op_v (f, t, f->msched[i], 1);
606 
        GEN ("%s or ", t);
607 
      }
608 
      GEN ("bb_start_r");
609 
      if (nloads) GEN (" or l_end");
610 
      if (nstores) GEN (" or s_end");
611 
      GEN (")\n");
612 
      GEN ("begin\n  ");
613 
      cucdebug (1, "%s\n", s);
614 
      for (i = 0; i < f->nmsched; i++)
615 
        if (j == 0 && f->mtype[i] & MT_LOAD
616 
         || j == 1 && f->mtype[i] & MT_STORE
617 
         || j == 2 && f->mtype[i] & MT_CALL) {
618 
        cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
619 
        assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
620 
        GEN ("if (");
621 
        print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
622 
        GEN (") begin\n");
623 
        GEN ("    %c_req_o = 1'b1;\n", c);
624 
        GEN ("    %c_sel_o[3:0] = 4'b", c);
625 
        switch (f->mtype[i] & MT_WIDTH) {
626 
          case 1: GEN ("0001 << (%s & 32'h3);\n",
627 
                                  print_op_v (f, t, f->msched[i], 1)); break;
628 
          case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
629 
                                  print_op_v (f, t, f->msched[i], 1)); break;
630 
          case 4: GEN ("1111;\n"); break;
631 
          default: assert (0);
632 
        }
633 
        GEN ("    %c_linbrst_o = 1'b%i;\n", c,
634 
                      (f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
635 1308 phoenix 
        GEN ("    %c_adr_o = t%lx_%lx & ~32'h3;\n", c,
636 1244 hpanther 
                      REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
637 
        GEN ("  end else ");
638 
      }
639 
      GEN ("if (%c_end[%i]) begin\n", c, cur - 1);
640 
      GEN ("    %c_req_o = 1'b0;\n", c);
641 
      GEN ("    %c_sel_o[3:0] = 4'bx;\n", c);
642 
      GEN ("    %c_linbrst_o = 1'b0;\n", c);
643 
      GEN ("    %c_adr_o = 32'hx;\n", c);
644 
      GEN ("  end else begin\n");
645 
      GEN ("    %c_req_o = 1'b0;\n", c);
646 
      GEN ("    %c_sel_o[3:0] = 4'bx;\n", c);
647 
      GEN ("    %c_linbrst_o = 1'b0;\n", c);
648 
      GEN ("    %c_adr_o = 32'hx;\n", c);
649 
      GEN ("  end\n");
650 
      GEN ("end\n");
651 
    }
652 
  }
653 
 
654 
  if (ncalls) {
655 
    int cur_call = 0;
656 
    GEN ("\n/* Function calls state machine */\n");
657 
    GEN ("always @(posedge clk or posedge rst)\n");
658 
    GEN ("begin\n");
659 
    GEN ("  if (rst) begin\n");
660 
    GEN ("    f_stb <= #Tp %i'h0;\n", nstores);
661 
    for (i = 0; i < 6; i++) GEN ("    fr%i_o <= #Tp 32'h0;\n", i + 3);
662 
    if (log2_int(ncalls)) GEN ("    fid_o <= #Tp %i'h0;\n", log2_int (f->nfdeps));
663 
    GEN ("    fstart_o <= #Tp 1'b0;\n");
664 
    //GEN ("    f11_r <= #Tp 32'h0;\n");
665 
    GEN ("  end else begin\n");
666 
    cucdebug (1, "calls \n");
667 
    for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_CALL) {
668 
      dep_list *dep = f->INSN(f->msched[i]).dep;
669 
      cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
670 
      assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
671 
      GEN ("    if (");
672 
      print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
673 
      GEN (") begin\n");
674 
      print_turn_off_dep (fo, f, dep);
675 
      GEN ("      f_stb[%i] <= #Tp 1'b1;\n", cur_call++);
676 
      GEN ("      fstart_o <= #Tp 1'b1;\n");
677 
      if (log2_int (f->nfdeps))
678 
        GEN ("      fid_o <= #Tp %i'h%x;\n", log2_int (f->nfdeps), func_index (f, f->msched[i]));
679 
 
680 
      for (j = 0; j < 6; j++)
681 
        GEN ("      fr%i_o <= #Tp t%x_%x;\n", j + 3,
682 
                       REF_BB (f->msched[i]), REF_I (f->msched[i]) - 6 + i);
683 
      GEN ("    end\n");
684 
    }
685 
    GEN ("    if (f_end[%i]) begin\n", ncalls - 1);
686 
    GEN ("      f_stb <= #Tp %i'h0;\n", ncalls);
687 
    GEN ("      f_start_o <= #Tp 1'b0;\n");
688 
    GEN ("    end\n");
689 
    GEN ("  end\n");
690 
    GEN ("end\n");
691 
  }
692 
 
693 
  GEN ("\n/* Basic blocks state machine */\n");
694 
  GEN ("always @(posedge clk or posedge rst)\n");
695 
  GEN ("begin\n");
696 
  GEN ("  if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
697 
  GEN ("  else if (end_o) begin\n");
698 
  GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
699 
  for (i = 0; i < f->num_bb; i++) {
700 
    GEN ("  end else if (bb_start[%i]) begin\n", i);
701 
    GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
702 
  }
703 
  GEN ("  end else if (end_o) begin\n");
704 
  GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
705 
  GEN ("  end\n");
706 
  GEN ("end\n");
707 
 
708 
  /* output footer */
709 
  GEN ("\nendmodule\n");
710 
 
711 
  fclose (fo);
712 
}
713 
 
714 
void generate_main (int nfuncs, cuc_func **f, char *filename)
715 
{
716 
  FILE *fo;
717 
  int i, j, nrf, first;
718 
  char tmp[256];
719 
  int ncallees[MAX_FUNCS];
720 
  int nl[MAX_FUNCS], ns[MAX_FUNCS];
721 
  int maxncallees = 0;
722 
  sprintf (tmp, "%s_top.v", filename);
723 
 
724 
  for (i = 0, nrf = 0; i < nfuncs; i++) {
725 
    nl[i] = ns[i] = 0;
726 
    ncallees[i] = 0;
727 
    if (f[i]) {
728 
      f[i]->tmp = nrf++;
729 
      for (j = 0; j < f[i]->nmsched; j++)
730 
        if (f[i]->mtype[j] & MT_LOAD) nl[i]++;
731 
        else if (f[i]->mtype[j] & MT_STORE) ns[i]++;
732 
      for (j = 0; j < f[i]->nfdeps; j++)
733 
        ncallees[f[i]->fdeps[j]->tmp]++;
734 
    }
735 
  }
736 
  if (!nrf) return;
737 
 
738 
  for (i = 0; i < nrf; i++)
739 
    if (maxncallees < ncallees[i]) maxncallees = ncallees[i];
740 
 
741 
  log ("Generating verilog file \"%s\"\n", tmp);
742 
  PRINTF ("Generating verilog file \"%s\"\n", tmp);
743 
  if ((fo = fopen (tmp, "wt+")) == NULL) {
744 
    fprintf (stderr, "Cannot open '%s'\n", tmp);
745 
    exit (1);
746 
  }
747 
 
748 
  /* output header */
749 
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
750 
  GEN ("   (C) 2002 Opencores */\n\n");
751 
  GEN ("/* Includes %i functions:", nrf);
752 
  for (i = 0; i < nfuncs; i++) if (f[i])
753 
    GEN ("\n%s", prof_func[i].name);
754 
  GEN (" */\n\n");
755 
 
756 
  GEN ("`include \"timescale.v\"\n\n");
757 
  GEN ("module %s (clk, rst,\n", filename);
758 
  GEN ("              /* Load and store master Wishbone ports */\n");
759 
  GEN ("              l_adr_o, l_dat_i, l_cyc_o, l_stb_o,\n");
760 
  GEN ("              l_sel_o, l_linbrst_o, l_rdy_i, l_we_o,\n");
761 
  GEN ("              s_adr_o, s_dat_o, s_cyc_o, s_stb_o,\n");
762 
  GEN ("              s_sel_o, s_linbrst_o, s_rdy_i, s_we_o,\n\n");
763 
  GEN ("              /* cuc interface */\n");
764 
  GEN ("              cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_rdy_o);\n\n");
765 
 
766 
  GEN ("parameter Tp = 1;\n");
767 
  GEN ("\n/* module ports */\n");
768 
  GEN ("input         clk, rst, cuc_stb_i, cuc_we_i;\n");
769 
  GEN ("input         l_rdy_i, s_rdy_i;\n");
770 
  GEN ("output        l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
771 
  GEN ("reg           l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
772 
  GEN ("output        s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
773 
  GEN ("reg           s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
774 
  GEN ("output        cuc_rdy_o; /* Not registered ! */\n");
775 
  GEN ("output  [3:0] l_sel_o, s_sel_o;\n");
776 
  GEN ("reg     [3:0] l_sel_o, s_sel_o;\n");
777 
  GEN ("output [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
778 
  GEN ("reg    [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
779 
  GEN ("input  [15:0] cuc_adr_i;\n");
780 
  GEN ("input  [31:0] l_dat_i, cuc_dat_i;\n\n");
781 
 
782 
  GEN ("wire   [%2i:0] i_we, i_re, i_finish, i_selected, i_first_reg;\n", nrf - 1);
783 
  GEN ("wire   [%2i:0] i_bidok, i_start_bid, i_start_bidok, main_start, main_end;\n", nrf - 1);
784 
  GEN ("wire   [%2i:0] i_start, i_end, i_start_block, i_busy;\n", nrf - 1);
785 
  GEN ("wire   [%2i:0] i_l_req, i_s_req;\n", nrf - 1);
786 
  GEN ("reg    [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
787 
 
788 
  GEN ("assign i_selected = {\n");
789 
  for (i = 0; i < nrf; i++)
790 
    GEN ("    cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
791 
 
792 
  GEN ("assign i_first_reg = {\n");
793 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
794 
    for (j = 0; j <= MAX_REGS; j++) if (f[i]->used_regs[j]) break;
795 
    GEN ("    cuc_adr_i[5:0] == %i%s\n", j, f[i]->tmp < nrf - 1 ? "," : "};");
796 
  }
797 
 
798 
  GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
799 
  GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
800 
 
801 
  GEN ("assign i_start = i_go_bsy & {%i{cuc_rdy_o}};\n", nrf);
802 
  GEN ("assign i_start_bidok = {\n");
803 
  for (i = 0; i < nrf; i++)
804 
    GEN ("    i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
805 
  GEN ("assign main_start = i_start & i_selected & i_first_reg & i_we;\n");
806 
  GEN ("assign main_end = {%i{i_end}} & i_selected;\n");
807 
 
808 
  GEN ("\nalways @(posedge clk or posedge rst)\n");
809 
  GEN ("begin\n");
810 
  GEN ("  if (rst) i_go_bsy <= #Tp %i'b0;\n", nrf);
811 
  GEN ("  else i_go_bsy <= #Tp i_we | ~i_finish & i_go_bsy;\n");
812 
  GEN ("end\n");
813 
 
814 
 
815 
  /* Function specific data */
816 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
817 
    int ci = 0, co = 0;
818 
    int fn = f[i]->tmp;
819 
    GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
820 
    for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j]) {
821 
      GEN ("%s i%i_r%ii", first ? "/* inputs */\nreg    [31:0]" : ",", fn, j);
822 
      first = 0;
823 
      ci++;
824 
    }
825 
    if (ci) GEN (";\n");
826 
 
827 
    for (j = 0, first = 1; j < MAX_REGS; j++)
828 
      if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) {
829 
        GEN ("%s i%i_r%io", first ? "/* outputs */\nwire   [31:0]" : ",", fn, j);
830 
        first = 0;
831 
        co++;
832 
      }
833 
    if (co) GEN (";\n");
834 
    GEN ("wire [31:0] i%i_l_adr, i%i_s_adr;\n", fn, fn);
835 
 
836 
    GEN ("always @(posedge clk or posedge rst)\n");
837 
    GEN ("  if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
838 
    GEN ("  else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
839 
 
840 
    if (ci) {
841 
      GEN ("\n/* write register access */\n");
842 
      GEN ("always @(posedge clk or posedge rst)\n");
843 
      GEN ("begin\n");
844 
      GEN ("  if (rst) begin\n");
845 
      for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
846 
        GEN ("    i%i_r%ii <= #Tp 32'h0;\n", fn, j);
847 
      GEN ("  end else if (!i_go_bsy[%i] && i_we[%i])\n", fn, fn);
848 
      GEN ("    case (cuc_adr_i[5:0])\n");
849 
      for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
850 
        GEN ("      %-2i: i%i_r%ii <= #Tp cuc_dat_i;\n", j, fn, j);
851 
      GEN ("    endcase\n");
852 
      GEN ("end\n");
853 
    }
854 
 
855 
    GEN ("\n");
856 
  }
857 
 
858 
  /* Generate machine for reading all function registers. Register read can be
859 
     delayed till function completion */
860 
  {
861 
    int co;
862 
    GEN ("/* read register access - data */\n");
863 
    GEN ("always @(posedge clk or posedge rst)\n");
864 
    GEN ("  if (rst) cuc_dat_o <= #Tp 32'h0;\n");
865 
    GEN ("  else if (cuc_stb_i && cuc_we_i) begin\n");
866 
    GEN ("    ");
867 
 
868 
    for (i = 0; i < nfuncs; i++) if (f[i]) {
869 
      co = 0;
870 
      for (j = 0; j < MAX_REGS; j++)
871 
        if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) co++;
872 
 
873 
      GEN ("if (cuc_adr_i[15:6] == %i)", f[i]->tmp);
874 
      if (co) {
875 
        first = 1;
876 
        GEN ("\n      case (cuc_adr_i[5:0])\n");
877 
        for (j = 0; j < MAX_REGS; j++)
878 
          if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
879 
            GEN ("        %-2i: cuc_dat_o <= #Tp i%i_r%io;\n", j, f[i]->tmp, j);
880 
        GEN ("      endcase\n");
881 
      } else {
882 
        GEN ("      cuc_dat_o <= #Tp 32'hx;\n");
883 
      }
884 
      GEN ("    else ");
885 
    }
886 
    GEN ("cuc_dat_o <= #Tp 32'hx;\n");
887 
    GEN ("  end else cuc_dat_o <= #Tp 32'hx;\n");
888 
 
889 
    GEN ("\n/* read register access - acknowledge */\n");
890 
    GEN ("assign cuc_rdy_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
891 
  }
892 
 
893 
  /* Store/load Wishbone bridge */
894 
  for (j = 0; j < 2; j++) {
895 
    char t = j ? 's' : 'l';
896 
    GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
897 
    GEN ("reg [%i:0] %cm_sel;\n", log2_int (nrf), t);
898 
    GEN ("reg [%i:0] %cm_bid;\n", log2_int (nrf), t);
899 
    GEN ("reg       %ccyc_ip;\n\n", t);
900 
    GEN ("always @(posedge clk)\n");
901 
    GEN ("begin\n");
902 
    GEN ("  %c_we_o <= #Tp 1'b%i;\n", t, j);
903 
    GEN ("  %c_cyc_o <= #Tp |i_%c_req;\n", t, t);
904 
    GEN ("  %c_stb_o <= #Tp |i_%c_req;\n", t, t);
905 
    GEN ("end\n");
906 
 
907 
    GEN ("\n/* highest bid */\n");
908 
    GEN ("always @(");
909 
    for (i = 0; i < nrf; i++) GEN ("%si_%c_req", i > 0 ? " or " : "", t);
910 
    GEN (")\n");
911 
    for (i = 0; i < nrf; i++) GEN ("  %sif (i_%c_req) %cm_bid = %i'h%x;\n",
912 
                    i ? "else " : "", t, t, log2_int (nrf) + 1, i);
913 
 
914 
    GEN ("\n/* selected transfer */\n");
915 
    GEN ("always @(posedge clk or posedge rst)\n");
916 
    GEN ("  if (rst) %cm_sel <= #Tp %i'h0;\n", t, log2_int (nrf) + 1);
917 
    GEN ("  else if (%c_rdy_i) %cm_sel <= #Tp %i'h0;\n", t, t, log2_int (nrf) + 1);
918 
    GEN ("  else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
919 
 
920 
    GEN ("\n/* Cycle */\n");
921 
    GEN ("\nalways @(posedge clk or posedge rst)\n");
922 
    GEN ("  if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
923 
    GEN ("  else if (%c_rdy_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
924 
    GEN ("  else %ccyc_ip <= #Tp %c_cyc_o;\n", t, t);
925 
  }
926 
 
927 
  GEN ("\n/* Acknowledge */\n");
928 
  for (i = 0; i < nrf; i++) {
929 
    GEN ("wire i%i_s_rdy = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & s_rdy_i;\n", i, i, i);
930 
    GEN ("wire i%i_l_rdy = ((lm_bid == %i & !lcyc_ip) | lm_sel == %i) & l_rdy_i;\n", i, i, i);
931 
  }
932 
 
933 
  GEN ("\n/* data, address selects and burst enables */\n");
934 
  for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_s_dat;\n", i);
935 
  for (i = 0; i < nrf; i++) GEN ("wire i%i_s_linbrst, i%i_l_linbrst;\n", i, i);
936 
  for (i = 0; i < nrf; i++) GEN ("wire [3:0]  i%i_s_sel, i%i_l_sel;\n", i, i);
937 
  for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_l_dat = l_dat_i;\n", i);
938 
  GEN ("\nalways @(posedge clk)\n");
939 
  GEN ("begin\n");
940 
  GEN ("  s_dat_o <= #Tp ");
941 
  for (i = 0; i < nrf - 1; i++)
942 
    GEN ("\n    sm_bid == %i ? i%i_s_dat : ", i, i);
943 
  GEN ("i%i_s_dat;\n", nrf - 1);
944 
  GEN ("  s_adr_o <= #Tp ");
945 
  for (i = 0; i < nrf - 1; i++)
946 
    GEN ("\n    sm_bid == %i ? i%i_s_adr : ", i, i);
947 
  GEN ("i%i_s_adr;\n", nrf - 1);
948 
  GEN ("  s_sel_o <= #Tp ");
949 
  for (i = 0; i < nrf - 1; i++)
950 
    GEN ("\n    sm_bid == %i ? i%i_s_sel : ", i, i);
951 
  GEN ("i%i_s_sel;\n", nrf - 1);
952 
  GEN ("  s_linbrst_o <= #Tp ");
953 
  for (i = 0; i < nrf - 1; i++)
954 
    GEN ("\n    sm_bid == %i ? i%i_s_linbrst : ", i, i);
955 
  GEN ("i%i_s_linbrst;\n", nrf - 1);
956 
  GEN ("end\n\n");
957 
 
958 
  GEN ("always @(posedge clk)\n");
959 
  GEN ("begin\n");
960 
  GEN ("  l_adr_o <= #Tp ");
961 
  for (i = 0; i < nrf - 1; i++)
962 
    GEN ("\n    lm_bid == %i ? i%i_l_adr : ", i, i);
963 
  GEN ("i%i_l_adr;\n", nrf - 1);
964 
  GEN ("  l_sel_o <= #Tp ");
965 
  for (i = 0; i < nrf - 1; i++)
966 
    GEN ("\n    lm_bid == %i ? i%i_l_sel : ", i, i);
967 
  GEN ("i%i_l_sel;\n", nrf - 1);
968 
  GEN ("  l_linbrst_o <= #Tp ");
969 
  for (i = 0; i < nrf - 1; i++)
970 
    GEN ("\n    lm_bid == %i ? i%i_l_linbrst : ", i, i);
971 
  GEN ("i%i_l_linbrst;\n", nrf - 1);
972 
  GEN ("end\n\n");
973 
 
974 
  /* start/end signals */
975 
  GEN ("\n\n/* start/end signals */\n");
976 
  for (i = 0; i < nrf; i++) {
977 
    if (log2_int (maxncallees + 1))
978 
      GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
979 
        log2_int (maxncallees + 1), i, i, i, i, i);
980 
    else GEN ("wire i%i_current = 0;\n", i);
981 
  }
982 
  GEN ("\n");
983 
 
984 
  for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
985 
    if (log2_int (ncallees[i])) {
986 
      GEN ("reg [%i:0] i%i_start_bid;\n", log2_int (ncallees[i]), j);
987 
      GEN ("always @(start%i", f[i]->tmp);
988 
      for (j = 0, first = 1; j < f[i]->nfdeps; j++)
989 
        if (f[i]->fdeps[j]) GEN (", ");
990 
      GEN (")\n");
991 
      GEN ("begin !!!\n"); //TODO
992 
      GEN ("  \n");
993 
      GEN ("end\n");
994 
    }
995 
    GEN ("wire i%i_start = main_start[%i];\n", j, j);
996 
    j++;
997 
  }
998 
  GEN ("\n");
999 
 
1000 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
1001 
    int nf = f[i]->tmp;
1002 
    GEN ("\n%s%s i%i(.clk(clk), .rst(rst),\n", filename, prof_func[i].name, nf);
1003 
    GEN ("  .l_adr_o(i%i_l_adr), .l_dat_i(i%i_l_dat), .l_req_o(i_l_req[%i]),\n",
1004 
                    nf, nf, nf);
1005 
    GEN ("  .l_sel_o(i%i_l_sel), .l_linbrst_o(i%i_l_linbrst), .l_rdy_i(i%i_l_rdy),\n",
1006 
                    nf, nf, nf);
1007 
    GEN ("  .s_adr_o(i%i_s_adr), .s_dat_o(i%i_s_dat), .s_req_o(i_s_req[%i]),\n",
1008 
                    nf, nf, nf);
1009 
    GEN ("  .s_sel_o(i%i_s_sel), .s_linbrst_o(i%i_s_linbrst), .s_rdy_i(i%i_s_rdy),\n",
1010 
                    nf, nf, nf);
1011 
    GEN ("  ");
1012 
    for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j])
1013 
      GEN (".r%i_i(i%i_r%ii), ", j, nf, j), first = 0;
1014 
 
1015 
    if (first) GEN ("\n  ");
1016 
    for (j = 0, first = 1; j < MAX_REGS; j++)
1017 
      if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
1018 
        GEN (".r%i_o(i%i_r%io), ", j, nf, j), first = 0;
1019 
    if (first) GEN ("\n  ");
1020 
    if (f[i]->nfdeps) {
1021 
      GEN (".fstart_o(i_fstart[%i]), .fend_i(i_fend[%i]), .fid_o(i%i_fid),\n", i, i, i),
1022 
      GEN ("  .fr3_o(i%i_fr3), .fr4_o(i%i_fr4), .fr5_o(i%i_fr5), .fr6_o(i%i_fr6),\n");
1023 
      GEN ("  .fr7_o(i%i_fr7), .fr8_o(i%i_fr8), .fr11_i(i%i_fr11i),\n  ");
1024 
    }
1025 
    GEN (".start_i(i_start[%i]), .end_o(i_end[%i]), .busy_o(i_busy[%i]));\n", nf, nf, nf);
1026 
  }
1027 
 
1028 
  /* output footer */
1029 
  GEN ("\nendmodule\n");
1030 
 
1031 
  fclose (fo);
1032 
}
1033 
 

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