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/* verilog.c -- OpenRISC Custom Unit Compiler, verilog generator

 *    Copyright (C) 2002 Marko Mlinar, markom@opencores.org

 *

 *    This file is part of OpenRISC 1000 Architectural Simulator.

 *

 *    This program is free software; you can redistribute it and/or modify

 *    it under the terms of the GNU General Public License as published by

 *    the Free Software Foundation; either version 2 of the License, or

 *    (at your option) any later version.

 *

 *    This program is distributed in the hope that it will be useful,

 *    but WITHOUT ANY WARRANTY; without even the implied warranty of

 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *    GNU General Public License for more details.

 *

 *    You should have received a copy of the GNU General Public License

 *    along with this program; if not, write to the Free Software

 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

#include <stdio.h>

#include <stdlib.h>

#include <stdarg.h>

#include <assert.h>

#include "cuc.h"

#include "insn.h"

/* Find index of load/store */

int find_ls_index (cuc_func *f, int ref)

{

  int c = 0;

  int i;

  int load = II_IS_LOAD (f->INSN(ref).index);

  for (i = 0; i < f->nmsched; i++) {

    if (f->msched[i] == ref) break;

    if (load && (!(f->mtype[i] & MT_WRITE))

     || !load && (f->mtype[i] & MT_WRITE)) c++;

  }

  return c;

}

/* Print out dependencies as verilog expression */

void print_deps (FILE *fo, cuc_func *f, int b, dep_list *t, int registered)

{

  if (t) {

    int first = 0;

    while (t) {

      assert (f->INSN(t->ref).type & IT_MEMORY);

      fprintf (fo, "%s%c_end[%i]", first ? " && " : "",

                  II_IS_LOAD (f->INSN(t->ref).index) ? 'l' : 's', find_ls_index (f, t->ref));

      first = 1;

      t = t->next;

    }

  } else {

    if (registered) fprintf (fo, "bb_start_r[%i]", b);

    else fprintf (fo, "bb_start[%i]", b);

  }

}

char *print_op_v (cuc_func *f, char *s, int ref, int j)

{

  unsigned long op = f->INSN(ref).op[j];

  unsigned long opt = f->INSN(ref).opt[j];

  switch (opt & ~OPT_DEST) {

    case OPT_NONE: assert (0); break;

    case OPT_CONST: sprintf (s, "32'h%x", op); break;

    case OPT_REGISTER:

                    if (opt & OPT_DEST) sprintf (s, "t%x_%x", REF_BB(ref), REF_I(ref));

                    else sprintf (s, "r%i_%c", op, opt & OPT_DEST ? 'o' : 'i');

                    break;

    case OPT_REF:   sprintf (s, "t%x_%x", REF_BB(op), REF_I(op)); break;

  }

  return s;

}

/* Prints out specified instruction */

void print_insn_v (FILE *fo, cuc_func *f, int b, int i)

{

  cuc_insn *ii = &f->bb[b].insn[i];

  char *s = known[ii->index].rtl;

  char tmp[200] = "";

  while (*s) {

    if (*s <= MAX_OPERANDS) {

      char t[30];

      sprintf (tmp, "%s%s", tmp, print_op_v (f, t, REF(b, i), *s - 1));

    } else if (*s == '\b') sprintf (tmp, "%s%i", b);

    else sprintf (tmp, "%s%c", tmp, *s);

    s++;

  }

  fprintf (fo, "%-40s /* %s */\n", tmp, ii->disasm);

  if (ii->type & IT_MEMORY) {

    int j, nls = find_ls_index (f, REF (b, i));

    if (II_IS_LOAD (ii->index)) {

      int nm;

      for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;

      assert (nm < f->nmsched);

      fprintf (fo, "  if (rst) t%x_%x <= #1 32'h0;\n", b, i);

      fprintf (fo, "  else if (l_end[%i]) t%x_%x <= #1 ", nls, b, i);

      switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {

        case 1: fprintf (fo, "lwb_dat_i & 32'hff;\n");

                break;

        case 2: fprintf (fo, "lwb_dat_i & 32'hffff;\n");

                break;

        case 4 | MT_SIGNED:

        case 4: fprintf (fo, "lwb_dat_i;\n");

                break;

        case 1 | MT_SIGNED:

                fprintf (fo, "{24{lwb_dat_i[7]}, lwb_dat_i[7:0]};\n");

                break;

        case 2 | MT_SIGNED:

                fprintf (fo, "{16{lwb_dat_i[15]}, lwb_dat_i[15:0]};\n");

                break;

        default: assert (0);

      }

    }

  } else if (ii->index == II_LRBB) {

    fprintf (fo, "  if (rst) t%x_%x <= #1 1'b0;\n", b, i);

    assert (f->bb[b].prev[0] >= 0);

    fprintf (fo, "  else if (bb_start[%i]) t%x_%x <= #1 bb_stb[%i];\n", b, b, i, f->bb[b].prev[0]);

  } else if (ii->index == II_REG) {

    fprintf (fo, "  if (rst) t%x_%x <= #1 32'h0;\n", b, i);

    assert (ii->opt[1] == OPT_REF);

    fprintf (fo, "  else if (");

    if (f->bb[b].mdep) print_deps (fo, f, b, f->bb[b].mdep, 0);

    else fprintf (fo, "bb_stb[%i]", b);

    fprintf (fo, ") t%x_%x <= #1 t%x_%x;\n",  b, i,

                    REF_BB (ii->op[1]), REF_I (ii->op[1]));

  }

}

/* Outputs binary number */

char *bin_str (unsigned long x, int len)

{

  static char bx[33];

  char *s = bx;

  while (len > 0) *s++ = '0' + ((x >> --len) & 1);

  *s = '\0';

  return bx;

}

/* Returns index of branch instruction inside a block b */

int branch_index (cuc_bb *bb)

{

  int i;

  for (i = bb->ninsn - 1; i >= 0; i--)

    if (bb->insn[i].type & IT_BRANCH) return i;

  return -1;

}

/* Generates verilog file out of insn dataflow */

void output_verilog (cuc_func *f, char *filename)

{

  FILE *fo;

  int used_regs[MAX_REGS] = {0};

  int lur[MAX_REGS] = {0};

  int b, i, j;

  int ci = 0, co = 0;

  int nloads = 0, nstores = 0;

  char tmp[256];

  cuc_bb *end_bb = NULL;

  int end_bb_no = -1;

  sprintf (tmp, "%s.v", filename);

  if ((fo = fopen (tmp, "wt+")) == NULL) {

    fprintf (stderr, "Cannot open '%s'\n", tmp);

    exit (1);

  }

  /* Determine register usage */

  for (i = 0; i < MAX_REGS; i++) lur[i] = -1;

  for (b = 0; b < f->num_bb; b++) {

    for (i = 0; i < f->bb[b].ninsn; i++)

      for (j = 0; j < MAX_OPERANDS; j++)

        if (f->bb[b].insn[i].opt[j] & OPT_REGISTER && f->bb[b].insn[i].op[j] >= 0)

          if (f->bb[b].insn[i].opt[j] & OPT_DEST) lur[f->bb[b].insn[i].op[j]] = REF (b, i);

          else used_regs[f->bb[b].insn[i].op[j]] = 1;

    if (f->bb[b].type & BB_END) end_bb = &f->bb[end_bb_no = b];

  }

  assert (end_bb && end_bb->type & BB_END);

  /* output header */

  fprintf (fo, "/* %s -- generated by OpenRISC Custom Unit Compiler (c) OpenCores */\n", tmp);

  fprintf (fo, "module %s (clk, rst,\n", filename);

  fprintf (fo, "              lwb_adr_o, lwb_dat_i, lwb_cycstb_o,\n");

  fprintf (fo, "              lwb_sel_o, lwb_linbrst_o, lwb_ack_i,\n");

  fprintf (fo, "              swb_adr_o, swb_dat_o, swb_cycstb_o,\n");

  fprintf (fo, "              swb_sel_o, swb_linbrst_o, swb_ack_i,\n");

  fprintf (fo, "/* inputs */  ");

  for (i = 0; i < MAX_REGS; i++)

    if (used_regs[i]) {

      fprintf (fo, "r%i_i, ", i);

      ci++;

    }

  if (!ci) fprintf (fo, "/* NONE */");

  fprintf (fo, "\n/* outputs */ ");

  for (i = 0; i < MAX_REGS; i++)

    if (lur[i] >= 0 && !f->saved_regs[i]) {

      fprintf (fo, "r%i_o, ", i);

      co++;

    }

  if (!co) fprintf (fo, "/* NONE */");

  fprintf (fo, "\n              start_i, end_o);\n\n");

  fprintf (fo, "input         clk, rst;\n");

  fprintf (fo, "input         start_i;\t/* Module starts when set to 1 */ \n");

  fprintf (fo, "output        end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n\n");

  fprintf (fo, "/* Bus signals */\n");

  fprintf (fo, "output        lwb_cycstb_o, swb_cycstb_o;\n");

  fprintf (fo, "input         lwb_ack_i, swb_ack_i;\n");

  fprintf (fo, "output  [3:0] lwb_sel_o, swb_sel_o;\n");

  fprintf (fo, "output [31:0] lwb_adr_o, swb_adr_o;\n");

  fprintf (fo, "output        lwb_linbrst_o, swb_linbrst_o;\n");

  fprintf (fo, "input  [31:0] lwb_dat_i;\n");

  fprintf (fo, "output [31:0] swb_dat_o;\n\n");

  fprintf (fo, "reg           lwb_cycstb_o, swb_cycstb_o;\n");

  fprintf (fo, "reg    [31:0] lwb_adr_o, swb_adr_o;\n");

  fprintf (fo, "reg     [3:0] lwb_sel_o, swb_sel_o;\n");

  fprintf (fo, "reg    [31:0] swb_dat_o;\n");

  fprintf (fo, "reg           lwb_linbrst_o, swb_linbrst_o;\n");

  if (ci || co) fprintf (fo, "\n/* module ports */\n");

  if (ci) {

    int first = 1;

    fprintf (fo, "input  [31:0]");

    for (i = 0; i < MAX_REGS; i++)

      if (used_regs[i]) {

        fprintf (fo, "%sr%i_i", first ? " " : ", ", i);

        first = 0;

      }

    fprintf (fo, ";\n");

  }

  if (co) {

    int first = 1;

    fprintf (fo, "output [31:0]");

    for (i = 0; i < MAX_REGS; i++)

      if (lur[i] >= 0 && !f->saved_regs[i]) {

        fprintf (fo, "%sr%i_o", first ? " " : ", ", i);

        first = 0;

      }

    fprintf (fo, ";\n");

  }

  /* Count loads & stores */

  for (i = 0; i < f->nmsched; i++)

    if (f->mtype[i] & MT_WRITE) nstores++;

    else nloads++;

  /* Output internal registers for loads */

  if (nloads) {

    int first = 1;

    fprintf (fo, "\n/* internal registers for loads */\n");

    for (i = 0; i < f->nmsched; i++)

      if (!(f->mtype[i] & MT_WRITE)) {

        fprintf (fo, "%st%x_%x", first ? "reg    [31:0] " : ", ",

                REF_BB(f->msched[i]), REF_I(f->msched[i]));

        first = 0;

      }

    if (!first) fprintf (fo, ";\n");

  }

  fprintf (fo, "\n/* 'zero or one' hot state machines */\n");

  if (nloads) fprintf (fo, "reg     [%i:0] l_stb; /* loads */\n", nloads - 1);

  if (nstores) fprintf (fo, "reg     [%i:0] s_stb; /* stores */\n", nstores - 1);

  fprintf (fo, "reg     [%i:0] bb_stb; /* basic blocks */\n", f->num_bb - 1);

  {

    int first = 1;

    int num = 0;

    fprintf (fo, "\n/* basic block condition wires */\n");

    for (b = 0; b < f->num_bb; b++)

      for (i = 0; i < f->bb[b].ninsn; i++)

        if (f->bb[b].insn[i].type & IT_COND

         && f->bb[b].insn[i].index != II_REG

         && f->bb[b].insn[i].index != II_LRBB) {

          fprintf (fo, "%st%x_%x", first ? "wire          " : ", ", b, i);

          if (num >= 10) {

            fprintf (fo, ";\n");

            first = 1;

            num = 0;

          } else {

            first = 0;

            num++;

          }

        }

    if (!first) fprintf (fo, ";\n");

    fprintf (fo, "\n/* forward declaration of normal wires */\n");

    num = 0;

    first = 1;

    for (b = 0; b < f->num_bb; b++)

      for (i = 0; i < f->bb[b].ninsn; i++)

        if (!(f->bb[b].insn[i].type & (IT_COND | IT_BRANCH))

         && f->bb[b].insn[i].index != II_REG

         && f->bb[b].insn[i].index != II_LRBB) {

          /* Exclude loads */

          if (f->bb[b].insn[i].type & IT_MEMORY && II_IS_LOAD (f->bb[b].insn[i].index)) continue;

          fprintf (fo, "%st%x_%x", first ? "wire   [31:0] " : ", ", b, i);

          if (num >= 10) {

            fprintf (fo, ";\n");

            first = 1;

            num = 0;

          } else {

            first = 0;

            num++;

          }

        }

    if (!first) fprintf (fo, ";\n");

    fprintf (fo, "\n/* forward declaration registers */\n");

    num = 0;

    first = 1;

    for (b = 0; b < f->num_bb; b++)

      for (i = 0; i < f->bb[b].ninsn; i++)

        if (f->bb[b].insn[i].index == II_REG

         && f->bb[b].insn[i].index != II_LRBB) {

          fprintf (fo, "%st%x_%x", first ? "reg    [31:0] " : ", ", b, i);

          if (num >= 10) {

            fprintf (fo, ";\n");

            first = 1;

            num = 0;

          } else {

            first = 0;

            num++;

          }

        }

    if (!first) fprintf (fo, ";\n");

    num = 0;

    first = 1;

    for (b = 0; b < f->num_bb; b++)

      for (i = 0; i < f->bb[b].ninsn; i++)

        if (f->bb[b].insn[i].index != II_REG

         && f->bb[b].insn[i].index == II_LRBB) {

          fprintf (fo, "%st%x_%x", first ? "reg           " : ", ", b, i);

          if (num >= 10) {

            fprintf (fo, ";\n");

            first = 1;

            num = 0;

          } else {

            first = 0;

            num++;

          }

        }

    if (!first) fprintf (fo, ";\n");

  }

  if (nloads || nstores) fprintf (fo, "\n/* dependencies */\n");

  if (nloads) fprintf (fo, "wire    [%i:0] l_end = l_stb & {%i{lwb_ack_i}};\n",

                  nloads - 1, nloads);

  if (nstores) fprintf (fo, "wire    [%i:0] s_end = s_stb & {%i{swb_ack_i}};\n",

                  nstores - 1, nstores);

  fprintf (fo, "\n/* last dependency */\n");

  fprintf (fo, "wire   end_o = bb_stb[%i]", end_bb_no);

  if (end_bb->mdep) {

    fprintf (fo, " && ");

    print_deps (fo, f, end_bb_no, end_bb->mdep, 0);

  }

  /* Is there a loop right at end? */

  if (end_bb->next[0] >= 0) {

    int bidx = branch_index (end_bb);

    char t[30];

    print_op_v (f, t, REF (end_bb_no, bidx), 1);

    fprintf (fo, " && !%s", t);

  }

  fprintf (fo, ";\n");

  fprintf (fo, "\n/* Basic block triggers */\n");

  fprintf (fo, "wire   [%2i:0] bb_start = {\n", f->num_bb - 1);

  for (b = f->num_bb - 1; b >= 0; b--) {

    fprintf (fo, "    /* bb_start[%2i] */ ", b);

    if (f->bb[b].prev[0] < 0) fprintf (fo, "start_i");

    else {

      cuc_bb *prev = &f->bb[f->bb[b].prev[0]];

      int t;

      if (prev->mdep) {

        print_deps (fo, f, f->bb[b].prev[0], prev->mdep, 0);

        fprintf (fo, " && ");

      }

      fprintf (fo, "bb_stb[%i]", f->bb[b].prev[0]);

      if (prev->next[0] >= 0 && prev->next[1] >= 0) {

        int bidx = branch_index (&f->bb[f->bb[b].prev[0]]);

        assert (bidx >= 0);

        fprintf (fo, " && ");

        t = prev->next[0] == b;

        fprintf (fo, "%st%x_%x", t ? "" : "!", f->bb[b].prev[0], bidx);

      }

      if (f->bb[b].prev[1] >= 0) {

        prev = &f->bb[f->bb[b].prev[1]];

        fprintf (fo, "\n                    || ");

        if (prev->mdep) {

          print_deps (fo, f, f->bb[b].prev[1], prev->mdep, 0);

          fprintf (fo, " && ");

        }

        fprintf (fo, "bb_stb[%i]", f->bb[b].prev[1]);

        if (prev->next[0] >= 0 && prev->next[1] >= 0) {

          int bidx = branch_index (&f->bb[f->bb[b].prev[1]]);

          assert (bidx >= 0);

          fprintf (fo, " && ");

          t = prev->next[0] == b;

          fprintf (fo, "%st%x_%x", t ? "" : "!", f->bb[b].prev[1], bidx);

        }

      }

    }

    if (b == 0) fprintf (fo, "};\n");

    else fprintf (fo, ",\n");

  }

  fprintf (fo, "\n/* Register the bb_start */\n");

  fprintf (fo, "reg   [%2i:0] bb_start_r;\n\n", f->num_bb - 1);

  fprintf (fo, "always @(posedge rst or posedge clk)\n");

  fprintf (fo, "begin\n");

  fprintf (fo, "  if (rst || end_o) bb_start_r <= #1 %i'b0;\n", f->num_bb);

  fprintf (fo, "  else bb_start_r <= #1 bb_start;\n");

  fprintf (fo, "end\n");

  fprintf (fo, "\n/* Logic */\n");

  /* output body */

  for (b = 0; b < f->num_bb; b++) {

    fprintf (fo, "\t\t/* BB%i */\n", b);

    for (i = 0; i < f->bb[b].ninsn; i++)

      print_insn_v (fo, f, b, i);

    fprintf (fo, "\n");

  }

  if (co) {

    fprintf (fo, "\n/* Outputs */\n");

    for (i = 0; i < MAX_REGS; i++)

      if (lur[i] >= 0 && !f->saved_regs[i])

        fprintf (fo, "assign r%i_o = t%x_%x;\n", i, REF_BB(lur[i]),

                        REF_I(lur[i]));

  }

  if (nstores) {

    int cur_store = 0;

    fprintf (fo, "\n/* Memory stores */\n");

    fprintf (fo, "always @(posedge clk or posedge rst)\nbegin\n");

    fprintf (fo, "  if (rst) swb_dat_o <= #1 32'h0;\n");

    for (i = 0; i < f->nmsched; i++)

      if (f->mtype[i] & MT_WRITE) {

        char t[30];

        fprintf (fo, "  else if (s_stb[%i]) swb_dat_o <= #1 %s;\n", cur_store++,

                        print_op_v (f, t, f->msched[i], 0));

        //printf ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);

      }

    fprintf (fo, "end\n");

  }

  if (nloads) {

    int cur_load = 0;

    fprintf (fo, "\n/* Load state machine */\n");

    fprintf (fo, "always @(posedge clk or posedge rst)\n");

    fprintf (fo, "begin\n");

    fprintf (fo, "  if (rst) begin\n");

    fprintf (fo, "    l_stb <= #1 %i'h0;\n", nloads);

    fprintf (fo, "    lwb_cycstb_o <= #1 1'b0;\n");

    fprintf (fo, "    lwb_sel_o[3:0] <= #1 4'b0000;\n");

    fprintf (fo, "    lwb_linbrst_o <= #1 1'b0;\n");

    fprintf (fo, "    lwb_adr_o <= #1 32'h0;\n");

    fprintf (fo, "  end else begin\n");

    printf ("loads \n");

    for (i = 0; i < f->nmsched; i++) if (!(f->mtype[i] & MT_WRITE)) {

      char t[30];

      dep_list *dep = f->INSN(f->msched[i]).dep;

      printf ("msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);

      assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));

      fprintf (fo, "    if (");

      print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);

      fprintf (fo, ") begin\n");

      while (dep) {

        assert (f->INSN(dep->ref).type & IT_MEMORY);

        fprintf (fo, "      %c_end[%i] <= #1 1'b0;\n",

                  II_IS_LOAD (f->INSN(dep->ref).index) ? 'l' : 's', find_ls_index (f, dep->ref));

        dep = dep->next;

      }

      fprintf (fo, "      l_stb[%i] <= #1 1'b1;\n", cur_load++);

      fprintf (fo, "      lwb_cycstb_o <= #1 1'b1;\n");

      fprintf (fo, "      lwb_sel_o[3:0] <= #1 4'b");

      switch (f->mtype[i] & MT_WIDTH) {

        case 1: fprintf (fo, "0001 << (%s & 32h'3);\n",

                                print_op_v (f, t, f->msched[i], 1)); break;

        case 2: fprintf (fo, "0011 << ((%s & 32h'1) << 1);\n",

                                print_op_v (f, t, f->msched[i], 1)); break;

        case 4: fprintf (fo, "1111;\n"); break;

        default: assert (0);

      }

      fprintf (fo, "      lwb_linbrst_o <= #1 1'b%i;\n",

                      (f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);

      fprintf (fo, "      lwb_adr_o <= #1 t%x_%x & ~32'h3;\n",

                      REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));

      fprintf (fo, "    end\n");

    }

    fprintf (fo, "    if (l_end[%i]) begin\n", nloads - 1);

    fprintf (fo, "      l_stb <= #1 %i'h0;\n", nloads);

    fprintf (fo, "      lwb_cycstb_o <= #1 1'b0;\n");

    fprintf (fo, "      lwb_sel_o[3:0] <= #1 4'b0000;\n");

    fprintf (fo, "      lwb_linbrst_o <= #1 1'b0;\n");

    fprintf (fo, "      lwb_adr_o <= #1 32'h0;\n");

    fprintf (fo, "    end\n");

    fprintf (fo, "  end\n");

    fprintf (fo, "end\n");