OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [sim-config.h] - Blame information for rev 1751

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1446 nogj
/* sim-config.h -- Simulator configuration header file
2 1743 jeremybenn
 
3 7 jrydberg
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4 1743 jeremybenn
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8 7 jrydberg
   This file is part of OpenRISC 1000 Architectural Simulator.
9 1743 jeremybenn
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
22 428 markom
 
23 1748 jeremybenn
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25 1743 jeremybenn
 
26 428 markom
 
27 1748 jeremybenn
#ifndef SIM_CONFIG_H
28
#define SIM_CONFIG_H
29
 
30
/* System includes */
31 173 markom
#include <stdio.h>
32
 
33 1748 jeremybenn
/* Package includes */
34
#include "arch.h"
35
 
36 7 jrydberg
/* Simulator configuration macros. Eventually this one will be a lot bigger. */
37 30 lampret
 
38 1748 jeremybenn
#define MAX_SBUF_LEN     256    /* Max. length of store buffer */
39 424 markom
 
40 1748 jeremybenn
#define EXE_LOG_HARDWARE   0    /* Print out RTL states */
41
#define EXE_LOG_SIMPLE     1    /* Executed log prints out dissasembly */
42
#define EXE_LOG_SOFTWARE   2    /* Simple with some register output */
43 672 markom
 
44 1748 jeremybenn
#define STR_SIZE         256
45 239 markom
 
46 1748 jeremybenn
/* Number of cycles between checks to runtime.sim.iprompt */
47
#define CHECK_INT_TIME 100000
48 1745 jeremybenn
 
49 1748 jeremybenn
#define PRINTF(x...) fprintf (runtime.sim.fout, x)
50 1718 nogj
 
51 1748 jeremybenn
/*! Data structure for configuration data */
52
struct config
53
{
54
  struct
55
  {                             /* External linkage for SystemC */
56
    void *class_ptr;
57
    unsigned long int (*read_up) (void *class_ptr,
58
                                  unsigned long int addr,
59
                                  unsigned long int mask);
60
    void (*write_up) (void *class_ptr,
61
                      unsigned long int addr,
62
                      unsigned long int mask, unsigned long int wdata);
63
  } ext;
64 897 markom
 
65 1748 jeremybenn
  struct
66
  {
67
    int debug;                  /* Simulator debugging */
68
    int verbose;                /* Force verbose output */
69 884 markom
 
70 1748 jeremybenn
    int profile;                /* Is profiler running */
71
    char *prof_fn;              /* Profiler filename */
72 1320 phoenix
 
73 1748 jeremybenn
    int mprofile;               /* Is memory profiler running */
74
    char *mprof_fn;             /* Memory profiler filename */
75 1353 nogj
 
76 1748 jeremybenn
    int history;                /* instruction stream history analysis */
77
    int exe_log;                /* Print out RTL states? */
78
    int exe_log_type;           /* Type of log */
79
    long long int exe_log_start;        /* First instruction to log */
80
    long long int exe_log_end;  /* Last instr to log, -1 if continuous */
81
    int exe_log_marker;         /* If nonzero, place markers before */
82
    /* each exe_log_marker instructions */
83
    char *exe_log_fn;           /* RTL state comparison filename */
84
    long clkcycle_ps;           /* Clock duration in ps */
85 264 markom
  } sim;
86 883 markom
 
87 1748 jeremybenn
  struct
88
  {                             /* Verification API */
89
    int enabled;                /* Whether is VAPI module enabled */
90
    int server_port;            /* user specified port for services */
91
    int log_enabled;            /* Whether to log the vapi requests */
92
    int hide_device_id;         /* Whether to log dev ID each request */
93
    char *vapi_fn;              /* vapi log filename */
94 293 markom
  } vapi;
95 1748 jeremybenn
 
96
  struct
97
  {
98
    char *timings_fn;           /* Filename of the timing table */
99
    int memory_order;           /* Memory access stricness */
100
    int calling_convention;     /* Do funcs follow std calling conv? */
101
    int enable_bursts;          /* Whether burst are enabled */
102
    int no_multicycle;          /* Generate no multicycle paths */
103 897 markom
  } cuc;
104 239 markom
 
105 1748 jeremybenn
  struct
106
  {
107
    int superscalar;            /* superscalara analysis */
108
    int hazards;                /* dependency hazards analysis */
109
    int dependstats;            /* dependency statistics */
110
    int sbuf_len;               /* length of store buffer, 0=disabled */
111
  } cpu;
112 551 markom
 
113 1748 jeremybenn
  struct
114
  {
115
    int enabled;                /* Whether data cache is enabled */
116
    int nways;                  /* Number of DC ways */
117
    int nsets;                  /* Number of DC sets */
118
    int blocksize;              /* DC entry size */
119
    int ustates;                /* number of DC usage states */
120
    int store_missdelay;        /* cycles a store miss costs */
121
    int store_hitdelay;         /* cycles a store hit costs */
122
    int load_missdelay;         /* cycles a load miss costs */
123
    int load_hitdelay;          /* cycles a load hit costs */
124
  } dc;
125 997 markom
 
126 1748 jeremybenn
  struct pic
127
  {
128
    int enabled;                /* Is interrupt controller enabled? */
129
    int edge_trigger;           /* Are interrupts edge triggered? */
130
  } pic;
131 239 markom
 
132 1748 jeremybenn
  struct
133
  {
134
    int enabled;                /* Is power management operational? */
135
  } pm;
136 361 markom
 
137 1748 jeremybenn
  struct
138
  {
139
    int enabled;                /* branch prediction buffer analysis */
140
    int sbp_bnf_fwd;            /* Static BP for l.bnf uses fwd predn */
141
    int sbp_bf_fwd;             /* Static BP for l.bf uses fwd predn */
142
    int btic;                   /* BP target insn cache analysis */
143
    int missdelay;              /* How much cycles does the miss cost */
144
    int hitdelay;               /* How much cycles does the hit cost */
145
  } bpb;
146 428 markom
 
147 1748 jeremybenn
  struct
148
  {
149
    int enabled;                /* Is debug module enabled */
150 1751 jeremybenn
    int gdb_enabled;            /* Is legacy debugging with GDB possible */
151
    int rsp_enabled;            /* Is RSP debugging with GDB possible */
152
    int server_port;            /* Port for legacy GDB connection */
153
    int rsp_port;               /* Port for RSP GDB connection */
154 1748 jeremybenn
    unsigned long vapi_id;      /* "Fake" vapi dev id for JTAG proxy */
155
  } debug;
156
};
157 549 markom
 
158 1748 jeremybenn
/*! Data structure for run time data */
159
struct runtime
160
{
161
  struct
162
  {
163
    FILE *fprof;                /* Profiler file */
164
    FILE *fmprof;               /* Memory profiler file */
165
    FILE *fexe_log;             /* RTL state comparison file */
166
    FILE *fout;                 /* file for standard output */
167
    char *filename;             /* Original Command Simulator file (CZ) */
168
    int iprompt;                /* Interactive prompt */
169
    int iprompt_run;            /* Interactive prompt is running */
170
    long long cycles;           /* Cycles counts fetch stages */
171
    long long int end_cycles;   /* JPB. Cycles to end of quantum */
172
    double time_point;          /* JPB. Time point in the simulation */
173
    unsigned long int ext_int;  /* JPB. External interrupt flags */
174 1308 phoenix
 
175 1748 jeremybenn
    int mem_cycles;             /* Each cycle has counter of mem_cycles;
176
                                   this value is joined with cycles
177
                                   at the end of the cycle; no sim
178
                                   originated memory accesses should be
179
                                   performed inbetween. */
180
    int loadcycles;             /* Load and store stalls */
181
    int storecycles;
182 1308 phoenix
 
183 1748 jeremybenn
    long long reset_cycles;
184 1353 nogj
 
185 1751 jeremybenn
    int  hush;                  /* Is simulator to do reg dumps */
186 1748 jeremybenn
  } sim;
187 1471 nogj
 
188 1748 jeremybenn
  struct
189
  {
190
    long long instructions;     /* Instructions executed */
191
    long long reset_instructions;
192 1471 nogj
 
193 1748 jeremybenn
    int stalled;
194
    int hazardwait;             /* how many cycles were wasted because of hazards */
195
    int supercycles;            /* Superscalar cycles */
196
  } cpu;
197 1353 nogj
 
198 1748 jeremybenn
  struct
199
  {                             /* Verification API, part of Advanced Core Verification */
200
    int enabled;                /* Whether is VAPI module enabled */
201
    FILE *vapi_file;            /* vapi file */
202
    int server_port;            /* A user specified port number for services */
203
  } vapi;
204 1358 nogj
 
205 1748 jeremybenn
/* CUC configuration parameters */
206
  struct
207
  {
208
    int mdelay[4];              /* average memory delays in cycles
209
                                   {read single, read burst, write single, write burst} */
210
    double cycle_duration;      /* in ns */
211
  } cuc;
212
};
213 1360 nogj
 
214 1748 jeremybenn
/*! Union of all possible paramter values */
215
union param_val
216
{
217
  char          *str_val;
218
  int            int_val;
219
  long long int  longlong_val;
220
  oraddr_t       addr_val;
221 1358 nogj
};
222
 
223 1748 jeremybenn
/*! Enum of all possible paramter types */
224
enum param_t
225
{
226
  paramt_none = 0,               /* No parameter */
227
  paramt_str,                   /* String parm enclosed in double quotes (") */
228
  paramt_word,                  /* String parm NOT enclosed in double quotes */
229
  paramt_int,                   /* Integer parameter */
230
  paramt_longlong,              /* Long long int parameter */
231
  paramt_addr                   /* Address parameter */
232 1358 nogj
};
233
 
234 1748 jeremybenn
/* Generic structure for a configuration section */
235
struct config_section
236
{
237 1358 nogj
  char *name;
238 1748 jeremybenn
  void *(*sec_start) (void);
239
  void (*sec_end) (void *);
240 1358 nogj
  void *dat;
241
  struct config_param *params;
242
  struct config_section *next;
243
};
244
 
245 1748 jeremybenn
/* Externally visible data structures*/
246
extern struct config          config;
247
extern struct runtime         runtime;
248
extern struct config_section *cur_section;
249
extern int                    do_stats;
250 1358 nogj
 
251 1748 jeremybenn
/* Prototypes for external use */
252
extern void  set_config_command (int argc, char **argv);
253
extern void  init_defconfig (void);
254
extern int   parse_args (int argc, char *argv[]);
255
extern void  print_config (void);
256
extern void  reg_config_param (struct config_section *sec,
257
                               const char            *param,
258
                               enum param_t           type,
259
                               void (*param_cb)  (union param_val,
260
                                                  void *));
261
extern struct config_section *reg_config_sec (const char *section,
262
                                              void *(*sec_start) (void),
263
                                              void  (*sec_end) (void *));
264 1358 nogj
 
265 1748 jeremybenn
extern void  reg_config_secs ();
266 1358 nogj
 
267 1748 jeremybenn
#endif /* SIM_CONFIG_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.