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/* sim.cfg -- Simulator configuration script file

   Copyright (C) 2001, Marko Mlinar, markom@opencores.org

This file includes a lot of help about configurations and default one

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

/* INTRODUCTION

   The or1ksim have various parameters, which can be set in configuration

   files.  Multiple configurations may be used and switched between at

   or1ksim startup.

   By default, or1ksim loads condfiguration file from './sim.cfg' and if not

   found it checks '~/.or1k/sim.cfg'. If even this file is not found or

   all parameters are not defined, default configuration is used.

   Users should not rely on default configuration, but rather redefine all

   critical settings, since default configuration may differ in newer

   versions of the or1ksim.

   If multiple configurations are used, user can switch between them by

   supplying -f  option when starting simulator.

   This file may contain (standard C) only comments - no // support.

   Like normal configuration file, this file is divided in sections,

   where each section is described in detail also.

   Some section also have subsections. One example of such subsection is

   block:

   device 

     instance specific parameters...

   enddevice

   which creates a device instance.

*/

/* MEMORY SECTION

   This section specifies how is initial memory generated and which blocks

   it consist of.

   type = random/unknown/pattern

      specifies the initial memory values. 'random' parameter generate

      random memory using seed 'random_seed' parameter. 'pattern' parameter

      fills memory with 'pattern' parameter and 'unknown' does not specify

      how memory should be generated - the fastest option.

   random_seed = 

      random seed for randomizer, used if type = random

   pattern = 

      pattern to fill memory, used if type = pattern

   nmemories = 

      number of memory instances connected

   instance specific:

     baseaddr = 

        memory start address

     size = 

        memory size

     name = ""

        memory block name

     ce = 

        chip enable index of the memory instance

     delayr = 

        cycles, required for read access, -1 if instance does not support reading

     delayw = 

        cycles, required for write access, -1 if instance does not support writing

     16550 = 0/1

        0, if this device is uart 16450 and 1, if it is 16550

     log = ""

        filename, where to log memory accesses to, no log, if log command is not specified

*/

section memory

  /*random_seed = 12345

  type = random*/

  pattern = 0x00

  type = unknown /* Fastest */

  nmemories = 2

  device 0

    name = "RAM"

    ce = 0

    baseaddr = 0x00000000

    size = 0x00100000

    delayr = 10

    delayw = -1

  enddevice

  device 1

    name = "FLASH"

    ce = 1

    baseaddr = 0x40000000

    size = 0x00100000

    delayr = 2

    delayw = 4

  enddevice

end

/* IMMU SECTION

    This section configures Instruction Memory Menangement Unit

    enabled = 0/1

       whether IMMU is enabled

       (NOTE: UPR bit is set)

    nsets = 

       number of ITLB sets; must be power of two

    nways = 

       number of ITLB ways

    pagesize = 

       instruction page size; must be power of two

    entrysize = 

       instruction entry size in bytes

    ustates = 

       number of ITLB usage states (2, 3, 4 etc., max is 4)

    hitdelay = 

       number of cycles immu hit costs

    missdelay = 

       number of cycles immu miss costs

*/

section immu

  enabled = 0

  nsets = 32

  nways = 1

  pagesize = 8192

  hitdelay = 0

  missdelay = 0

end

/* DMMU SECTION

    This section configures Data Memory Menangement Unit

    enabled = 0/1

       whether DMMU is enabled

       (NOTE: UPR bit is set)

    nsets = 

       number of DTLB sets; must be power of two

    nways = 

       number of DTLB ways

    pagesize = 

       data page size; must be power of two

    entrysize = 

       data entry size in bytes

    ustates = 

       number of DTLB usage states (2, 3, 4 etc., max is 4)

    hitdelay = 

       number of cycles immu hit costs

    missdelay = 

       number of cycles immu miss costs

*/

section dmmu

  enabled = 0

  nsets = 32

  nways = 1

  pagesize = 8192

  hitdelay = 0

  missdelay = 0

end

/* IC SECTION

   This section configures Instruction Cache

   enabled = 0/1

      whether IC is enabled

      (NOTE: UPR bit is set)

   nsets = 

      number of IC sets; must be power of two

   nways = 

      number of IC ways

   blocksize = 

      IC block size in bytes; must be power of two

   ustates = 

      number of IC usage states (2, 3, 4 etc., max is 4)

   hitdelay = 

      number of cycles ic hit costs

    missdelay = 

      number of cycles ic miss costs

*/

section ic

  enabled = 0

  nsets = 512

  nways = 1

  blocksize = 16

  hitdelay = 0

  missdelay = 0

end

/* DC SECTION

   This section configures Data Cache

   enabled = 0/1

      whether DC is enabled

      (NOTE: UPR bit is set)

   nsets = 

      number of DC sets; must be power of two

   nways = 

      number of DC ways

   blocksize = 

      DC block size in bytes; must be power of two

   ustates = 

      number of DC usage states (2, 3, 4 etc., max is 4)

   load_hitdelay = 

      number of cycles dc load hit costs

   load_missdelay = 

      number of cycles dc load miss costs

   store_hitdelay = 

      number of cycles dc load hit costs

   store_missdelay = 

      number of cycles dc load miss costs

*/

section dc

  enabled = 0

  nsets = 512

  nways = 1

  blocksize = 16

  load_hitdelay = 0

  load_missdelay = 0

  store_hitdelay = 0

  store_missdelay = 0

end

/* SIM SECTION

  This section specifies how should sim behave.

  verbose = 0/1

      whether to print out extra messages

  debug = 0-9

      = 0 disabled debug messages

      1-9 level of sim debug information, greater the number more verbose is

          the output

  profile = 0/1

      whether to generate profiling file 'sim.profile'

  prof_fn = ""

      filename, where to generate profiling info, used

      only if 'profile' is set

  history = 0/1

      whether instruction execution flow is tracked for

      display by simulator hist command. Useful for

      back-trace debugging.

  iprompt = 0/1

      whether we strart in interactive prompt

  exe_log = 0/1

      whether execution log should be generated

  exe_log_fn = ""

      where to put execution log in, used only if 'exe_log'

      is set

  clkcycle = [ps|ns|us|ms]

      specifies time measurement for one cycle

*/

section sim

  /* verbose = 1 */

  debug = 0

  profile = 0

  prof_fn = "sim.profile"

  history = 1

  /* iprompt = 0 */

  exe_log = 0

  exe_log_fn = "executed.log"

  clkcycle = 4ns

end

/* SECTION VAPI

    This section configures Verification API, used for Advanced

    Core Verification.

    enabled = 0/1

        whether to start VAPI server

    server_port = 

        TCP/IP port to start VAPI server on

    log_enabled = 0/1

       whether logging of VAPI requests is enabled

    hide_device_id = 0/1

       whether to disable logging of device id (for compatability with old version)

    vapi_fn = 

       specifies filename where to log into, if log_enabled is selected

*/

section VAPI

  enabled = 0

  server_port = 9998

  log_enabled = 0

  vapi_log_fn = "vapi.log"

end

/* CPU SECTION

   This section specifies various CPU parameters.

   ver = 

   rev = 

      specifies version and revision of the CPU used

   upr = 

      changes the upr register

   superscalar = 0/1

      whether CPU is scalar or superscalar

      (modify cpu/or32/execute.c to tune superscalar model)

   hazards = 0/1

      whether data hazards are tracked in superscalar CPU

      and displayed by the simulator r command

   dependstats = 0/1

      whether inter-instruction dependencies are calculated

      and displayed by simulator stats command.

   raw_range = 

      range in cycles for raw register over time analysis, 0 = disabled

*/

section cpu

  ver = 0x1200

  rev = 0x0001

  /* upr = */

  superscalar = 0

  hazards = 0

  dependstats = 0

  btic = 0

  bpb = 0

  sbp_bf_fwd = 0

  sbp_bnf_fwd = 1

  raw_range = 0

end

/* BPB SECTION

   This section specifies how branch prediction should behave.

   enabled = 0/1

      whether bpb is enabled

   btic = 0/1

      enable branch target instruction cache model

   sbp_bf_fwd = 0/1

      whether static branch prediction for l.bf uses forward prediction

   sbp_bnf_fwd = 0/1

      whether static branch prediction for l.bnf uses forward prediction

   hitdelay = 

       number of cycles bpb hit costs

   missdelay = 

       number of cycles bpb miss costs

*/

section bpb

  enabled = 0

  btic = 0

  sbp_bf_fwd = 0

  sbp_bnf_fwd = 0

  hitdelay = 0

  missdelay = 0

end

/* DEBUG SECTION

   This sections specifies how debug unit should behave.

   enabled = 0/1

      whether debug unit is enabled

   gdb_enabled = 0/1

      whether to start gdb server at 'server_port' port

   server_port = 

      TCP/IP port to start gdb server on, used only if gdb_enabled

      is set

   vapi_id = 

      Used to create "fake" vapi log file containing the JTAG proxy messages.

*/

section debug

  enabled = 0

  gdb_enabled = 0

  server_port = 9999

  vapi_id = 0xFFFF

end

/* MC SECTION

   This section configures the memory controller

   enabled = 0/1

      whether memory controller is enabled

   baseaddr = 

      address of first MC register

   POC = 

      Power On Configuration register

*/

section mc

  enabled = 0

  baseaddr = 0xa0000000

  POC = 0x00000008                 /* Power on configuration register */

end

/* UART SECTION

   This section configures UARTs

   enabled = 0/1

      whether uarts are enabled

   nuarts = 

      make specified number of instances, configure each

      instance within device - enddevice construct.

   instance specific:

     baseaddr = 

        address of first UART register for this device

     rx_file = ""

        filename, where to read data from

     tx_file = ""

        filename, where to write data to

     irq = 

        irq number for this device

     16550 = 0/1

        0, if this device is uart 16450 and 1, if it is 16550

     jitter = 

        in msecs... time to block, -1 to disable it

     vapi_id = 

        VAPI id of this instance

*/

section uart

  enabled = 0

  nuarts = 1

  device 0

    baseaddr = 0x80000000

    irq = 2

    rxfile = "/tmp/uart0.rx"

    txfile = "/tmp/uart0.tx"

    jitter = -1                     /* async behaviour */

  enddevice

end

/* DMA SECTION

   This section configures DMAs

   enabled = 0/1

      whether DMAs are enabled

   ndmas = 

      make specified number of instances, configure each

      instance within device - enddevice construct.

   instance specific:

     baseaddr = 

        address of first DMA register for this device

     irq = 

        irq number for this device

     vapi_id = 

        VAPI id of this instance

*/

section dma

  enabled = 0

  ndmas = 1

  device 0

    baseaddr = 0x90000000

    irq = 4

  enddevice

end

/* ETHERNET SECTION

   This section configures ethernets

   enabled = 0/1

      whether ethernets are enabled

   nethernets = 

      make specified number of instances, configure each

      instance within device - enddevice construct.

   instance specific:

     baseaddr = 

        address of first ethernet register for this device

     dma = 

        which controller is this ethernet "connected" to

     rx_channel = 

        DMA channel used for RX

     tx_channel = 

        DMA channel used for TX

     rx_file = ""

        filename, where to read data from

     tx_file = ""

        filename, where to write data to

     vapi_id = 

        VAPI id of this instance

*/

section ethernet

  enabled = 0

  nethernets = 1

  device 0

    baseaddr = 0x88000000

    dma = 0

    tx_channel = 0

    rx_channel = 1

    rxfile = "/tmp/eth0.rx"

    txfile = "/tmp/eth0.tx"

  enddevice

end

/* GPIO SECTION

   This section configures GPIOs

   enabled = 0/1

      whether GPIOs are enabled

   ngpios = 

      make specified number of instances, configure each

      instance within device - enddevice construct.

   instance specific:

     baseaddr = 

        address of first GPIO register for this device

     irq = 

        irq number for this device

     base_vapi_id = 

        first VAPI id of this instance

        GPIO uses 8 consecutive VAPI IDs

*/

section gpio

  enabled = 0

  ngpios = 1

  device 0

    baseaddr = 0xB0000000

    irq = 23

    base_vapi_id = 0x0200

  enddevice

end

/* TICK TIMER SECTION

    This section configures tick timer

    enabled = 0/1

      whether tick timer is enabled

    irq = 

      irq number

*/

section tick

  enabled = 0

  irq = 3

end