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[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [testbench/] [int_test.ld] - Blame information for rev 1765

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MEMORY
        {
        flash  : ORIGIN = 0xf0000000, LENGTH = 0x00200000
        ram    : ORIGIN = 0x00000500, LENGTH = 0x001fb000
        }
 
SECTIONS
{
      .reset :
        {
        *(.reset)
         _src_beg = .;
        } > flash
      .text :
        AT ( ADDR (.reset) + SIZEOF (.reset) )
        {
        _dst_beg = .;
        *(.text)
        } > ram
      .data :
        AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) )
        {
        *(.data)
        *(.rodata)
        _dst_end = .;
        } > ram
      .bss :
        {
        *(.bss)
        } > ram
}

Line No.	Rev	Author	Line
1	970	simons	`MEMORY`
2			`{`
3			`flash : ORIGIN = 0xf0000000, LENGTH = 0x00200000`
4			`ram : ORIGIN = 0x00000500, LENGTH = 0x001fb000`
5			`}`
6
7			`SECTIONS`
8			`{`
9			`.reset :`
10			`{`
11			`*(.reset)`
12			`_src_beg = .;`
13			`} > flash`
14			`.text :`
15			`AT ( ADDR (.reset) + SIZEOF (.reset) )`
16			`{`
17			`_dst_beg = .;`
18			`*(.text)`
19			`} > ram`
20			`.data :`
21			`AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) )`
22			`{`
23			`*(.data)`
24			`*(.rodata)`
25			`_dst_end = .;`
26			`} > ram`
27			`.bss :`
28			`{`
29			`*(.bss)`
30			`} > ram`
31			`}`

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