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[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [testbench/] [mmu_asm.S] - Blame information for rev 1765

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#include "spr_defs.h"
 
#define PAGE_SIZE 8192
#define DTLB_PR_NOLIMIT  (SPR_DTLBTR_URE  | \
                          SPR_DTLBTR_UWE  | \
                          SPR_DTLBTR_SRE  | \
                          SPR_DTLBTR_SWE  )
#define ITLB_PR_NOLIMIT  (SPR_ITLBTR_SXE  | \
                          SPR_ITLBTR_UXE  )
        .global _lo_dmmu_en
        .global _lo_immu_en
        .global _lo_dtlb_ci_test
        .global _lo_itlb_ci_test
        .global _testjump
        .global _ic_enable
        .global _ic_disable
        .global _dc_enable
        .global _dc_disable
 
_lo_dmmu_en:
                                l.mfspr r11,r0,SPR_SR
        l.ori   r11,r11,SPR_SR_DME
        l.mtspr r0,r11,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_lo_dmmu_dis:
        l.addi  r13,r0,-1
        l.xori  r13,r13,SPR_SR_DME
        l.mfspr r11,r0,SPR_SR
        l.and   r11,r11,r13
        l.mtspr r0,r11,SPR_SR
        l.jr    r9
        l.nop
 
_lo_immu_en:
                                l.mfspr r11,r0,SPR_SR
        l.ori   r11,r11,SPR_SR_IME
        l.mtspr r0,r11,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_lo_immu_dis:
        l.addi  r13,r0,-1
        l.xori  r13,r13,SPR_SR_IME
        l.mfspr r11,r0,SPR_SR
        l.and   r11,r11,r13
        l.mtspr r0,r11,SPR_SR
        l.jr    r9
        l.nop
 
_testjump:
        l.movhi r5,0x4800
        l.ori   r5,r5,0x4800
        l.sw    0x0(r3),r5
        l.movhi r5,0x1500
        l.ori   r5,r5,0x0000
        l.sw    0x4(r3),r5
        l.or    r5,r0,r9
        l.jalr  r4
        l.nop
        l.or    r9,r0,r5
        l.jr    r9
        l.nop
 
_ic_enable:
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        /* Invalidate IC */
        l.addi  r13,r0,0
        l.addi  r11,r0,8192
1:
        l.mtspr r0,r13,SPR_ICBIR
        l.sfne  r13,r11
        l.bf    1b
        l.addi  r13,r13,16
 
        /* Enable IC */
        l.mfspr r13,r0,SPR_SR
        l.ori   r13,r13,SPR_SR_ICE
        l.mtspr r0,r13,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        l.jr    r9
        l.nop
 
_ic_disable:
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        l.jr    r9
        l.nop
 
_dc_enable:
        /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        /* Flush DC */
        l.addi  r13,r0,0
        l.addi  r11,r0,8192
1:
        l.mtspr r0,r13,SPR_DCBIR
        l.sfne  r13,r11
        l.bf    1b
        l.addi  r13,r13,16
 
        /* Enable DC */
        l.mfspr r13,r0,SPR_SR
        l.ori   r13,r13,SPR_SR_DCE
        l.mtspr r0,r13,SPR_SR
 
        l.jr    r9
        l.nop
 
_dc_disable:
        /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        l.jr    r9
        l.nop
 
        /* dtlb_ic_test(unsigned long add, unsigned long set) */
_lo_dtlb_ci_test:
        l.addi  r1,r1,-4
        l.sw    0(r1),r9
 
        l.addi  r8,r0,0
 
        l.movhi r5,hi(0x01234567)
        l.ori   r5,r5,lo(0x01234567)
        l.sw    0(r3),r5
        l.movhi r5,hi(0x89abcdef)
        l.ori   r5,r5,lo(0x89abcdef)
        l.sw    (PAGE_SIZE - 4)(r3),r5
 
        l.ori   r5,r3,SPR_DTLBMR_V
        l.mtspr r4,r5,SPR_DTLBMR_BASE(0)
 
        l.ori   r5,r3,(DTLB_PR_NOLIMIT  | SPR_DTLBTR_CI)
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
 
        l.addi  r5,r3,PAGE_SIZE
        l.ori   r5,r5,SPR_DTLBMR_V
        l.addi  r6,r4,1
        l.mtspr r6,r5,SPR_DTLBMR_BASE(0)
 
        l.addi  r5,r3,PAGE_SIZE
        l.ori   r5,r5,(DTLB_PR_NOLIMIT  | SPR_DTLBTR_CI)
        l.addi  r6,r4,1
        l.mtspr r6,r5,SPR_DTLBTR_BASE(0)
 
        l.jal   _lo_dmmu_en
        l.nop
        l.jal   _dc_enable
        l.nop
 
        l.movhi r6,hi(0x01234567)
        l.ori   r6,r6,lo(0x01234567)
        l.lwz   r5,0(r3)
        l.sfeq  r6,r5
        l.bnf   11f
        l.nop
        l.movhi r6,hi(0x89abcdef)
        l.ori   r6,r6,lo(0x89abcdef)
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
        l.sfeq  r6,r5
        l.bnf   12f
        l.nop
 
        l.movhi r5,hi(0x76543210)
        l.ori   r5,r5,lo(0x76543210)
        l.sw    0(r3),r5
        l.movhi r5,hi(0xfedcba9)
        l.ori   r5,r5,lo(0xfedcba9)
        l.sw    (PAGE_SIZE - 4)(r3),r5
 
        l.jal   _lo_dmmu_dis
        l.nop
        l.ori   r5,r3,(DTLB_PR_NOLIMIT)
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
        l.jal   _lo_dmmu_en
        l.nop
 
        l.movhi r6,hi(0x76543210)
        l.ori   r6,r6,lo(0x76543210)
        l.lwz   r5,0(r3)
        l.sfeq  r6,r5
        l.bnf   13f
        l.nop
        l.movhi r6,hi(0xfedcba9)
        l.ori   r6,r6,lo(0xfedcba9)
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
        l.sfeq  r6,r5
        l.bnf   14f
        l.nop
 
        l.jal   _lo_dmmu_dis
        l.nop
        l.ori   r5,r3,(DTLB_PR_NOLIMIT | SPR_DTLBTR_CI)
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
        l.jal   _lo_dmmu_en
        l.nop
 
        l.movhi r5,hi(0x00112233)
        l.ori   r5,r5,lo(0x00112233)
        l.sw    0(r3),r5
#if 1
        l.movhi r5,hi(0x44556677)
        l.ori   r5,r5,lo(0x44556677)
        l.sw    4(r3),r5
        l.movhi r5,hi(0x8899aabb)
        l.ori   r5,r5,lo(0x8899aabb)
        l.sw    8(r3),r5
        l.movhi r5,hi(0xccddeeff)
        l.ori   r5,r5,lo(0xccddeeff)
        l.sw    12(r3),r5
#endif
        l.movhi r5,hi(0x44556677)
        l.ori   r5,r5,lo(0x44556677)
        l.sw    (PAGE_SIZE - 4)(r3),r5
 
        l.movhi r6,hi(0x00112233)
        l.ori   r6,r6,lo(0x00112233)
        l.lwz   r5,0(r3)
        l.sfeq  r6,r5
        l.bnf   15f
        l.nop
        l.movhi r6,hi(0x44556677)
        l.ori   r6,r6,lo(0x44556677)
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
        l.sfeq  r6,r5
        l.bnf   16f
        l.nop
 
        l.jal   _lo_dmmu_dis
        l.nop
        l.ori   r5,r3,(DTLB_PR_NOLIMIT)
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
        l.jal   _lo_dmmu_en
        l.nop
 
        l.movhi r6,hi(0x76543210)
        l.ori   r6,r6,lo(0x76543210)
        l.lwz   r5,0(r3)
        l.sfeq  r6,r5
        l.bnf   17f
        l.nop
 
        l.movhi r6,hi(0xfedcba9)
        l.ori   r6,r6,lo(0xfedcba9)
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
        l.sfeq  r6,r5
        l.bnf   18f
        l.nop
 
        /* Invalidate cache */
        l.jal   _dc_disable
        l.nop
 
        l.movhi r5,hi(0x00112233)
        l.ori   r5,r5,lo(0x00112233)
        l.sw    12(r3),r5
        l.movhi r5,hi(0x44556677)
        l.ori   r5,r5,lo(0x44556677)
        l.sw    8(r3),r5
        l.movhi r5,hi(0x8899aabb)
        l.ori   r5,r5,lo(0x8899aabb)
        l.sw    4(r3),r5
        l.movhi r5,hi(0xccddeeff)
        l.ori   r5,r5,lo(0xccddeeff)
        l.sw    0(r3),r5
        l.movhi r5,hi(0x44556677)
        l.ori   r5,r5,lo(0x44556677)
        l.sw    (PAGE_SIZE - 4)(r3),r5
 
        l.jal   _dc_enable
        l.nop
 
        /* I want this part to execute as fast as possible */
        l.jal   _ic_enable
        l.nop
 
        l.addi  r5,r3,PAGE_SIZE
 
        /* This jump is just to be shure that the following
           instructions will get into IC */
        l.j     1f
        l.nop
        /* This shuld trigger cahe line refill */
2:      l.lwz   r6,0(r3)
        l.j     2f
        /* This load is from non cached area and may cause some problems
           in previuos refill, which is probably still in progress */
        l.lwz   r6,0(r5)
1:      l.j     2b
        l.nop
2:
        /* Check the line that was previosly refilled */
        l.movhi r6,hi(0x00112233)
        l.ori   r6,r6,lo(0x00112233)
        l.lwz   r5,12(r3)
        l.sfeq  r6,r5
        l.bnf   19f
        l.nop
        l.movhi r6,hi(0x44556677)
        l.ori   r6,r6,lo(0x44556677)
        l.lwz   r5,8(r3)
        l.sfeq  r6,r5
        l.bnf   19f
        l.nop
        l.movhi r6,hi(0x8899aabb)
        l.ori   r6,r6,lo(0x8899aabb)
        l.lwz   r5,4(r3)
        l.sfeq  r6,r5
        l.bnf   19f
        l.nop
        l.movhi r6,hi(0xccddeeff)
        l.ori   r6,r6,lo(0xccddeeff)
        l.lwz   r5,0(r3)
        l.sfeq  r6,r5
        l.bnf   19f
        l.nop
 
        l.jal   _dc_disable
        l.nop
 
        l.jal   _lo_dmmu_dis
        l.nop
 
        l.j     10f
        l.nop
 
19:     l.addi  r8,r8,1
18:     l.addi  r8,r8,1
17:     l.addi  r8,r8,1
16:     l.addi  r8,r8,1
15:     l.addi  r8,r8,1
14:     l.addi  r8,r8,1
13:     l.addi  r8,r8,1
12:     l.addi  r8,r8,1
11:     l.addi  r8,r8,1
 
10:     l.jal   _dc_disable
        l.nop
 
        l.jal   _ic_disable
        l.nop
 
        l.jal   _lo_dmmu_dis
        l.nop
 
        l.addi  r11,r8,0
        l.sw    0(r0),r8
        l.sw    4(r0),r5
 
        l.lwz   r9,0(r1)
        l.jr    r9
        l.addi  r1,r1,4
 
        /* itlb_ic_test(unsigned long add, unsigned long set) */
_lo_itlb_ci_test:
        l.addi  r1,r1,-4
        l.sw    0(r1),r9
 
        l.addi  r8,r0,0
 
        /* Copy the code to the prepeared location */
        l.addi  r7,r0,88
        l.movhi r5,hi(_ci_test)
        l.ori   r5,r5,lo(_ci_test)
        l.addi  r6,r3,0
1:      l.lwz   r11,0(r5)
        l.sw    0(r6),r11
        l.addi  r5,r5,4
        l.addi  r6,r6,4
        l.addi  r7,r7,-4
        l.sfeqi r7,0
        l.bnf   1b
        l.nop
 
        l.ori   r5,r3,SPR_ITLBMR_V
        l.mtspr r4,r5,SPR_ITLBMR_BASE(0)
 
        l.ori   r5,r3,ITLB_PR_NOLIMIT
        l.mtspr r4,r5,SPR_ITLBTR_BASE(0)
 
        l.jal   _lo_immu_en
        l.nop
        l.jal   _ic_enable
        l.nop
 
        l.addi  r5,r0,0
        l.addi  r6,r0,0
        l.jalr  r3
        l.nop
 
        l.sfeqi r5,5
        l.bnf   11f
        l.nop
 
        /* Copy the code to the prepeared location */
        l.addi  r7,r0,20
        l.movhi r5,hi(_ic_refill_test)
        l.ori   r5,r5,lo(_ic_refill_test)
        l.addi  r6,r3,12
1:      l.lwz   r11,0(r5)
        l.sw    0(r6),r11
        l.addi  r5,r5,4
        l.addi  r6,r6,4
        l.addi  r7,r7,-4
        l.sfeqi r7,0
        l.bnf   1b
        l.nop
 
        l.jal   _ic_disable
        l.nop
        l.jal   _ic_enable
        l.nop
 
        l.addi  r5,r0,0
        l.addi  r6,r3,12
        l.jalr  r6
        l.nop
        l.addi  r6,r3,16
        l.jalr  r6
        l.nop
 
        l.sfeqi r5,4
        l.bnf   12f
        l.nop
 
        l.j     10f
        l.nop
 
12:     l.addi  r8,r8,1
11:     l.addi  r8,r8,1
 
10:     l.jal   _ic_disable
        l.nop
 
        l.jal   _lo_dmmu_dis
        l.nop
 
        l.addi  r11,r8,0
        l.sw    0(r0),r11
        l.sw    4(r0),r5
 
        l.lwz   r9,0(r1)
        l.jr    r9
        l.addi  r1,r1,4
 
_ci_test:
3:      l.addi  r5,r5,1
 
        l.sfeqi r6,0x01
        l.bnf   1f
        l.nop
 
        l.addi  r13,r0,-1
        l.xori  r13,r13,SPR_SR_IME
        l.mfspr r11,r0,SPR_SR
        l.and   r13,r11,r13
        l.mtspr r0,r13,SPR_SR
 
        l.ori   r7,r3,(ITLB_PR_NOLIMIT  | SPR_ITLBTR_CI)
        l.mtspr r4,r7,SPR_ITLBTR_BASE(0)
 
        l.mtspr r0,r11,SPR_SR
 
1:      l.lwz   r7,0(r3)
        l.addi  r7,r7,1
        l.sw    0(r3),r7
 
2:      l.addi  r6,r6,1
        l.sfeqi r6,3
        l.bnf   3b
        l.nop
 
        l.jr    r9
        l.nop
 
 
_ic_refill_test:
        l.jr    r9
        l.addi  r5,r5,1
        l.addi  r5,r5,1
        l.jr    r9
        l.addi  r5,r5,1

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Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [testbench/] [mmu_asm.S] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	410	simons	`#include "spr_defs.h"`
2
3	639	simons	`#define PAGE_SIZE 8192`
4			`#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE \| \`
5			`SPR_DTLBTR_UWE \| \`
6			`SPR_DTLBTR_SRE \| \`
7			`SPR_DTLBTR_SWE )`
8			`#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE \| \`
9			`SPR_ITLBTR_UXE )`
10			`.global _lo_dmmu_en`
11			`.global _lo_immu_en`
12			`.global _lo_dtlb_ci_test`
13			`.global _lo_itlb_ci_test`
14			`.global _testjump`
15			`.global _ic_enable`
16			`.global _ic_disable`
17			`.global _dc_enable`
18			`.global _dc_disable`
19	410	simons
20			`_lo_dmmu_en:`
21	639	simons	`l.mfspr r11,r0,SPR_SR`
22			`l.ori r11,r11,SPR_SR_DME`
23			`l.mtspr r0,r11,SPR_ESR_BASE`
24			`l.mtspr r0,r9,SPR_EPCR_BASE`
25			`l.rfe`
26			`l.nop`
27	410	simons
28	639	simons	`_lo_dmmu_dis:`
29			`l.addi r13,r0,-1`
30			`l.xori r13,r13,SPR_SR_DME`
31			`l.mfspr r11,r0,SPR_SR`
32			`l.and r11,r11,r13`
33			`l.mtspr r0,r11,SPR_SR`
34			`l.jr r9`
35			`l.nop`
36
37	410	simons	`_lo_immu_en:`
38	639	simons	`l.mfspr r11,r0,SPR_SR`
39			`l.ori r11,r11,SPR_SR_IME`
40			`l.mtspr r0,r11,SPR_ESR_BASE`
41			`l.mtspr r0,r9,SPR_EPCR_BASE`
42			`l.rfe`
43			`l.nop`
44	415	simons
45	639	simons	`_lo_immu_dis:`
46			`l.addi r13,r0,-1`
47			`l.xori r13,r13,SPR_SR_IME`
48			`l.mfspr r11,r0,SPR_SR`
49			`l.and r11,r11,r13`
50			`l.mtspr r0,r11,SPR_SR`
51			`l.jr r9`
52			`l.nop`
53
54	415	simons	`_testjump:`
55	639	simons	`l.movhi r5,0x4800`
56			`l.ori r5,r5,0x4800`
57			`l.sw 0x0(r3),r5`
58			`l.movhi r5,0x1500`
59			`l.ori r5,r5,0x0000`
60			`l.sw 0x4(r3),r5`
61			`l.or r5,r0,r9`
62			`l.jalr r4`
63			`l.nop`
64			`l.or r9,r0,r5`
65			`l.jr r9`
66			`l.nop`
67
68			`_ic_enable:`
69			`/* Disable IC */`
70			`l.mfspr r13,r0,SPR_SR`
71			`l.addi r11,r0,-1`
72			`l.xori r11,r11,SPR_SR_ICE`
73			`l.and r11,r13,r11`
74			`l.mtspr r0,r11,SPR_SR`
75
76			`/* Invalidate IC */`
77			`l.addi r13,r0,0`
78			`l.addi r11,r0,8192`
79			`1:`
80			`l.mtspr r0,r13,SPR_ICBIR`
81			`l.sfne r13,r11`
82			`l.bf 1b`
83			`l.addi r13,r13,16`
84
85			`/* Enable IC */`
86			`l.mfspr r13,r0,SPR_SR`
87			`l.ori r13,r13,SPR_SR_ICE`
88			`l.mtspr r0,r13,SPR_SR`
89			`l.nop`
90			`l.nop`
91			`l.nop`
92			`l.nop`
93			`l.nop`
94
95			`l.jr r9`
96			`l.nop`
97
98			`_ic_disable:`
99			`/* Disable IC */`
100			`l.mfspr r13,r0,SPR_SR`
101			`l.addi r11,r0,-1`
102			`l.xori r11,r11,SPR_SR_ICE`
103			`l.and r11,r13,r11`
104			`l.mtspr r0,r11,SPR_SR`
105
106			`l.jr r9`
107			`l.nop`
108
109			`_dc_enable:`
110			`/* Disable DC */`
111			`l.mfspr r13,r0,SPR_SR`
112			`l.addi r11,r0,-1`
113			`l.xori r11,r11,SPR_SR_DCE`
114			`l.and r11,r13,r11`
115			`l.mtspr r0,r11,SPR_SR`
116
117			`/* Flush DC */`
118			`l.addi r13,r0,0`
119			`l.addi r11,r0,8192`
120			`1:`
121			`l.mtspr r0,r13,SPR_DCBIR`
122			`l.sfne r13,r11`
123			`l.bf 1b`
124			`l.addi r13,r13,16`
125
126			`/* Enable DC */`
127			`l.mfspr r13,r0,SPR_SR`
128			`l.ori r13,r13,SPR_SR_DCE`
129			`l.mtspr r0,r13,SPR_SR`
130
131			`l.jr r9`
132			`l.nop`
133
134			`_dc_disable:`
135			`/* Disable DC */`
136			`l.mfspr r13,r0,SPR_SR`
137			`l.addi r11,r0,-1`
138			`l.xori r11,r11,SPR_SR_DCE`
139			`l.and r11,r13,r11`
140			`l.mtspr r0,r11,SPR_SR`
141
142			`l.jr r9`
143			`l.nop`
144
145			`/* dtlb_ic_test(unsigned long add, unsigned long set) */`
146			`_lo_dtlb_ci_test:`
147			`l.addi r1,r1,-4`
148			`l.sw 0(r1),r9`
149
150			`l.addi r8,r0,0`
151
152			`l.movhi r5,hi(0x01234567)`
153			`l.ori r5,r5,lo(0x01234567)`
154			`l.sw 0(r3),r5`
155			`l.movhi r5,hi(0x89abcdef)`
156			`l.ori r5,r5,lo(0x89abcdef)`
157			`l.sw (PAGE_SIZE - 4)(r3),r5`
158
159			`l.ori r5,r3,SPR_DTLBMR_V`
160			`l.mtspr r4,r5,SPR_DTLBMR_BASE(0)`
161
162			`l.ori r5,r3,(DTLB_PR_NOLIMIT \| SPR_DTLBTR_CI)`
163			`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`
164
165			`l.addi r5,r3,PAGE_SIZE`
166			`l.ori r5,r5,SPR_DTLBMR_V`
167			`l.addi r6,r4,1`
168			`l.mtspr r6,r5,SPR_DTLBMR_BASE(0)`
169
170			`l.addi r5,r3,PAGE_SIZE`
171			`l.ori r5,r5,(DTLB_PR_NOLIMIT \| SPR_DTLBTR_CI)`
172			`l.addi r6,r4,1`
173			`l.mtspr r6,r5,SPR_DTLBTR_BASE(0)`
174
175			`l.jal _lo_dmmu_en`
176			`l.nop`
177			`l.jal _dc_enable`
178			`l.nop`
179
180			`l.movhi r6,hi(0x01234567)`
181			`l.ori r6,r6,lo(0x01234567)`
182			`l.lwz r5,0(r3)`
183			`l.sfeq r6,r5`
184			`l.bnf 11f`
185			`l.nop`
186			`l.movhi r6,hi(0x89abcdef)`
187			`l.ori r6,r6,lo(0x89abcdef)`
188			`l.lwz r5,(PAGE_SIZE - 4)(r3)`
189			`l.sfeq r6,r5`
190			`l.bnf 12f`
191			`l.nop`
192
193			`l.movhi r5,hi(0x76543210)`
194			`l.ori r5,r5,lo(0x76543210)`
195			`l.sw 0(r3),r5`
196			`l.movhi r5,hi(0xfedcba9)`
197			`l.ori r5,r5,lo(0xfedcba9)`
198			`l.sw (PAGE_SIZE - 4)(r3),r5`
199
200			`l.jal _lo_dmmu_dis`
201			`l.nop`
202			`l.ori r5,r3,(DTLB_PR_NOLIMIT)`
203			`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`
204			`l.jal _lo_dmmu_en`
205			`l.nop`
206
207			`l.movhi r6,hi(0x76543210)`
208			`l.ori r6,r6,lo(0x76543210)`
209			`l.lwz r5,0(r3)`
210			`l.sfeq r6,r5`
211			`l.bnf 13f`
212			`l.nop`
213			`l.movhi r6,hi(0xfedcba9)`
214			`l.ori r6,r6,lo(0xfedcba9)`
215			`l.lwz r5,(PAGE_SIZE - 4)(r3)`
216			`l.sfeq r6,r5`
217			`l.bnf 14f`
218			`l.nop`
219
220			`l.jal _lo_dmmu_dis`
221			`l.nop`
222			`l.ori r5,r3,(DTLB_PR_NOLIMIT \| SPR_DTLBTR_CI)`
223			`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`
224			`l.jal _lo_dmmu_en`
225			`l.nop`
226
227			`l.movhi r5,hi(0x00112233)`
228			`l.ori r5,r5,lo(0x00112233)`
229			`l.sw 0(r3),r5`
230			`#if 1`
231			`l.movhi r5,hi(0x44556677)`
232			`l.ori r5,r5,lo(0x44556677)`
233			`l.sw 4(r3),r5`
234			`l.movhi r5,hi(0x8899aabb)`
235			`l.ori r5,r5,lo(0x8899aabb)`
236			`l.sw 8(r3),r5`
237			`l.movhi r5,hi(0xccddeeff)`
238			`l.ori r5,r5,lo(0xccddeeff)`
239			`l.sw 12(r3),r5`
240			`#endif`
241			`l.movhi r5,hi(0x44556677)`
242			`l.ori r5,r5,lo(0x44556677)`
243			`l.sw (PAGE_SIZE - 4)(r3),r5`
244
245			`l.movhi r6,hi(0x00112233)`
246			`l.ori r6,r6,lo(0x00112233)`
247			`l.lwz r5,0(r3)`
248			`l.sfeq r6,r5`
249			`l.bnf 15f`
250			`l.nop`
251			`l.movhi r6,hi(0x44556677)`
252			`l.ori r6,r6,lo(0x44556677)`
253			`l.lwz r5,(PAGE_SIZE - 4)(r3)`
254			`l.sfeq r6,r5`
255			`l.bnf 16f`
256			`l.nop`
257
258			`l.jal _lo_dmmu_dis`
259			`l.nop`
260			`l.ori r5,r3,(DTLB_PR_NOLIMIT)`
261			`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`
262			`l.jal _lo_dmmu_en`
263			`l.nop`
264
265			`l.movhi r6,hi(0x76543210)`
266			`l.ori r6,r6,lo(0x76543210)`
267			`l.lwz r5,0(r3)`
268			`l.sfeq r6,r5`
269			`l.bnf 17f`
270			`l.nop`
271
272			`l.movhi r6,hi(0xfedcba9)`
273			`l.ori r6,r6,lo(0xfedcba9)`
274			`l.lwz r5,(PAGE_SIZE - 4)(r3)`
275			`l.sfeq r6,r5`
276			`l.bnf 18f`
277			`l.nop`
278
279			`/* Invalidate cache */`
280			`l.jal _dc_disable`
281			`l.nop`
282
283			`l.movhi r5,hi(0x00112233)`
284			`l.ori r5,r5,lo(0x00112233)`
285			`l.sw 12(r3),r5`
286			`l.movhi r5,hi(0x44556677)`
287			`l.ori r5,r5,lo(0x44556677)`
288			`l.sw 8(r3),r5`
289			`l.movhi r5,hi(0x8899aabb)`
290			`l.ori r5,r5,lo(0x8899aabb)`
291			`l.sw 4(r3),r5`
292			`l.movhi r5,hi(0xccddeeff)`
293			`l.ori r5,r5,lo(0xccddeeff)`
294			`l.sw 0(r3),r5`
295			`l.movhi r5,hi(0x44556677)`
296			`l.ori r5,r5,lo(0x44556677)`
297			`l.sw (PAGE_SIZE - 4)(r3),r5`
298
299			`l.jal _dc_enable`
300			`l.nop`
301
302			`/* I want this part to execute as fast as possible */`
303			`l.jal _ic_enable`
304			`l.nop`
305
306			`l.addi r5,r3,PAGE_SIZE`
307
308			`/* This jump is just to be shure that the following`
309			`instructions will get into IC */`
310			`l.j 1f`
311			`l.nop`
312			`/* This shuld trigger cahe line refill */`
313			`2: l.lwz r6,0(r3)`
314			`l.j 2f`
315			`/* This load is from non cached area and may cause some problems`
316			`in previuos refill, which is probably still in progress */`
317			`l.lwz r6,0(r5)`
318			`1: l.j 2b`
319			`l.nop`
320			`2:`
321			`/* Check the line that was previosly refilled */`
322			`l.movhi r6,hi(0x00112233)`
323			`l.ori r6,r6,lo(0x00112233)`
324			`l.lwz r5,12(r3)`
325			`l.sfeq r6,r5`
326			`l.bnf 19f`
327			`l.nop`
328			`l.movhi r6,hi(0x44556677)`
329			`l.ori r6,r6,lo(0x44556677)`
330			`l.lwz r5,8(r3)`
331			`l.sfeq r6,r5`
332			`l.bnf 19f`
333			`l.nop`
334			`l.movhi r6,hi(0x8899aabb)`
335			`l.ori r6,r6,lo(0x8899aabb)`
336			`l.lwz r5,4(r3)`
337			`l.sfeq r6,r5`
338			`l.bnf 19f`
339			`l.nop`
340			`l.movhi r6,hi(0xccddeeff)`
341			`l.ori r6,r6,lo(0xccddeeff)`
342			`l.lwz r5,0(r3)`
343			`l.sfeq r6,r5`
344			`l.bnf 19f`
345			`l.nop`
346
347			`l.jal _dc_disable`
348			`l.nop`
349
350			`l.jal _lo_dmmu_dis`
351			`l.nop`
352
353			`l.j 10f`
354			`l.nop`
355
356			`19: l.addi r8,r8,1`
357			`18: l.addi r8,r8,1`
358			`17: l.addi r8,r8,1`
359			`16: l.addi r8,r8,1`
360			`15: l.addi r8,r8,1`
361			`14: l.addi r8,r8,1`
362			`13: l.addi r8,r8,1`
363			`12: l.addi r8,r8,1`
364			`11: l.addi r8,r8,1`
365
366			`10: l.jal _dc_disable`
367			`l.nop`
368
369			`l.jal _ic_disable`
370			`l.nop`
371
372			`l.jal _lo_dmmu_dis`
373			`l.nop`
374
375			`l.addi r11,r8,0`
376			`l.sw 0(r0),r8`
377			`l.sw 4(r0),r5`
378
379			`l.lwz r9,0(r1)`
380			`l.jr r9`
381			`l.addi r1,r1,4`
382
383			`/* itlb_ic_test(unsigned long add, unsigned long set) */`
384			`_lo_itlb_ci_test:`
385			`l.addi r1,r1,-4`
386			`l.sw 0(r1),r9`
387
388			`l.addi r8,r0,0`
389
390			`/* Copy the code to the prepeared location */`
391			`l.addi r7,r0,88`
392			`l.movhi r5,hi(_ci_test)`
393			`l.ori r5,r5,lo(_ci_test)`
394			`l.addi r6,r3,0`
395			`1: l.lwz r11,0(r5)`
396			`l.sw 0(r6),r11`
397			`l.addi r5,r5,4`
398			`l.addi r6,r6,4`
399			`l.addi r7,r7,-4`
400			`l.sfeqi r7,0`
401			`l.bnf 1b`
402			`l.nop`
403
404			`l.ori r5,r3,SPR_ITLBMR_V`
405			`l.mtspr r4,r5,SPR_ITLBMR_BASE(0)`
406
407			`l.ori r5,r3,ITLB_PR_NOLIMIT`
408			`l.mtspr r4,r5,SPR_ITLBTR_BASE(0)`
409
410			`l.jal _lo_immu_en`
411			`l.nop`
412			`l.jal _ic_enable`
413			`l.nop`
414
415			`l.addi r5,r0,0`
416			`l.addi r6,r0,0`
417			`l.jalr r3`
418			`l.nop`
419
420			`l.sfeqi r5,5`
421			`l.bnf 11f`
422			`l.nop`
423
424			`/* Copy the code to the prepeared location */`
425			`l.addi r7,r0,20`
426			`l.movhi r5,hi(_ic_refill_test)`
427			`l.ori r5,r5,lo(_ic_refill_test)`
428			`l.addi r6,r3,12`
429			`1: l.lwz r11,0(r5)`
430			`l.sw 0(r6),r11`
431			`l.addi r5,r5,4`
432			`l.addi r6,r6,4`
433			`l.addi r7,r7,-4`
434			`l.sfeqi r7,0`
435			`l.bnf 1b`
436			`l.nop`
437
438			`l.jal _ic_disable`
439			`l.nop`
440			`l.jal _ic_enable`
441			`l.nop`
442
443			`l.addi r5,r0,0`
444			`l.addi r6,r3,12`
445			`l.jalr r6`
446			`l.nop`
447			`l.addi r6,r3,16`
448			`l.jalr r6`
449			`l.nop`
450
451			`l.sfeqi r5,4`
452			`l.bnf 12f`
453			`l.nop`
454
455			`l.j 10f`
456			`l.nop`
457
458			`12: l.addi r8,r8,1`
459			`11: l.addi r8,r8,1`
460
461			`10: l.jal _ic_disable`
462			`l.nop`
463
464			`l.jal _lo_dmmu_dis`
465			`l.nop`
466
467			`l.addi r11,r8,0`
468			`l.sw 0(r0),r11`
469			`l.sw 4(r0),r5`
470
471			`l.lwz r9,0(r1)`
472			`l.jr r9`
473			`l.addi r1,r1,4`
474
475			`_ci_test:`
476			`3: l.addi r5,r5,1`
477
478			`l.sfeqi r6,0x01`
479			`l.bnf 1f`
480			`l.nop`
481
482			`l.addi r13,r0,-1`
483			`l.xori r13,r13,SPR_SR_IME`
484			`l.mfspr r11,r0,SPR_SR`
485			`l.and r13,r11,r13`
486			`l.mtspr r0,r13,SPR_SR`
487
488			`l.ori r7,r3,(ITLB_PR_NOLIMIT \| SPR_ITLBTR_CI)`
489			`l.mtspr r4,r7,SPR_ITLBTR_BASE(0)`
490
491			`l.mtspr r0,r11,SPR_SR`
492
493			`1: l.lwz r7,0(r3)`
494			`l.addi r7,r7,1`
495			`l.sw 0(r3),r7`
496
497			`2: l.addi r6,r6,1`
498			`l.sfeqi r6,3`
499			`l.bnf 3b`
500			`l.nop`
501
502			`l.jr r9`
503			`l.nop`
504
505
506			`_ic_refill_test:`
507			`l.jr r9`
508			`l.addi r5,r5,1`
509			`l.addi r5,r5,1`
510			`l.jr r9`
511			`l.addi r5,r5,1`