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[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 1484

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/* abstract.c -- Abstract entities
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Abstract memory and routines that go with this. I need to
add all sorts of other abstract entities. Currently we have
only memory. */
 
#include <stdlib.h>
#include <stdio.h>
#include <ctype.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
 
#include "arch.h"
#include "parse.h"
#include "abstract.h"
#include "sim-config.h"
#include "labels.h"
#include "except.h"
#include "debug_unit.h"
#include "opcode/or32.h"
#include "spr_defs.h"
#include "execute.h"
#include "sprs.h"
#include "support/profile.h"
#include "dmmu.h"
#include "immu.h"
#include "dcache_model.h"
#include "icache_model.h"
#include "debug.h"
#include "stats.h"
 
#if DYNAMIC_EXECUTION
#include "dyn_rec.h"
#endif
 
extern char *disassembled;
 
/* Pointer to memory area descriptions that are assigned to individual
   peripheral devices. */
struct dev_memarea *dev_list;
 
/* Temporary variable to increase speed.  */
struct dev_memarea *cur_area;
 
/* Pointer to memory controller device descriptor.  */
struct dev_memarea *mc_area = (struct dev_memarea *)0;
 
/* These are set by mmu if cache inhibit bit is set for current acces.  */
int data_ci, insn_ci;
 
/* Virtual address of current access. */
oraddr_t cur_vadd;
 
/* Calculates bit mask to fit the data */
unsigned int bit_mask (uint32_t data) {
  int i = 0;
  data--;
  while (data >> i)
    data |= 1 << i++;
  return data;
}
 
/* Register read and write function for a memory area.
   addr is inside the area, if addr & addr_mask == addr_compare
   (used also by peripheral devices like 16450 UART etc.) */
void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,
                         uint32_t size, unsigned granularity, unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  struct dev_memarea **pptmp;
  unsigned int size_mask = bit_mask (size);
  int found_error = 0;
  addr_compare &= addr_mask;
 
  debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",
        addr_mask, addr_compare, addr_compare | bit_mask (size), size,
        granularity);
  /* Go to the end of the list. */
  for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
    if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
     || (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
      if (!found_error) {
        fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
        fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                         ", size %08"PRIx32", gran %iB\n",
                 addr_mask, addr_compare, addr_compare | bit_mask (size), size,
                 granularity);
      }
      found_error = 1;
      fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                       ", size %08"PRIx32", gran %iB\n",
               (*pptmp)->addr_mask, (*pptmp)->addr_compare,
               (*pptmp)->addr_compare | (*pptmp)->size_mask,
               (*pptmp)->size, (*pptmp)->granularity);
    }
 
  if (found_error)
    exit (-1);
 
  cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
 
  if (mc_dev)
    mc_area = *pptmp;
 
  (*pptmp)->addr_mask = addr_mask;
  (*pptmp)->addr_compare = addr_compare;
  (*pptmp)->size = size;
  (*pptmp)->size_mask = size_mask;
  (*pptmp)->granularity = granularity;
  (*pptmp)->readfunc = readfunc;
  (*pptmp)->writefunc = writefunc;
  (*pptmp)->log = 0;
  (*pptmp)->delayr = 2;
  (*pptmp)->delayw = 2;
  (*pptmp)->priv_dat = dat;
  (*pptmp)->chip_select = -1;
  (*pptmp)->next = NULL;
}
 
/* Register read and write function for a memory area.
   Memory areas should be aligned. Memory area is rounded up to
   fit the nearest 2^n aligment.
   (used also by peripheral devices like 16450 UART etc.)
   If mc_dev is 1, this means that this device will be checked first for match
   and will be accessed in case of overlaping memory spaces.
   Only one device can have this set to 1 (used for memory controller) */
void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,
                         unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  unsigned int size_mask = bit_mask (size);
  unsigned int addr_mask = ~size_mask;
  register_memoryarea_mask (addr_mask, addr & addr_mask,
                      size_mask + 1, granularity, mc_dev,
                      readfunc, writefunc, dat);
}
 
 
/* Check if access is to registered area of memory. */
inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
{
  struct dev_memarea *ptmp;
 
  /* Check memory controller space first */
  if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
    return cur_area = mc_area;
 
  /* Check cached value */
  if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
    return cur_area;
 
  /* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
    if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
      return cur_area = ptmp;
  return cur_area = NULL;
}
 
/* Finds the memory area for the address and adjust the read and write delays for it. */
void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)
{
  if (verify_memoryarea(memaddr)) {
    cur_area->delayr = delayr;
    cur_area->delayw = delayw;
  }
}
 
/* for cpu accesses
 *
 * STATISTICS: check cpu/common/parse.c
 */
inline uint32_t evalsim_mem32(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint32_t evalsim_mem32_void(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 0));
}
 
uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      break;
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
    if (cpu_access)
      runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);
  }
  return temp;
}
 
/* for cpu accesses */
inline uint16_t evalsim_mem16(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint16_t evalsim_mem16_void(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 0));
}
 
uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr * 2;
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);
      if (memaddr & 2)
        temp &= 0xffff;
      else
        temp >>= 16;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline uint8_t evalsim_mem8(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint8_t evalsim_mem8_void(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 0));
}
 
uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 2:
      temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);
      if (memaddr & 1)
        temp &= 0xff;
      else
        temp >>= 8;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);
      temp >>= 8 * (3 - (memaddr & 3));
      temp &= 0xff;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_READ);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK
 */
uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR
             ") in eval_direct32()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
//  memaddr = simulate_ic_mmu_fetch(memaddr);
 
  cur_vadd = memaddr;
 
#if !(DYNAMIC_EXECUTION)
  memaddr = immu_translate(memaddr);
 
  if (except_pending)
    return 0;
#endif
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);
 
  if (config.ic.enabled)
    temp = ic_simulate_fetch(memaddr);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK
 */
uint32_t eval_insn_direct(oraddr_t memaddr, int* breakpoint, int through_mmu)
{
  uint32_t temp;
  int brk;
 
  cur_vadd = memaddr;
 
  if(through_mmu)
    memaddr = peek_into_itlb(memaddr);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress, memaddr);
 
  temp = eval_direct32(memaddr, &brk, 0, 0);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData, temp);
 
  return temp;
}
 
 
/* Returns 16-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
{
  uint16_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_READ);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = (uint16_t)dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint16_t eval_direct16(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR
             ") in eval_direct16()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 8-bit values from mem array.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
{
  uint8_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_READ);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);  /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = (uint8_t)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint8_t eval_direct8(oraddr_t memaddr, int *breakpoint, int through_mmu,
                     int through_dc)
{
  uint8_t temp;
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = (unsigned char)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR
             ") in eval_direct8()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline void setsim_mem32(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem32_void(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 0));
}
 
void setsim_mem32_atomic(oraddr_t memaddr, uint32_t value, int cpu_access)
{
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 1:
      cur_area->writefunc(memaddr    , (value >> 24) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, (value >> 16) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, (value >>  8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 3, (value      ) & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 4;
      break;
    case 2:
      cur_area->writefunc(memaddr, (value >> 16) & 0xFFFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
#if DYNAMIC_EXECUTION
    /* FIXME: Do this with mprotect() */
    struct dyn_page *dp;
 
    /* Since the locations 0x0-0xff are nearly always written to in an exception
     * handler, ignore any writes to these locations.  If code ends up jumping
     * out there, we'll recompile when the jump actually happens. */
    if((memaddr > 0x100) && (dp = find_dynd_page(memaddr)) && !dp->dirty)
      dirtyfy_page(dp);
#endif
  } else {
    PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem16(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem16_void(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 0));
}
 
void setsim_mem16_atomic(oraddr_t memaddr, uint16_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, (value >> 8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, value & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    case 2:
      cur_area->writefunc(memaddr, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 4:
      temp = evalsim_mem32_void(memaddr & ~ADDR_C(3));
      temp &= 0xffff << ((memaddr & 2) ? 16 : 0);
      temp |= (unsigned long)(value & 0xffff) << ((memaddr & 2) ? 0 : 16);
      setsim_mem32_atomic(memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
#if DYNAMIC_EXECUTION
    /* FIXME: Do this with mprotect() */
    struct dyn_page *dp;
 
    /* Since the locations 0x0-0xff are nearly always written to in an exception
     * handler, ignore any writes to these locations.  If code ends up jumping
     * out there, we'll recompile when the jump actually happens. */
 
    if((memaddr > 0x100) && (dp = find_dynd_page(memaddr)) && !dp->dirty)
      dirtyfy_page(dp);
#endif
  } else {
    PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem8(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem8_void(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 0));
}
 
void setsim_mem8_atomic(oraddr_t memaddr, uint8_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch (cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 2:
      temp = evalsim_mem16_void (memaddr & ~ADDR_C(1));
      temp &= 0xff << ((memaddr & 1) ? 8 : 0);
      temp |= (unsigned short)(value & 0xff) << ((memaddr & 1) ? 0 : 8);
      setsim_mem16_atomic (memaddr & ~ADDR_C(1), temp, cpu_access);
      break;
    case 4:
      temp = evalsim_mem32_void (memaddr & ~ADDR_C(3));
      temp &= ~(0xff << (8 * (3 - (memaddr & 3))));
      temp |= (unsigned long)(value & 0xff) << (8 * (3 - (memaddr & 3)));
      setsim_mem32_atomic (memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    }
#if DYNAMIC_EXECUTION
    /* FIXME: Do this with mprotect() */
    struct dyn_page *dp;
 
    /* Since the locations 0x0-0xff are nearly always written to in an exception
     * handler, ignore any writes to these locations.  If code ends up jumping
     * out there, we'll recompile when the jump actually happens. */
 
    if((memaddr > 0x100) && (dp = find_dynd_page(memaddr)) && !dp->dirty)
      dirtyfy_page(dp);
#endif
  } else {
    PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* Set mem, 32-bit. Big endian version.
 *
 * STATISTICS OK. (the only suspicious usage is in sim-cmd.c,
 *                 where this instruction is used for patching memory,
 *                 wether this is cpu or architectual access is yet to
 *                 be decided)
 */
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct32(oraddr_t memaddr, uint32_t value,int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 1, through_dc);
  }
 
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
             memaddr, value);
}
 
 
/* Set mem, 16-bit. Big endian version. */
 
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct16(oraddr_t memaddr, uint16_t value, int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
             memaddr, value);
}
 
/* Set mem, 8-bit. */
 
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending) return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct8(oraddr_t memaddr, uint8_t value, int* breakpoint,
                 int through_mmu, int through_dc)
{
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
             memaddr, value);
}
 
 
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
{
  oraddr_t i, j;
  struct label_entry *tmp;
  int ilen = disasm ? 4 : 16;
  int breakpoint;
 
  for(i = from; i < to; i += ilen) {
    PRINTF("%"PRIxADDR": ", i);
    for (j = 0; j < ilen;) {
      if (!disasm) {
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
          PRINTF("%02"PRIx8" ", eval_direct8(i + j, &breakpoint, 0, 0));
        } else PRINTF("XX ");
        j++;
      } else {
        uint32_t _insn = eval_direct32(i, &breakpoint, 0, 0);
        int index = insn_decode (_insn);
        int len = insn_len (index);
 
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
 
          PRINTF(": %08"PRIx32" ", _insn);
          if (index >= 0) {
            disassemble_insn (_insn);
            PRINTF(" %s", disassembled);
          } else
            PRINTF("<invalid>");
        } else PRINTF("XXXXXXXX");
        j += len;
      }
    }
    if (nl)
      PRINTF ("\n");
  }
}
 
uint32_t simmem_read_word(oraddr_t addr, void *priv_dat) {
  return *(uint32_t *)(priv_dat + (addr & cur_area->size_mask));
}
 
void simmem_write_word(oraddr_t addr, uint32_t value, void *priv_dat) {
  *(uint32_t *)(priv_dat + (addr & cur_area->size_mask)) = value;
}
 
uint32_t simmem_read_zero(oraddr_t addr, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory read from non-read memory area 0x%"
                     PRIxADDR".\n", addr);
  return 0;
}
 
void simmem_write_null(oraddr_t addr, uint32_t value, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory write to 0x%"PRIxADDR", non-write memory area (value 0x%08"PRIx32").\n", addr, value);
}
 
/* Initialize memory table from a config struct */
 
void init_memory_table ()
{
  /* If nothing was defined, use default memory block */
  if (config.memory.nmemories) {
    int i;
    for (i = 0; i < config.memory.nmemories; i++) {
      oraddr_t start = config.memory.table[i].baseaddr;
      uint32_t length = config.memory.table[i].size;
      char *type = config.memory.table[i].name;
      int rd = config.memory.table[i].delayr;
      int wd = config.memory.table[i].delayw;
      int ce = config.memory.table[i].ce;
      void *mem = malloc (length);
 
      if (config.sim.verbose)
        debug (1, "%"PRIxADDR" %08"PRIx32" (%"PRIi32" KB): %s (activated by CE%i; read delay = %icyc, write delay = %icyc)\n",
          start, length, length >> 10, type, ce, rd, wd);
 
      if (!mem) {
        fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
        exit (-1);
      }
 
      register_memoryarea(start, length, 4, 0, &simmem_read_word,
                          &simmem_write_word, mem);
      cur_area->chip_select = ce;
      cur_area->valid = 1;
      cur_area->delayw = wd;
      cur_area->delayr = rd;
      if (config.memory.table[i].log[0] != '\0') {
        if ((cur_area->log = fopen (config.memory.table[i].log, "wt+")) == NULL)
          fprintf (stderr, "WARNING: Cannot open '%s'.\n",
                   config.memory.table[i].log);
      } else
        cur_area->log = NULL;
    }
    PRINTF ("\n");
  } else {
    void *mem = malloc (DEFAULT_MEMORY_LEN);
    if (config.sim.verbose)
      fprintf (stderr, "WARNING: Memory not defined, assuming standard configuration.\n");
 
    if (!mem) {
      fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
      exit (-1);
    }
 
    register_memoryarea(DEFAULT_MEMORY_START, DEFAULT_MEMORY_LEN, 4, 0,
                        &simmem_read_word, &simmem_write_word, mem);
    cur_area->chip_select = 0;
    cur_area->valid = 1;
    cur_area->delayw = 1;
    cur_area->delayr = 1;
    cur_area->log = NULL;
  }
}
 
/* Changes read/write memory in read/write only */
 
void lock_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->delayr < 0 && ptmp->readfunc == &simmem_read_word)
      ptmp->readfunc = &simmem_read_zero;
    if (ptmp->delayw < 0 && ptmp->writefunc == &simmem_write_word)
      ptmp->writefunc = &simmem_write_null;
 
    /* If this mem area is not for memory chip under MC control
       then this area is valid all the time */
    if (ptmp->readfunc != &simmem_read_word) {
      ptmp->valid = 1;
      ptmp->chip_select = -1;
    }
  }
}
 
/* Closes files, etc. */
 
void done_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->log)
      fclose (ptmp->log);
  }
}
 
/* Displays current memory configuration */
 
void memory_table_status ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32
            ", gran %iB\n",
      ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
      ptmp->size, ptmp->granularity);
    PRINTF ("\t");
    if (ptmp->delayr >= 0)
      PRINTF ("read delay = %i cycles, ", ptmp->delayr);
    else
      PRINTF ("reads not possible, ");
 
    if (ptmp->delayw >= 0)
      PRINTF ("write delay = %i cycles", ptmp->delayw);
    else
      PRINTF ("writes not possible");
 
    if (ptmp->log)
      PRINTF (", (logged)\n");
    else
      PRINTF ("\n");
  }
}
 
/* Outputs time in pretty form to dest string */
 
char *generate_time_pretty (char *dest, long time_ps)
{
  int exp3 = 0;
  if (time_ps) {
    while ((time_ps % 1000) == 0) {
      time_ps /= 1000;
      exp3++;
    }
  }
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
  return dest;
}

Line No.	Rev	Author	Line
1	2	cvs	`/* abstract.c -- Abstract entities`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20	66	lampret	`/* Abstract memory and routines that go with this. I need to`
21	2	cvs	`add all sorts of other abstract entities. Currently we have`
22			`only memory. */`
23
24	221	markom	`#include <stdlib.h>`
25	2	cvs	`#include <stdio.h>`
26			`#include <ctype.h>`
27			`#include <string.h>`
28
29	6	lampret	`#include "config.h"`
30	1350	nogj
31			`#ifdef HAVE_INTTYPES_H`
32			`#include <inttypes.h>`
33			`#endif`
34
35			`#include "port.h"`
36	6	lampret
37	1350	nogj	`#include "arch.h"`
38	2	cvs	`#include "parse.h"`
39			`#include "abstract.h"`
40	1358	nogj	`#include "sim-config.h"`
41	261	markom	`#include "labels.h"`
42	32	lampret	`#include "except.h"`
43	123	markom	`#include "debug_unit.h"`
44	134	markom	`#include "opcode/or32.h"`
45	1432	nogj	`#include "spr_defs.h"`
46			`#include "execute.h"`
47			`#include "sprs.h"`
48	547	markom	`#include "support/profile.h"`
49	1308	phoenix	`#include "dmmu.h"`
50	1446	nogj	`#include "immu.h"`
51	1308	phoenix	`#include "dcache_model.h"`
52			`#include "icache_model.h"`
53			`#include "debug.h"`
54	1344	nogj	`#include "stats.h"`
55	2	cvs
56	1452	nogj	`#if DYNAMIC_EXECUTION`
57			`#include "dyn_rec.h"`
58			`#endif`
59
60	138	markom	`extern char *disassembled;`
61	2	cvs
62	30	lampret	`/* Pointer to memory area descriptions that are assigned to individual`
63			`peripheral devices. */`
64			`struct dev_memarea *dev_list;`
65
66	221	markom	`/* Temporary variable to increase speed. */`
67			`struct dev_memarea *cur_area;`
68
69	970	simons	`/* Pointer to memory controller device descriptor. */`
70			`struct dev_memarea mc_area = (struct dev_memarea )0;`
71
72	638	simons	`/* These are set by mmu if cache inhibit bit is set for current acces. */`
73			`int data_ci, insn_ci;`
74
75	525	simons	`/* Virtual address of current access. */`
76	1350	nogj	`oraddr_t cur_vadd;`
77	525	simons
78	261	markom	`/* Calculates bit mask to fit the data */`
79	1350	nogj	`unsigned int bit_mask (uint32_t data) {`
80	261	markom	`int i = 0;`
81			`data--;`
82	382	markom	`while (data >> i)`
83	261	markom	`data \|= 1 << i++;`
84			`return data;`
85			`}`
86
87			`/* Register read and write function for a memory area.`
88			`addr is inside the area, if addr & addr_mask == addr_compare`
89			`(used also by peripheral devices like 16450 UART etc.) */`
90	1350	nogj	`void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,`
91			`uint32_t size, unsigned granularity, unsigned mc_dev,`
92	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
93			`void (writefunc)(oraddr_t, uint32_t, void *),`
94			`void *dat)`
95	30	lampret	`{`
96	239	markom	`struct dev_memarea **pptmp;`
97	1350	nogj	`unsigned int size_mask = bit_mask (size);`
98	261	markom	`int found_error = 0;`
99			`addr_compare &= addr_mask;`
100	221	markom
101	1350	nogj	`debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",`
102			`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
103			`granularity);`
104	239	markom	`/* Go to the end of the list. */`
105	261	markom	`for(pptmp = &dev_list; pptmp; pptmp = &(pptmp)->next)`
106			`if ((addr_compare >= (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)`
107			`\|\| (addr_compare + size > (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)) {`
108	262	markom	`if (!found_error) {`
109	261	markom	`fprintf (stderr, "ERROR: Overlapping memory area(s):\n");`
110	1350	nogj	`fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
111			`", size %08"PRIx32", gran %iB\n",`
112	1308	phoenix	`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
113			`granularity);`
114	262	markom	`}`
115	261	markom	`found_error = 1;`
116	1350	nogj	`fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
117			`", size %08"PRIx32", gran %iB\n",`
118	1308	phoenix	`(pptmp)->addr_mask, (pptmp)->addr_compare,`
119			`(pptmp)->addr_compare \| (pptmp)->size_mask,`
120			`(pptmp)->size, (pptmp)->granularity);`
121	261	markom	`}`
122
123			`if (found_error)`
124			`exit (-1);`
125	537	markom
126	239	markom	`cur_area = pptmp = (struct dev_memarea )malloc(sizeof(struct dev_memarea));`
127	970	simons
128			`if (mc_dev)`
129			`mc_area = *pptmp;`
130
131	261	markom	`(*pptmp)->addr_mask = addr_mask;`
132			`(*pptmp)->addr_compare = addr_compare;`
133	239	markom	`(*pptmp)->size = size;`
134	261	markom	`(*pptmp)->size_mask = size_mask;`
135	239	markom	`(*pptmp)->granularity = granularity;`
136			`(*pptmp)->readfunc = readfunc;`
137			`(*pptmp)->writefunc = writefunc;`
138	479	markom	`(*pptmp)->log = 0;`
139	882	simons	`(*pptmp)->delayr = 2;`
140			`(*pptmp)->delayw = 2;`
141	1359	nogj	`(*pptmp)->priv_dat = dat;`
142	1362	nogj	`(*pptmp)->chip_select = -1;`
143	239	markom	`(*pptmp)->next = NULL;`
144	261	markom	`}`
145	221	markom
146	261	markom	`/* Register read and write function for a memory area.`
147			`Memory areas should be aligned. Memory area is rounded up to`
148			`fit the nearest 2^n aligment.`
149	970	simons	`(used also by peripheral devices like 16450 UART etc.)`
150			`If mc_dev is 1, this means that this device will be checked first for match`
151	1359	nogj	`and will be accessed in case of overlaping memory spaces.`
152	970	simons	`Only one device can have this set to 1 (used for memory controller) */`
153	1350	nogj	`void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,`
154			`unsigned mc_dev,`
155	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
156			`void (writefunc)(oraddr_t, uint32_t, void *),`
157			`void *dat)`
158	261	markom	`{`
159	1350	nogj	`unsigned int size_mask = bit_mask (size);`
160			`unsigned int addr_mask = ~size_mask;`
161	261	markom	`register_memoryarea_mask (addr_mask, addr & addr_mask,`
162	970	simons	`size_mask + 1, granularity, mc_dev,`
163	1359	nogj	`readfunc, writefunc, dat);`
164	30	lampret	`}`
165
166	261	markom
167	30	lampret	`/* Check if access is to registered area of memory. */`
168	1350	nogj	`inline struct dev_memarea *verify_memoryarea(oraddr_t addr)`
169	30	lampret	`{`
170	239	markom	`struct dev_memarea *ptmp;`
171	221	markom
172	970	simons	`/* Check memory controller space first */`
173			`if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))`
174			`return cur_area = mc_area;`
175
176			`/* Check cached value */`
177	560	markom	`if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))`
178			`return cur_area;`
179
180			`/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */`
181	1375	nogj	`/* Check list of registered devices. */`
182			`for(ptmp = dev_list; ptmp; ptmp = ptmp->next)`
183			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)`
184			`return cur_area = ptmp;`
185	239	markom	`return cur_area = NULL;`
186	30	lampret	`}`
187
188	882	simons	`/* Finds the memory area for the address and adjust the read and write delays for it. */`
189	1350	nogj	`void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)`
190	882	simons	`{`
191			`if (verify_memoryarea(memaddr)) {`
192			`cur_area->delayr = delayr;`
193			`cur_area->delayw = delayw;`
194			`}`
195			`}`
196
197	1319	phoenix	`/* for cpu accesses`
198			`*`
199			`* STATISTICS: check cpu/common/parse.c`
200			`*/`
201	1350	nogj	`inline uint32_t evalsim_mem32(oraddr_t memaddr)`
202	560	markom	`{`
203	1319	phoenix	`return(evalsim_mem32_atomic(memaddr, 1));`
204			`}`
205	560	markom
206	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
207	1350	nogj	`inline uint32_t evalsim_mem32_void(oraddr_t memaddr)`
208	1319	phoenix	`{`
209			`return(evalsim_mem32_atomic(memaddr, 0));`
210			`}`
211
212	1350	nogj	`uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)`
213	1319	phoenix	`{`
214	1350	nogj	`uint32_t temp = 0;`
215	1319	phoenix
216	560	markom	`if (verify_memoryarea(memaddr)) {`
217			`switch(cur_area->granularity) {`
218			`case 4:`
219	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
220	560	markom	`break;`
221			`case 1:`
222	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;`
223			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;`
224			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;`
225			`temp \|= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);`
226	560	markom	`break;`
227			`case 2:`
228	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;`
229			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);`
230	560	markom	`break;`
231	1319	phoenix	`default:`
232			`/* if you add new memory granularity be sure to check the formula`
233			`* below for the read delay and fix it if necessery`
234			`*/`
235			`PRINTF("unknown/unhandled memory granularuty\n");`
236			`exit(-1);`
237	560	markom	`}`
238	1319	phoenix	`if (cpu_access)`
239			`runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);`
240	560	markom	`}`
241			`return temp;`
242			`}`
243
244	1319	phoenix	`/* for cpu accesses */`
245	1350	nogj	`inline uint16_t evalsim_mem16(oraddr_t memaddr)`
246	560	markom	`{`
247	1319	phoenix	`return(evalsim_mem16_atomic(memaddr, 1));`
248			`}`
249	560	markom
250	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
251	1350	nogj	`inline uint16_t evalsim_mem16_void(oraddr_t memaddr)`
252	1319	phoenix	`{`
253			`return(evalsim_mem16_atomic(memaddr, 0));`
254			`}`
255
256	1350	nogj	`uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)`
257	1319	phoenix	`{`
258	1350	nogj	`uint32_t temp = 0;`
259	1319	phoenix
260	560	markom	`if (verify_memoryarea(memaddr)) {`
261			`switch(cur_area->granularity) {`
262			`case 1:`
263	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;`
264			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);`
265	1319	phoenix	`if (cpu_access)`
266			`runtime.sim.mem_cycles += cur_area->delayr * 2;`
267	560	markom	`break;`
268			`case 2:`
269	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
270	1319	phoenix	`if (cpu_access)`
271			`runtime.sim.mem_cycles += cur_area->delayr;`
272	560	markom	`break;`
273			`case 4:`
274	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);`
275	560	markom	`if (memaddr & 2)`
276			`temp &= 0xffff;`
277			`else`
278			`temp >>= 16;`
279			`break;`
280	1319	phoenix	`default:`
281			`/* if you add new memory granularity be sure to check the formula`
282			`* below for the read delay and fix it if necessery`
283			`*/`
284			`PRINTF("unknown/unhandled memory granularuty\n");`
285			`exit(-1);`
286	560	markom	`}`
287			`}`
288			`return temp;`
289			`}`
290
291	1319	phoenix	`/* for cpu accesses */`
292	1350	nogj	`inline uint8_t evalsim_mem8(oraddr_t memaddr)`
293	560	markom	`{`
294	1319	phoenix	`return(evalsim_mem8_atomic(memaddr, 1));`
295			`}`
296	560	markom
297	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
298	1350	nogj	`inline uint8_t evalsim_mem8_void(oraddr_t memaddr)`
299	1319	phoenix	`{`
300			`return(evalsim_mem8_atomic(memaddr, 0));`
301			`}`
302
303	1350	nogj	`uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)`
304	1319	phoenix	`{`
305	1350	nogj	`uint32_t temp = 0;`
306	1319	phoenix
307	560	markom	`if (verify_memoryarea(memaddr)) {`
308			`switch(cur_area->granularity) {`
309			`case 1:`
310	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
311	1319	phoenix	`if (cpu_access)`
312			`runtime.sim.mem_cycles += cur_area->delayr;`
313	560	markom	`break;`
314			`case 2:`
315	1350	nogj	`temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);`
316	560	markom	`if (memaddr & 1)`
317			`temp &= 0xff;`
318			`else`
319			`temp >>= 8;`
320			`break;`
321			`case 4:`
322	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);`
323	560	markom	`temp >>= 8 * (3 - (memaddr & 3));`
324			`temp &= 0xff;`
325			`break;`
326	1319	phoenix	`default:`
327			`/* if you add new memory granularity be sure to check the formula`
328			`* below for the read delay and fix it if necessery`
329			`*/`
330			`PRINTF("unknown/unhandled memory granularuty\n");`
331			`exit(-1);`
332	560	markom	`}`
333			`}`
334			`return temp;`
335			`}`
336
337	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
338			`*`
339			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
340			`*/`
341	1350	nogj	`uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)`
342	2	cvs	`{`
343	1350	nogj	`uint32_t temp;`
344	123	markom
345	547	markom	`if (config.sim.mprofile)`
346			`mprofile (memaddr, MPROF_32 \| MPROF_READ);`
347
348	538	markom	`if (memaddr & 3) {`
349			`except_handle (EXCEPT_ALIGN, memaddr);`
350			`return 0;`
351			`}`
352	557	markom
353	631	simons	`if (config.debug.enabled)`
354			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
355
356	574	markom	`cur_vadd = memaddr;`
357	631	simons
358			`memaddr = dmmu_translate(memaddr, 0);`
359	1386	nogj	`if (except_pending)`
360	574	markom	`return 0;`
361
362	992	simons	`if (config.dc.enabled)`
363			`temp = dc_simulate_read(memaddr, 4);`
364			`else {`
365			`temp = evalsim_mem32(memaddr);`
366			`if (!cur_area) {`
367	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
368			`memaddr);`
369	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
370			`temp = 0;`
371			`}`
372	611	simons	`}`
373
374	550	markom	`if (config.debug.enabled)`
375	270	markom	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
376	239	markom	`return temp;`
377	66	lampret	`}`
378
379	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do`
380			`*`
381			`* STATISTICS OK`
382			`*/`
383	1350	nogj	`uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,`
384			`int through_dc)`
385	1240	phoenix	`{`
386	1350	nogj	`uint32_t temp;`
387	1240	phoenix
388			`if (memaddr & 3) {`
389			`PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);`
390			`return 0;`
391			`}`
392
393			`cur_vadd = memaddr;`
394
395			`if (through_mmu)`
396			`memaddr = peek_into_dtlb(memaddr, 0, through_dc);`
397
398			`if (through_dc)`
399			`temp = dc_simulate_read(memaddr, 4);`
400			`else {`
401	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
402	1240	phoenix	`if (!cur_area) {`
403	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR`
404			`") in eval_direct32()\n", memaddr);`
405	1240	phoenix	`except_handle(EXCEPT_BUSERR, cur_vadd);`
406			`temp = 0;`
407			`}`
408			`}`
409
410			`return temp;`
411			`}`
412
413
414	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
415			`*`
416			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
417			`*/`
418	1386	nogj	`uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)`
419	349	simons	`{`
420	1350	nogj	`uint32_t temp;`
421	349	simons
422	547	markom	`if (config.sim.mprofile)`
423			`mprofile (memaddr, MPROF_32 \| MPROF_FETCH);`
424	532	markom	`// memaddr = simulate_ic_mmu_fetch(memaddr);`
425	1244	hpanther
426	1386	nogj	`cur_vadd = memaddr;`
427	1244	hpanther
428	1452	nogj	`#if !(DYNAMIC_EXECUTION)`
429	1386	nogj	`memaddr = immu_translate(memaddr);`
430
431			`if (except_pending)`
432			`return 0;`
433	1452	nogj	`#endif`
434	1386	nogj
435			`if (config.debug.enabled)`
436			`*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);`
437
438	631	simons	`if (config.ic.enabled)`
439			`temp = ic_simulate_fetch(memaddr);`
440	992	simons	`else {`
441	631	simons	`temp = evalsim_mem32(memaddr);`
442	992	simons	`if (!cur_area) {`
443	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
444			`memaddr);`
445	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
446			`temp = 0;`
447			`}`
448	611	simons	`}`
449
450	1386	nogj	`if (config.debug.enabled)`
451			`*breakpoint += CheckDebugUnit(DebugLoadData,temp);`
452	349	simons	`return temp;`
453			`}`
454
455	1452	nogj	`/* Returns 32-bit values from mem array. Big endian version.`
456			`*`
457			`* STATISTICS OK`
458			`*/`
459			`uint32_t eval_insn_direct(oraddr_t memaddr, int* breakpoint, int through_mmu)`
460			`{`
461			`uint32_t temp;`
462			`int brk;`
463
464			`cur_vadd = memaddr;`
465
466			`if(through_mmu)`
467			`memaddr = peek_into_itlb(memaddr);`
468
469			`if (config.debug.enabled)`
470			`*breakpoint += CheckDebugUnit(DebugLoadAddress, memaddr);`
471
472			`temp = eval_direct32(memaddr, &brk, 0, 0);`
473
474			`if (config.debug.enabled)`
475			`*breakpoint += CheckDebugUnit(DebugLoadData, temp);`
476
477			`return temp;`
478			`}`
479
480
481	1319	phoenix	`/* Returns 16-bit values from mem array. Big endian version.`
482			`*`
483			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
484			`*/`
485	1350	nogj	`uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)`
486	2	cvs	`{`
487	1350	nogj	`uint16_t temp;`
488	547	markom
489			`if (config.sim.mprofile)`
490			`mprofile (memaddr, MPROF_16 \| MPROF_READ);`
491
492	538	markom	`if (memaddr & 1) {`
493			`except_handle (EXCEPT_ALIGN, memaddr);`
494			`return 0;`
495			`}`
496	574	markom
497	631	simons	`if (config.debug.enabled)`
498			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
499
500	574	markom	`cur_vadd = memaddr;`

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[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 1484