URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [peripheral/] [atahost.c] - Blame information for rev 1713

Go to most recent revision | Details | Compare with Previous | View Log


/*
    atahost.c -- ATA Host code simulation
    Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
 
    This file is part of OpenRISC 1000 Architectural Simulator
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
 
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
/* get a prototype for 'reg_mem_area()', and 'adjust_rw_delay()' */
#include "abstract.h"
#include "sim-config.h"
#include "sched.h"
#include "debug.h"
 
#include "atahost.h"
 
/* default timing reset values */
#define PIO_MODE0_T1 6
#define PIO_MODE0_T2 28
#define PIO_MODE0_T4 2
#define PIO_MODE0_TEOC 23
 
#define DMA_MODE0_TM 4
#define DMA_MODE0_TD 21
#define DMA_MODE0_TEOC 21
 
DEFAULT_DEBUG_CHANNEL(ata);
 
/* reset and initialize ATA host core(s) */
static void ata_reset(void *dat)
{
   ata_host *ata = dat;
 
   // reset the core registers
   ata->regs.ctrl  = 0x0001;
   ata->regs.stat  = (ata->dev_id << 28) | (ata->rev << 24);
   ata->regs.pctr  = (ata->pio_mode0_teoc << ATA_TEOC) |
                     (ata->pio_mode0_t4 << ATA_T4) |
                     (ata->pio_mode0_t2 << ATA_T2) |
                     (ata->pio_mode0_t1 << ATA_T1);
   ata->regs.pftr0 = ata->regs.pctr;
   ata->regs.pftr1 = ata->regs.pctr;
   ata->regs.dtr0  = (ata->dma_mode0_teoc << ATA_TEOC) |
                     (ata->dma_mode0_td << ATA_TD) |
                     (ata->dma_mode0_tm << ATA_TM);
   ata->regs.dtr1  = ata->regs.dtr0;
   ata->regs.txb   = 0;
 
   // inform simulator about new read/write delay timings
   adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
 
   /* the reset bit in the control register 'ctrl' is set, reset connect ata-devices */
   ata_devices_hw_reset(&ata->devices, 1);
}
/* ========================================================================= */
 
 
/*
  Read a register
*/
static uint32_t ata_read32( oraddr_t addr, void *dat )
{
    ata_host *ata = dat;
 
    /* determine if ata_host or ata_device addressed */
    if (is_ata_hostadr(addr))
    {
        // Accesses to internal register take 2cycles
        adjust_rw_delay( ata->mem, 2, 2 );
 
        switch( addr ) {
            case ATA_CTRL :
                TRACE("Read control register: %"PRIx32"\n", ata->regs.ctrl);
                return ata -> regs.ctrl;
 
            case ATA_STAT :
                return ata -> regs.stat;
 
            case ATA_PCTR :
                return ata -> regs.pctr;
 
            case ATA_PFTR0:
                return ata->dev_id > 1 ? ata->regs.pftr0 : 0;
 
            case ATA_PFTR1:
                return ata->dev_id > 1 ? ata->regs.pftr1 : 0;
 
            case ATA_DTR0 :
                return ata->dev_id > 2 ? ata->regs.dtr0 : 0;
 
            case ATA_DTR1 :
                return ata->dev_id > 2 ? ata->regs.dtr1 : 0;
 
            case ATA_RXB  :
                return ata->dev_id > 2 ? ata->regs.rxb : 0;
 
            default:
                return 0;
        }
    }
 
    /* check if the controller is enabled */
    if(ata->regs.ctrl & ATA_IDE_EN) {
        // make sure simulator uses correct read/write delay timings
        if(((addr & 0x7f) == ATA_DR) && ata->dev_id > 1) {
          if(ata->dev_sel)
              adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr1), ata_pio_delay(ata->regs.pftr1));
          else
              adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr0), ata_pio_delay(ata->regs.pftr0));
        }
        else
          adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr));
 
        return ata_devices_read(&ata->devices, addr & 0x7f);
    }
    return 0;
}
/* ========================================================================= */
 
 
/*
  Write a register
*/
static void ata_write32( oraddr_t addr, uint32_t value, void *dat )
{
    ata_host *ata = dat;
 
    /* determine if ata_host or ata_device addressed */
    if (is_ata_hostadr(addr))
    {
       // Accesses to internal register take 2cycles
       adjust_rw_delay( ata->mem, 2, 2 );
 
        switch( addr ) {
            case ATA_CTRL :
                TRACE("Writting control register: %"PRIx32"\n", value);
                ata -> regs.ctrl =  value;
 
                /* check if reset bit set, if so reset ata-devices    */
                if (value & ATA_RST)
                  ata_devices_hw_reset(&ata->devices, 1);
                else
                  ata_devices_hw_reset(&ata->devices, 0);
                break;
 
            case ATA_STAT :
                ata -> regs.stat = (ata -> regs.stat & ~ATA_IDEIS) | (ata -> regs.stat & ATA_IDEIS & value);
                break;
 
            case ATA_PCTR :
                TRACE("PCTR: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
                      value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
                      value & 0xff);
                ata -> regs.pctr = value;
                break;
 
            case ATA_PFTR0:
                TRACE("PFTR0: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
                      value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
                      value & 0xff);
                ata -> regs.pftr0 = value;
                break;
 
            case ATA_PFTR1:
                TRACE("PFTR1: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
                      value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
                      value & 0xff);
                ata -> regs.pftr1 = value;
                break;
 
            case ATA_DTR0 :
                ata -> regs.dtr0  = value;
                break;
 
            case ATA_DTR1 :
                ata -> regs.dtr1  = value;
                break;
 
            case ATA_TXB  :
                ata -> regs.txb   = value;
                break;
 
            default:
                /* ERROR-macro currently only supports simple strings. */
                /*
                  fprintf(stderr, "ERROR  : Unknown register for OCIDEC(%1d).\n", DEV_ID );
 
                  Tried to show some useful info here.
                  But when using 'DM'-simulator-command, the screen gets filled with these messages.
                  Thereby eradicating the usefulness of the message
                */
                break;
        }
        return;
    }
 
    /* check if the controller is enabled */
    if(ata->regs.ctrl & ATA_IDE_EN) {
        // make sure simulator uses correct read/write delay timings
        if(((addr & 0x7f) == ATA_DR) && (ata->dev_id > 1)) {
          if(ata->dev_sel)
            adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr1), ata_pio_delay(ata->regs.pftr1));
          else
            adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr0), ata_pio_delay(ata->regs.pftr0));
        } else
          adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
 
        if((addr & 0x7f) == ATA_DHR)
          ata->dev_sel = value & ATA_DHR_DEV;
 
        ata_devices_write(&ata->devices, addr & 0x7f, value);
    }
}
/* ========================================================================= */
 
 
/* Dump status */
static void ata_status( void *dat )
{
  ata_host *ata = dat;
 
  if ( ata->baseaddr == 0 )
    return;
 
  PRINTF( "\nOCIDEC-%1d at: 0x%"PRIxADDR"\n", ata->dev_id, ata->baseaddr );
  PRINTF( "ATA CTRL     : 0x%08X\n", ata->regs.ctrl  );
  PRINTF( "ATA STAT     : 0x%08x\n", ata->regs.stat  );
  PRINTF( "ATA PCTR     : 0x%08x\n", ata->regs.pctr  );
 
  if(ata->dev_id > 1) {
    PRINTF( "ATA FCTR0    : 0x%08x\n", ata->regs.pftr0 );
    PRINTF( "ATA FCTR1    : 0x%08x\n", ata->regs.pftr1 );
  }
 
  if(ata->dev_id > 2) {
    PRINTF( "ATA DTR0     : 0x%08x\n", ata->regs.dtr0  );
    PRINTF( "ATA DTR1     : 0x%08x\n", ata->regs.dtr1  );
    PRINTF( "ATA TXD      : 0x%08x\n", ata->regs.txb   );
    PRINTF( "ATA RXD      : 0x%08x\n", ata->regs.rxb   );
  }
}
/* ========================================================================= */
 
/*----------------------------------------------------[ ATA Configuration ]---*/
static unsigned int conf_dev;
 
static void ata_baseaddr(union param_val val, void *dat)
{
  ata_host *ata = dat;
  ata->baseaddr = val.addr_val;
}
 
static void ata_irq(union param_val val, void *dat)
{
  ata_host *ata = dat;
  ata->irq = val.int_val;
}
 
static void ata_dev_id(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(val.int_val < 1 || val.int_val > 3) {
    fprintf(stderr, "Peripheral ATA: Unknown device id %d, useing 1\n",
            val.int_val);
    ata->dev_id = 1;
    return;
  }
 
  ata->dev_id = val.int_val;
}
 
static void ata_rev(union param_val val, void *dat)
{
  ata_host *ata = dat;
  ata->rev = val.int_val;
}
 
static void ata_pio_mode0_t1(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t1: %d\n", val.int_val);
    return;
  }
 
  ata->pio_mode0_t1 = val.int_val;
}
 
static void ata_pio_mode0_t2(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t2: %d\n", val.int_val);
    return;
  }
 
  ata->pio_mode0_t2 = val.int_val;
}
 
static void ata_pio_mode0_t4(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t4: %d\n", val.int_val);
    return;
  }
 
  ata->pio_mode0_t4 = val.int_val;
}
 
static void ata_pio_mode0_teoc(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_teoc: %d\n", val.int_val);
    return;
  }
 
  ata->pio_mode0_teoc = val.int_val;
}
 
static void ata_dma_mode0_tm(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_tm: %d\n", val.int_val);
    return;
  }
 
  ata->dma_mode0_tm = val.int_val;
}
 
static void ata_dma_mode0_td(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_td: %d\n", val.int_val);
    return;
  }
 
  ata->dma_mode0_td = val.int_val;
}
 
static void ata_dma_mode0_teoc(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_teoc: %d\n", val.int_val);
    return;
  }
 
  ata->dma_mode0_teoc = val.int_val;
}
 
static void ata_type(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.type = val.int_val;
}
 
static void ata_file(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(conf_dev <= 1)
    if(!(ata->devices.device[conf_dev].conf.file = strdup(val.str_val))) {
      fprintf(stderr, "Peripheral ATA: Run out of memory\n");
      exit(-1);
    }
}
 
static void ata_size(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.size = val.int_val << 20;
}
 
static void ata_packet(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.packet = val.int_val;
}
 
static void ata_enabled(union param_val val, void *dat)
{
  ata_host *ata = dat;
  ata->enabled = val.int_val;
}
 
static void ata_heads(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.heads = val.int_val;
}
 
static void ata_sectors(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.sectors = val.int_val;
}
 
static void ata_firmware(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    if(!(ata->devices.device[conf_dev].conf.firmware = strdup(val.str_val))) {
      fprintf(stderr, "Peripheral ATA: Run out of memory\n");
      exit(-1);
    }
}
 
static void ata_mwdma(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.mwdma = val.int_val;
}
 
static void ata_pio(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.pio = val.int_val;
}
 
 
static void ata_start_device(union param_val val, void *dat)
{
  conf_dev = val.int_val;
 
  if(conf_dev > 1)
    fprintf(stderr, "Device %d out-of-range\n", conf_dev);
}
 
static void ata_enddevice(union param_val val, void *dat)
{
  conf_dev = 2;
}
 
static void *ata_sec_start(void)
{
  ata_host *new = malloc(sizeof(ata_host));
 
  if(!new) {
    fprintf(stderr, "Peripheral ATA: Run out of memory\n");
    exit(-1);
  }
 
  memset(new, 0, sizeof(ata_host));
  new->enabled = 1;
  new->dev_id = 1;
 
  new->pio_mode0_t1 = PIO_MODE0_T1;
  new->pio_mode0_t2 = PIO_MODE0_T2;
  new->pio_mode0_t4 = PIO_MODE0_T4;
  new->pio_mode0_teoc = PIO_MODE0_TEOC;
 
  new->dma_mode0_tm = DMA_MODE0_TM;
  new->dma_mode0_td = DMA_MODE0_TD;
  new->dma_mode0_teoc = DMA_MODE0_TEOC;
 
  new->devices.device[0].conf.heads = 7;
  new->devices.device[0].conf.sectors = 32;
  new->devices.device[0].conf.firmware = "02207031";
  new->devices.device[0].conf.mwdma = 2;
  new->devices.device[0].conf.pio = 4;
 
  new->devices.device[1].conf.heads = 7;
  new->devices.device[1].conf.sectors = 32;
  new->devices.device[1].conf.firmware = "02207031";
  new->devices.device[1].conf.mwdma = 2;
  new->devices.device[1].conf.pio = 4;
 
  return new;
}
 
static void ata_sec_end(void *dat)
{
  ata_host *ata = dat;
  struct mem_ops ops;
 
  if(!ata->enabled) {
    free(dat);
    return;
  }
 
  /* Connect ata_devices.                                            */
  ata_devices_init(&ata->devices);
 
  memset(&ops, 0, sizeof(struct mem_ops));
 
  ops.readfunc32 = ata_read32;
  ops.read_dat32 = dat;
  ops.writefunc32 = ata_write32;
  ops.write_dat32 = dat;
 
  /* Delays will be readjusted later */
  ops.delayr = 2;
  ops.delayw = 2;
 
  ata->mem = reg_mem_area(ata->baseaddr, ATA_ADDR_SPACE, 0, &ops);
 
  reg_sim_reset(ata_reset, dat);
  reg_sim_stat(ata_status, dat);
}
 
void reg_ata_sec(void)
{
  struct config_section *sec = reg_config_sec("ata", ata_sec_start, ata_sec_end);
 
  reg_config_param(sec, "enabled", paramt_int, ata_enabled);
  reg_config_param(sec, "baseaddr", paramt_addr, ata_baseaddr);
  reg_config_param(sec, "irq", paramt_int, ata_irq);
  reg_config_param(sec, "dev_id", paramt_int, ata_dev_id);
  reg_config_param(sec, "rev", paramt_int, ata_rev);
 
  reg_config_param(sec, "pio_mode0_t1", paramt_int, ata_pio_mode0_t1);
  reg_config_param(sec, "pio_mode0_t2", paramt_int, ata_pio_mode0_t2);
  reg_config_param(sec, "pio_mode0_t4", paramt_int, ata_pio_mode0_t4);
  reg_config_param(sec, "pio_mode0_teoc", paramt_int, ata_pio_mode0_teoc);
 
  reg_config_param(sec, "dma_mode0_tm", paramt_int, ata_dma_mode0_tm);
  reg_config_param(sec, "dma_mode0_td", paramt_int, ata_dma_mode0_td);
  reg_config_param(sec, "dma_mode0_teoc", paramt_int, ata_dma_mode0_teoc);
 
  reg_config_param(sec, "device", paramt_int, ata_start_device);
  reg_config_param(sec, "enddevice", paramt_int, ata_enddevice);
 
  reg_config_param(sec, "type", paramt_int, ata_type);
  reg_config_param(sec, "file", paramt_str, ata_file);
  reg_config_param(sec, "size", paramt_int, ata_size);
  reg_config_param(sec, "packet", paramt_int, ata_packet);
  reg_config_param(sec, "heads", paramt_int, ata_heads);
  reg_config_param(sec, "sectors", paramt_int, ata_sectors);
  reg_config_param(sec, "firmware", paramt_int, ata_firmware);
  reg_config_param(sec, "mwdma", paramt_int, ata_mwdma);
  reg_config_param(sec, "pio", paramt_int, ata_pio);
}

Line No.	Rev	Author	Line
1	876	rherveille	`/*`
2			`atahost.c -- ATA Host code simulation`
3			`Copyright (C) 2002 Richard Herveille, rherveille@opencores.org`
4
5			`This file is part of OpenRISC 1000 Architectural Simulator`
6
7			`This program is free software; you can redistribute it and/or modify`
8			`it under the terms of the GNU General Public License as published by`
9			`the Free Software Foundation; either version 2 of the License, or`
10			`(at your option) any later version`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.`
20			`*/`
21
22	1364	nogj	`#include <string.h>`
23
24	1350	nogj	`#include "config.h"`
25
26			`#ifdef HAVE_INTTYPES_H`
27			`#include <inttypes.h>`
28			`#endif`
29
30			`#include "port.h"`
31			`#include "arch.h"`
32	1486	nogj	`/* get a prototype for 'reg_mem_area()', and 'adjust_rw_delay()' */`
33	876	rherveille	`#include "abstract.h"`
34			`#include "sim-config.h"`
35			`#include "sched.h"`
36	1713	nogj	`#include "debug.h"`
37	876	rherveille
38			`#include "atahost.h"`
39
40	1702	nogj	`/* default timing reset values */`
41			`#define PIO_MODE0_T1 6`
42			`#define PIO_MODE0_T2 28`
43			`#define PIO_MODE0_T4 2`
44			`#define PIO_MODE0_TEOC 23`
45
46			`#define DMA_MODE0_TM 4`
47			`#define DMA_MODE0_TD 21`
48			`#define DMA_MODE0_TEOC 21`
49
50	1713	nogj	`DEFAULT_DEBUG_CHANNEL(ata);`
51
52	876	rherveille	`/* reset and initialize ATA host core(s) */`
53	1649	nogj	`static void ata_reset(void *dat)`
54	876	rherveille	`{`
55	1364	nogj	`ata_host *ata = dat;`
56	876	rherveille
57	1364	nogj	`// reset the core registers`
58			`ata->regs.ctrl = 0x0001;`
59	1701	nogj	`ata->regs.stat = (ata->dev_id << 28) \| (ata->rev << 24);`
60	1702	nogj	`ata->regs.pctr = (ata->pio_mode0_teoc << ATA_TEOC) \|`
61			`(ata->pio_mode0_t4 << ATA_T4) \|`
62			`(ata->pio_mode0_t2 << ATA_T2) \|`
63			`(ata->pio_mode0_t1 << ATA_T1);`
64			`ata->regs.pftr0 = ata->regs.pctr;`
65			`ata->regs.pftr1 = ata->regs.pctr;`
66			`ata->regs.dtr0 = (ata->dma_mode0_teoc << ATA_TEOC) \|`
67			`(ata->dma_mode0_td << ATA_TD) \|`
68			`(ata->dma_mode0_tm << ATA_TM);`
69			`ata->regs.dtr1 = ata->regs.dtr0;`
70	1364	nogj	`ata->regs.txb = 0;`
71	919	rherveille
72	1364	nogj	`// inform simulator about new read/write delay timings`
73	1486	nogj	`adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );`
74	876	rherveille
75	1364	nogj	`/* the reset bit in the control register 'ctrl' is set, reset connect ata-devices */`
76			`ata_devices_hw_reset(&ata->devices, 1);`
77	876	rherveille	`}`
78			`/* ========================================================================= */`
79
80
81			`/*`
82			`Read a register`
83			`*/`
84	1649	nogj	`static uint32_t ata_read32( oraddr_t addr, void *dat )`
85	876	rherveille	`{`
86	1364	nogj	`ata_host *ata = dat;`
87	876	rherveille
88			`/* determine if ata_host or ata_device addressed */`
89			`if (is_ata_hostadr(addr))`
90	919	rherveille	`{`
91			`// Accesses to internal register take 2cycles`
92	1486	nogj	`adjust_rw_delay( ata->mem, 2, 2 );`
93	919	rherveille
94	876	rherveille	`switch( addr ) {`
95			`case ATA_CTRL :`
96	1713	nogj	`TRACE("Read control register: %"PRIx32"\n", ata->regs.ctrl);`
97	876	rherveille	`return ata -> regs.ctrl;`
98
99			`case ATA_STAT :`
100			`return ata -> regs.stat;`
101
102			`case ATA_PCTR :`
103			`return ata -> regs.pctr;`
104
105			`case ATA_PFTR0:`
106	1701	nogj	`return ata->dev_id > 1 ? ata->regs.pftr0 : 0;`
107	876	rherveille
108			`case ATA_PFTR1:`
109	1701	nogj	`return ata->dev_id > 1 ? ata->regs.pftr1 : 0;`
110	876	rherveille
111			`case ATA_DTR0 :`
112	1701	nogj	`return ata->dev_id > 2 ? ata->regs.dtr0 : 0;`
113	876	rherveille
114			`case ATA_DTR1 :`
115	1701	nogj	`return ata->dev_id > 2 ? ata->regs.dtr1 : 0;`
116	876	rherveille
117			`case ATA_RXB :`
118	1701	nogj	`return ata->dev_id > 2 ? ata->regs.rxb : 0;`
119	876	rherveille
120			`default:`
121			`return 0;`
122	919	rherveille	`}`
123	876	rherveille	`}`
124	1701	nogj
125	1019	rherveille	`/* check if the controller is enabled */`
126	1701	nogj	`if(ata->regs.ctrl & ATA_IDE_EN) {`
127	919	rherveille	`// make sure simulator uses correct read/write delay timings`
128	1701	nogj	`if(((addr & 0x7f) == ATA_DR) && ata->dev_id > 1) {`
129			`if(ata->dev_sel)`
130			`adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr1), ata_pio_delay(ata->regs.pftr1));`
131	919	rherveille	`else`
132	1701	nogj	`adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr0), ata_pio_delay(ata->regs.pftr0));`
133	919	rherveille	`}`
134			`else`
135	1701	nogj	`adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr));`
136	919	rherveille
137			`return ata_devices_read(&ata->devices, addr & 0x7f);`
138			`}`
139	1557	nogj	`return 0;`
140	876	rherveille	`}`
141			`/* ========================================================================= */`
142
143
144			`/*`
145			`Write a register`
146			`*/`
147	1649	nogj	`static void ata_write32( oraddr_t addr, uint32_t value, void *dat )`
148	876	rherveille	`{`
149	1364	nogj	`ata_host *ata = dat;`
150	876	rherveille
151			`/* determine if ata_host or ata_device addressed */`
152			`if (is_ata_hostadr(addr))`
153	919	rherveille	`{`
154			`// Accesses to internal register take 2cycles`
155	1486	nogj	`adjust_rw_delay( ata->mem, 2, 2 );`
156	919	rherveille
157	876	rherveille	`switch( addr ) {`
158			`case ATA_CTRL :`
159	1713	nogj	`TRACE("Writting control register: %"PRIx32"\n", value);`
160	876	rherveille	`ata -> regs.ctrl = value;`
161
162			`/* check if reset bit set, if so reset ata-devices */`
163			`if (value & ATA_RST)`
164			`ata_devices_hw_reset(&ata->devices, 1);`
165			`else`
166			`ata_devices_hw_reset(&ata->devices, 0);`
167			`break;`
168
169			`case ATA_STAT :`
170			`ata -> regs.stat = (ata -> regs.stat & ~ATA_IDEIS) \| (ata -> regs.stat & ATA_IDEIS & value);`
171			`break;`
172
173			`case ATA_PCTR :`
174	1713	nogj	`TRACE("PCTR: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",`
175			`value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,`
176			`value & 0xff);`
177	876	rherveille	`ata -> regs.pctr = value;`
178			`break;`
179
180			`case ATA_PFTR0:`
181	1713	nogj	`TRACE("PFTR0: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",`
182			`value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,`
183			`value & 0xff);`
184	876	rherveille	`ata -> regs.pftr0 = value;`
185			`break;`
186
187			`case ATA_PFTR1:`
188	1713	nogj	`TRACE("PFTR1: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",`
189			`value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,`
190			`value & 0xff);`
191	876	rherveille	`ata -> regs.pftr1 = value;`
192			`break;`
193
194			`case ATA_DTR0 :`
195			`ata -> regs.dtr0 = value;`
196			`break;`
197
198			`case ATA_DTR1 :`
199			`ata -> regs.dtr1 = value;`
200			`break;`
201
202			`case ATA_TXB :`
203			`ata -> regs.txb = value;`
204			`break;`
205
206			`default:`
207			`/* ERROR-macro currently only supports simple strings. */`
208			`/*`
209			`fprintf(stderr, "ERROR : Unknown register for OCIDEC(%1d).\n", DEV_ID );`
210
211			`Tried to show some useful info here.`
212			`But when using 'DM'-simulator-command, the screen gets filled with these messages.`
213			`Thereby eradicating the usefulness of the message`
214			`*/`
215			`break;`
216			`}`
217	1701	nogj	`return;`
218	919	rherveille	`}`
219	1701	nogj
220	1019	rherveille	`/* check if the controller is enabled */`
221	1701	nogj	`if(ata->regs.ctrl & ATA_IDE_EN) {`
222	919	rherveille	`// make sure simulator uses correct read/write delay timings`
223	1701	nogj	`if(((addr & 0x7f) == ATA_DR) && (ata->dev_id > 1)) {`
224			`if(ata->dev_sel)`
225			`adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr1), ata_pio_delay(ata->regs.pftr1));`
226	919	rherveille	`else`
227	1701	nogj	`adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr0), ata_pio_delay(ata->regs.pftr0));`
228			`} else`
229			`adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );`
230	919	rherveille
231	1701	nogj	`if((addr & 0x7f) == ATA_DHR)`
232			`ata->dev_sel = value & ATA_DHR_DEV;`
233
234	876	rherveille	`ata_devices_write(&ata->devices, addr & 0x7f, value);`
235	919	rherveille	`}`
236	876	rherveille	`}`
237			`/* ========================================================================= */`
238
239
240			`/* Dump status */`
241	1649	nogj	`static void ata_status( void *dat )`
242	876	rherveille	`{`
243	1364	nogj	`ata_host *ata = dat;`
244	876	rherveille
245	1364	nogj	`if ( ata->baseaddr == 0 )`
246			`return;`
247	876	rherveille
248	1701	nogj	`PRINTF( "\nOCIDEC-%1d at: 0x%"PRIxADDR"\n", ata->dev_id, ata->baseaddr );`
249	1364	nogj	`PRINTF( "ATA CTRL : 0x%08X\n", ata->regs.ctrl );`
250			`PRINTF( "ATA STAT : 0x%08x\n", ata->regs.stat );`
251			`PRINTF( "ATA PCTR : 0x%08x\n", ata->regs.pctr );`
252	876	rherveille
253	1701	nogj	`if(ata->dev_id > 1) {`
254			`PRINTF( "ATA FCTR0 : 0x%08x\n", ata->regs.pftr0 );`
255			`PRINTF( "ATA FCTR1 : 0x%08x\n", ata->regs.pftr1 );`
256			`}`
257	876	rherveille
258	1701	nogj	`if(ata->dev_id > 2) {`
259			`PRINTF( "ATA DTR0 : 0x%08x\n", ata->regs.dtr0 );`
260			`PRINTF( "ATA DTR1 : 0x%08x\n", ata->regs.dtr1 );`
261			`PRINTF( "ATA TXD : 0x%08x\n", ata->regs.txb );`
262			`PRINTF( "ATA RXD : 0x%08x\n", ata->regs.rxb );`
263			`}`
264	876	rherveille	`}`
265			`/* ========================================================================= */`
266	1358	nogj
267			`/----------------------------------------------------[ ATA Configuration ]---/`
268	1703	nogj	`static unsigned int conf_dev;`
269
270	1649	nogj	`static void ata_baseaddr(union param_val val, void *dat)`
271	1358	nogj	`{`
272	1364	nogj	`ata_host *ata = dat;`
273			`ata->baseaddr = val.addr_val;`
274	1358	nogj	`}`
275
276	1649	nogj	`static void ata_irq(union param_val val, void *dat)`
277	1358	nogj	`{`
278	1364	nogj	`ata_host *ata = dat;`
279			`ata->irq = val.int_val;`
280	1358	nogj	`}`
281
282	1701	nogj	`static void ata_dev_id(union param_val val, void *dat)`
283			`{`
284			`ata_host *ata = dat;`
285			`if(val.int_val < 1 \|\| val.int_val > 3) {`
286			`fprintf(stderr, "Peripheral ATA: Unknown device id %d, useing 1\n",`
287			`val.int_val);`
288			`ata->dev_id = 1;`
289			`return;`
290			`}`
291
292			`ata->dev_id = val.int_val;`
293			`}`
294
295			`static void ata_rev(union param_val val, void *dat)`
296			`{`
297			`ata_host *ata = dat;`
298			`ata->rev = val.int_val;`
299			`}`
300
301	1702	nogj	`static void ata_pio_mode0_t1(union param_val val, void *dat)`
302			`{`
303			`ata_host *ata = dat;`
304
305			`if(val.int_val < 0 \|\| val.int_val > 255) {`
306			`fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t1: %d\n", val.int_val);`
307			`return;`
308			`}`
309
310			`ata->pio_mode0_t1 = val.int_val;`
311			`}`
312
313			`static void ata_pio_mode0_t2(union param_val val, void *dat)`
314			`{`
315			`ata_host *ata = dat;`
316
317			`if(val.int_val < 0 \|\| val.int_val > 255) {`
318			`fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t2: %d\n", val.int_val);`
319			`return;`
320			`}`
321
322			`ata->pio_mode0_t2 = val.int_val;`
323			`}`
324
325			`static void ata_pio_mode0_t4(union param_val val, void *dat)`
326			`{`
327			`ata_host *ata = dat;`
328
329			`if(val.int_val < 0 \|\| val.int_val > 255) {`
330			`fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t4: %d\n", val.int_val);`
331			`return;`
332			`}`
333
334			`ata->pio_mode0_t4 = val.int_val;`
335			`}`
336
337			`static void ata_pio_mode0_teoc(union param_val val, void *dat)`
338			`{`
339			`ata_host *ata = dat;`
340
341			`if(val.int_val < 0 \|\| val.int_val > 255) {`
342			`fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_teoc: %d\n", val.int_val);`
343			`return;`
344			`}`
345
346			`ata->pio_mode0_teoc = val.int_val;`
347			`}`
348
349			`static void ata_dma_mode0_tm(union param_val val, void *dat)`
350			`{`
351			`ata_host *ata = dat;`
352
353			`if(val.int_val < 0 \|\| val.int_val > 255) {`
354			`fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_tm: %d\n", val.int_val);`
355			`return;`
356			`}`
357
358			`ata->dma_mode0_tm = val.int_val;`
359			`}`
360
361			`static void ata_dma_mode0_td(union param_val val, void *dat)`
362			`{`
363			`ata_host *ata = dat;`
364
365			`if(val.int_val < 0 \|\| val.int_val > 255) {`
366			`fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_td: %d\n", val.int_val);`
367			`return;`
368			`}`
369
370			`ata->dma_mode0_td = val.int_val;`
371			`}`
372
373			`static void ata_dma_mode0_teoc(union param_val val, void *dat)`
374			`{`
375			`ata_host *ata = dat;`
376
377			`if(val.int_val < 0 \|\| val.int_val > 255) {`
378			`fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_teoc: %d\n", val.int_val);`
379			`return;`
380			`}`
381
382			`ata->dma_mode0_teoc = val.int_val;`
383			`}`
384
385	1703	nogj	`static void ata_type(union param_val val, void *dat)`
386	1358	nogj	`{`
387	1364	nogj	`ata_host *ata = dat;`
388	1703	nogj	`if(conf_dev <= 1)`
389			`ata->devices.device[conf_dev].conf.type = val.int_val;`
390	1358	nogj	`}`
391
392	1703	nogj	`static void ata_file(union param_val val, void *dat)`
393	1358	nogj	`{`
394	1364	nogj	`ata_host *ata = dat;`
395	1358	nogj
396	1703	nogj	`if(conf_dev <= 1)`
397			`if(!(ata->devices.device[conf_dev].conf.file = strdup(val.str_val))) {`
398			`fprintf(stderr, "Peripheral ATA: Run out of memory\n");`
399			`exit(-1);`
400			`}`
401	1358	nogj	`}`
402
403	1703	nogj	`static void ata_size(union param_val val, void *dat)`
404	1358	nogj	`{`
405	1364	nogj	`ata_host *ata = dat;`
406	1703	nogj	`if(conf_dev <= 1)`
407			`ata->devices.device[conf_dev].conf.size = val.int_val << 20;`
408	1358	nogj	`}`
409
410	1703	nogj	`static void ata_packet(union param_val val, void *dat)`
411	1358	nogj	`{`
412	1364	nogj	`ata_host *ata = dat;`
413	1703	nogj	`if(conf_dev <= 1)`
414			`ata->devices.device[conf_dev].conf.packet = val.int_val;`
415	1358	nogj	`}`
416
417	1703	nogj	`static void ata_enabled(union param_val val, void *dat)`
418	1358	nogj	`{`
419	1364	nogj	`ata_host *ata = dat;`
420	1703	nogj	`ata->enabled = val.int_val;`
421	1358	nogj	`}`
422
423	1712	nogj	`static void ata_heads(union param_val val, void *dat)`
424			`{`
425			`ata_host *ata = dat;`
426			`if(conf_dev <= 1)`
427			`ata->devices.device[conf_dev].conf.heads = val.int_val;`
428			`}`
429
430			`static void ata_sectors(union param_val val, void *dat)`
431			`{`
432			`ata_host *ata = dat;`
433			`if(conf_dev <= 1)`
434			`ata->devices.device[conf_dev].conf.sectors = val.int_val;`
435			`}`
436
437			`static void ata_firmware(union param_val val, void *dat)`
438			`{`
439			`ata_host *ata = dat;`
440			`if(conf_dev <= 1)`
441			`if(!(ata->devices.device[conf_dev].conf.firmware = strdup(val.str_val))) {`
442			`fprintf(stderr, "Peripheral ATA: Run out of memory\n");`
443			`exit(-1);`
444			`}`
445			`}`
446
447			`static void ata_mwdma(union param_val val, void *dat)`
448			`{`
449			`ata_host *ata = dat;`
450			`if(conf_dev <= 1)`
451			`ata->devices.device[conf_dev].conf.mwdma = val.int_val;`
452			`}`
453
454			`static void ata_pio(union param_val val, void *dat)`
455			`{`
456			`ata_host *ata = dat;`
457			`if(conf_dev <= 1)`
458			`ata->devices.device[conf_dev].conf.pio = val.int_val;`
459			`}`
460
461
462	1703	nogj	`static void ata_start_device(union param_val val, void *dat)`
463	1358	nogj	`{`
464	1703	nogj	`conf_dev = val.int_val;`
465	1358	nogj
466	1703	nogj	`if(conf_dev > 1)`
467			`fprintf(stderr, "Device %d out-of-range\n", conf_dev);`
468	1358	nogj	`}`
469
470	1703	nogj	`static void ata_enddevice(union param_val val, void *dat)`
471	1461	nogj	`{`
472	1703	nogj	`conf_dev = 2;`
473	1461	nogj	`}`
474
475	1649	nogj	`static void *ata_sec_start(void)`
476	1364	nogj	`{`
477			`ata_host *new = malloc(sizeof(ata_host));`
478
479			`if(!new) {`
480			`fprintf(stderr, "Peripheral ATA: Run out of memory\n");`
481			`exit(-1);`
482			`}`
483
484			`memset(new, 0, sizeof(ata_host));`
485	1461	nogj	`new->enabled = 1;`
486	1701	nogj	`new->dev_id = 1;`
487
488	1702	nogj	`new->pio_mode0_t1 = PIO_MODE0_T1;`
489			`new->pio_mode0_t2 = PIO_MODE0_T2;`
490			`new->pio_mode0_t4 = PIO_MODE0_T4;`
491			`new->pio_mode0_teoc = PIO_MODE0_TEOC;`
492
493			`new->dma_mode0_tm = DMA_MODE0_TM;`
494			`new->dma_mode0_td = DMA_MODE0_TD;`
495			`new->dma_mode0_teoc = DMA_MODE0_TEOC;`
496
497	1712	nogj	`new->devices.device[0].conf.heads = 7;`
498			`new->devices.device[0].conf.sectors = 32;`
499			`new->devices.device[0].conf.firmware = "02207031";`
500			`new->devices.device[0].conf.mwdma = 2;`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [peripheral/] [atahost.c] - Blame information for rev 1713