URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [peripheral/] [atahost.c] - Blame information for rev 1726

Go to most recent revision | Details | Compare with Previous | View Log


/*
    atahost.c -- ATA Host code simulation
    Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
 
    This file is part of OpenRISC 1000 Architectural Simulator
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
 
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
/* get a prototype for 'reg_mem_area()', and 'adjust_rw_delay()' */
#include "abstract.h"
#include "sim-config.h"
#include "sched.h"
#include "pic.h"
#include "debug.h"
 
#include "atahost.h"
 
/* default timing reset values */
#define PIO_MODE0_T1 6
#define PIO_MODE0_T2 28
#define PIO_MODE0_T4 2
#define PIO_MODE0_TEOC 23
 
#define DMA_MODE0_TM 4
#define DMA_MODE0_TD 21
#define DMA_MODE0_TEOC 21
 
DEFAULT_DEBUG_CHANNEL(ata);
 
/* reset and initialize ATA host core(s) */
static void ata_reset(void *dat)
{
   ata_host *ata = dat;
 
   // reset the core registers
   ata->regs.ctrl  = 0x0001;
   ata->regs.stat  = (ata->dev_id << 28) | (ata->rev << 24);
   ata->regs.pctr  = (ata->pio_mode0_teoc << ATA_TEOC) |
                     (ata->pio_mode0_t4 << ATA_T4) |
                     (ata->pio_mode0_t2 << ATA_T2) |
                     (ata->pio_mode0_t1 << ATA_T1);
   ata->regs.pftr0 = ata->regs.pctr;
   ata->regs.pftr1 = ata->regs.pctr;
   ata->regs.dtr0  = (ata->dma_mode0_teoc << ATA_TEOC) |
                     (ata->dma_mode0_td << ATA_TD) |
                     (ata->dma_mode0_tm << ATA_TM);
   ata->regs.dtr1  = ata->regs.dtr0;
   ata->regs.txb   = 0;
 
   // inform simulator about new read/write delay timings
   adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
 
   /* the reset bit in the control register 'ctrl' is set, reset connect ata-devices */
   ata_devices_hw_reset(&ata->devices, 1);
}
/* ========================================================================= */
 
 
/* Assert interrupt */
void ata_int(void *dat)
{
  ata_host *ata = dat;
  if(!(ata->regs.stat & ATA_IDEIS)) {
    ata->regs.stat |= ATA_IDEIS;
    report_interrupt(ata->irq);
  }
}
/* ========================================================================= */
 
 
/*
  Read a register
*/
static uint32_t ata_read32( oraddr_t addr, void *dat )
{
    ata_host *ata = dat;
 
    /* determine if ata_host or ata_device addressed */
    if (is_ata_hostadr(addr))
    {
        // Accesses to internal register take 2cycles
        adjust_rw_delay( ata->mem, 2, 2 );
 
        switch( addr ) {
            case ATA_CTRL :
                TRACE("Read control register: %"PRIx32"\n", ata->regs.ctrl);
                return ata -> regs.ctrl;
 
            case ATA_STAT :
                return ata -> regs.stat;
 
            case ATA_PCTR :
                return ata -> regs.pctr;
 
            case ATA_PFTR0:
                return ata->dev_id > 1 ? ata->regs.pftr0 : 0;
 
            case ATA_PFTR1:
                return ata->dev_id > 1 ? ata->regs.pftr1 : 0;
 
            case ATA_DTR0 :
                return ata->dev_id > 2 ? ata->regs.dtr0 : 0;
 
            case ATA_DTR1 :
                return ata->dev_id > 2 ? ata->regs.dtr1 : 0;
 
            case ATA_RXB  :
                return ata->dev_id > 2 ? ata->regs.rxb : 0;
 
            default:
                return 0;
        }
    }
 
    /* check if the controller is enabled */
    if(ata->regs.ctrl & ATA_IDE_EN) {
        // make sure simulator uses correct read/write delay timings
        if(((addr & 0x7f) == ATA_DR) && ata->dev_id > 1) {
          if(ata->dev_sel)
              adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr1), ata_pio_delay(ata->regs.pftr1));
          else
              adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr0), ata_pio_delay(ata->regs.pftr0));
        }
        else
          adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr));
 
        return ata_devices_read(&ata->devices, addr & 0x7f);
    }
    return 0;
}
/* ========================================================================= */
 
 
/*
  Write a register
*/
static void ata_write32( oraddr_t addr, uint32_t value, void *dat )
{
    ata_host *ata = dat;
 
    /* determine if ata_host or ata_device addressed */
    if (is_ata_hostadr(addr))
    {
       // Accesses to internal register take 2cycles
       adjust_rw_delay( ata->mem, 2, 2 );
 
        switch( addr ) {
            case ATA_CTRL :
                TRACE("Writting control register: %"PRIx32"\n", value);
                ata -> regs.ctrl =  value;
 
                /* check if reset bit set, if so reset ata-devices    */
                if (value & ATA_RST)
                  ata_devices_hw_reset(&ata->devices, 1);
                else
                  ata_devices_hw_reset(&ata->devices, 0);
                break;
 
            case ATA_STAT :
                if(!(value & ATA_IDEIS) && (ata->regs.stat & ATA_IDEIS)) {
                  clear_interrupt(ata->irq);
                  ata->regs.stat &= ~ATA_IDEIS;
                }
                break;
 
            case ATA_PCTR :
                TRACE("PCTR: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
                      value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
                      value & 0xff);
                ata -> regs.pctr = value;
                break;
 
            case ATA_PFTR0:
                TRACE("PFTR0: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
                      value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
                      value & 0xff);
                ata -> regs.pftr0 = value;
                break;
 
            case ATA_PFTR1:
                TRACE("PFTR1: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
                      value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
                      value & 0xff);
                ata -> regs.pftr1 = value;
                break;
 
            case ATA_DTR0 :
                ata -> regs.dtr0  = value;
                break;
 
            case ATA_DTR1 :
                ata -> regs.dtr1  = value;
                break;
 
            case ATA_TXB  :
                ata -> regs.txb   = value;
                break;
 
            default:
                /* ERROR-macro currently only supports simple strings. */
                /*
                  fprintf(stderr, "ERROR  : Unknown register for OCIDEC(%1d).\n", DEV_ID );
 
                  Tried to show some useful info here.
                  But when using 'DM'-simulator-command, the screen gets filled with these messages.
                  Thereby eradicating the usefulness of the message
                */
                break;
        }
        return;
    }
 
    /* check if the controller is enabled */
    if(ata->regs.ctrl & ATA_IDE_EN) {
        // make sure simulator uses correct read/write delay timings
        if(((addr & 0x7f) == ATA_DR) && (ata->dev_id > 1)) {
          if(ata->dev_sel)
            adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr1), ata_pio_delay(ata->regs.pftr1));
          else
            adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr0), ata_pio_delay(ata->regs.pftr0));
        } else
          adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
 
        if((addr & 0x7f) == ATA_DHR)
          ata->dev_sel = value & ATA_DHR_DEV;
 
        ata_devices_write(&ata->devices, addr & 0x7f, value);
    }
}
/* ========================================================================= */
 
 
/* Dump status */
static void ata_status( void *dat )
{
  ata_host *ata = dat;
 
  if ( ata->baseaddr == 0 )
    return;
 
  PRINTF( "\nOCIDEC-%1d at: 0x%"PRIxADDR"\n", ata->dev_id, ata->baseaddr );
  PRINTF( "ATA CTRL     : 0x%08X\n", ata->regs.ctrl  );
  PRINTF( "ATA STAT     : 0x%08x\n", ata->regs.stat  );
  PRINTF( "ATA PCTR     : 0x%08x\n", ata->regs.pctr  );
 
  if(ata->dev_id > 1) {
    PRINTF( "ATA FCTR0    : 0x%08x\n", ata->regs.pftr0 );
    PRINTF( "ATA FCTR1    : 0x%08x\n", ata->regs.pftr1 );
  }
 
  if(ata->dev_id > 2) {
    PRINTF( "ATA DTR0     : 0x%08x\n", ata->regs.dtr0  );
    PRINTF( "ATA DTR1     : 0x%08x\n", ata->regs.dtr1  );
    PRINTF( "ATA TXD      : 0x%08x\n", ata->regs.txb   );
    PRINTF( "ATA RXD      : 0x%08x\n", ata->regs.rxb   );
  }
}
/* ========================================================================= */
 
/*----------------------------------------------------[ ATA Configuration ]---*/
static unsigned int conf_dev;
 
static void ata_baseaddr(union param_val val, void *dat)
{
  ata_host *ata = dat;
  ata->baseaddr = val.addr_val;
}
 
static void ata_irq(union param_val val, void *dat)
{
  ata_host *ata = dat;
  ata->irq = val.int_val;
}
 
static void ata_dev_id(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(val.int_val < 1 || val.int_val > 3) {
    fprintf(stderr, "Peripheral ATA: Unknown device id %d, useing 1\n",
            val.int_val);
    ata->dev_id = 1;
    return;
  }
 
  ata->dev_id = val.int_val;
}
 
static void ata_rev(union param_val val, void *dat)
{
  ata_host *ata = dat;
  ata->rev = val.int_val;
}
 
static void ata_pio_mode0_t1(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t1: %d\n", val.int_val);
    return;
  }
 
  ata->pio_mode0_t1 = val.int_val;
}
 
static void ata_pio_mode0_t2(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t2: %d\n", val.int_val);
    return;
  }
 
  ata->pio_mode0_t2 = val.int_val;
}
 
static void ata_pio_mode0_t4(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t4: %d\n", val.int_val);
    return;
  }
 
  ata->pio_mode0_t4 = val.int_val;
}
 
static void ata_pio_mode0_teoc(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_teoc: %d\n", val.int_val);
    return;
  }
 
  ata->pio_mode0_teoc = val.int_val;
}
 
static void ata_dma_mode0_tm(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_tm: %d\n", val.int_val);
    return;
  }
 
  ata->dma_mode0_tm = val.int_val;
}
 
static void ata_dma_mode0_td(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_td: %d\n", val.int_val);
    return;
  }
 
  ata->dma_mode0_td = val.int_val;
}
 
static void ata_dma_mode0_teoc(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(val.int_val < 0 || val.int_val > 255) {
    fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_teoc: %d\n", val.int_val);
    return;
  }
 
  ata->dma_mode0_teoc = val.int_val;
}
 
static void ata_type(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.type = val.int_val;
}
 
static void ata_file(union param_val val, void *dat)
{
  ata_host *ata = dat;
 
  if(conf_dev <= 1)
    if(!(ata->devices.device[conf_dev].conf.file = strdup(val.str_val))) {
      fprintf(stderr, "Peripheral ATA: Run out of memory\n");
      exit(-1);
    }
}
 
static void ata_size(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.size = val.int_val << 20;
}
 
static void ata_packet(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.packet = val.int_val;
}
 
static void ata_enabled(union param_val val, void *dat)
{
  ata_host *ata = dat;
  ata->enabled = val.int_val;
}
 
static void ata_heads(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.heads = val.int_val;
}
 
static void ata_sectors(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.sectors = val.int_val;
}
 
static void ata_firmware(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    if(!(ata->devices.device[conf_dev].conf.firmware = strdup(val.str_val))) {
      fprintf(stderr, "Peripheral ATA: Run out of memory\n");
      exit(-1);
    }
}
 
static void ata_mwdma(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.mwdma = val.int_val;
}
 
static void ata_pio(union param_val val, void *dat)
{
  ata_host *ata = dat;
  if(conf_dev <= 1)
    ata->devices.device[conf_dev].conf.pio = val.int_val;
}
 
 
static void ata_start_device(union param_val val, void *dat)
{
  conf_dev = val.int_val;
 
  if(conf_dev > 1)
    fprintf(stderr, "Device %d out-of-range\n", conf_dev);
}
 
static void ata_enddevice(union param_val val, void *dat)
{
  conf_dev = 2;
}
 
static void *ata_sec_start(void)
{
  ata_host *new = malloc(sizeof(ata_host));
 
  if(!new) {
    fprintf(stderr, "Peripheral ATA: Run out of memory\n");
    exit(-1);
  }
 
  memset(new, 0, sizeof(ata_host));
  new->enabled = 1;
  new->dev_id = 1;
 
  new->pio_mode0_t1 = PIO_MODE0_T1;
  new->pio_mode0_t2 = PIO_MODE0_T2;
  new->pio_mode0_t4 = PIO_MODE0_T4;
  new->pio_mode0_teoc = PIO_MODE0_TEOC;
 
  new->dma_mode0_tm = DMA_MODE0_TM;
  new->dma_mode0_td = DMA_MODE0_TD;
  new->dma_mode0_teoc = DMA_MODE0_TEOC;
 
  new->devices.device[0].conf.heads = 7;
  new->devices.device[0].conf.sectors = 32;
  new->devices.device[0].conf.firmware = "02207031";
  new->devices.device[0].conf.mwdma = 2;
  new->devices.device[0].conf.pio = 4;
 
  new->devices.device[1].conf.heads = 7;
  new->devices.device[1].conf.sectors = 32;
  new->devices.device[1].conf.firmware = "02207031";
  new->devices.device[1].conf.mwdma = 2;
  new->devices.device[1].conf.pio = 4;
 
  return new;
}
 
static void ata_sec_end(void *dat)
{
  ata_host *ata = dat;
  struct mem_ops ops;
 
  if(!ata->enabled) {
    free(dat);
    return;
  }
 
  /* Connect ata_devices.                                            */
  ata_devices_init(&ata->devices);
  ata->devices.device[0].internals.host = ata;
  ata->devices.device[1].internals.host = ata;
 
  memset(&ops, 0, sizeof(struct mem_ops));
 
  ops.readfunc32 = ata_read32;
  ops.read_dat32 = dat;
  ops.writefunc32 = ata_write32;
  ops.write_dat32 = dat;
 
  /* Delays will be readjusted later */
  ops.delayr = 2;
  ops.delayw = 2;
 
  ata->mem = reg_mem_area(ata->baseaddr, ATA_ADDR_SPACE, 0, &ops);
 
  reg_sim_reset(ata_reset, dat);
  reg_sim_stat(ata_status, dat);
}
 
void reg_ata_sec(void)
{
  struct config_section *sec = reg_config_sec("ata", ata_sec_start, ata_sec_end);
 
  reg_config_param(sec, "enabled", paramt_int, ata_enabled);
  reg_config_param(sec, "baseaddr", paramt_addr, ata_baseaddr);
  reg_config_param(sec, "irq", paramt_int, ata_irq);
  reg_config_param(sec, "dev_id", paramt_int, ata_dev_id);
  reg_config_param(sec, "rev", paramt_int, ata_rev);
 
  reg_config_param(sec, "pio_mode0_t1", paramt_int, ata_pio_mode0_t1);
  reg_config_param(sec, "pio_mode0_t2", paramt_int, ata_pio_mode0_t2);
  reg_config_param(sec, "pio_mode0_t4", paramt_int, ata_pio_mode0_t4);
  reg_config_param(sec, "pio_mode0_teoc", paramt_int, ata_pio_mode0_teoc);
 
  reg_config_param(sec, "dma_mode0_tm", paramt_int, ata_dma_mode0_tm);
  reg_config_param(sec, "dma_mode0_td", paramt_int, ata_dma_mode0_td);
  reg_config_param(sec, "dma_mode0_teoc", paramt_int, ata_dma_mode0_teoc);
 
  reg_config_param(sec, "device", paramt_int, ata_start_device);
  reg_config_param(sec, "enddevice", paramt_int, ata_enddevice);
 
  reg_config_param(sec, "type", paramt_int, ata_type);
  reg_config_param(sec, "file", paramt_str, ata_file);
  reg_config_param(sec, "size", paramt_int, ata_size);
  reg_config_param(sec, "packet", paramt_int, ata_packet);
  reg_config_param(sec, "heads", paramt_int, ata_heads);
  reg_config_param(sec, "sectors", paramt_int, ata_sectors);
  reg_config_param(sec, "firmware", paramt_int, ata_firmware);
  reg_config_param(sec, "mwdma", paramt_int, ata_mwdma);
  reg_config_param(sec, "pio", paramt_int, ata_pio);
}

Line No.	Rev	Author	Line
1	876	rherveille	`/*`
2			`atahost.c -- ATA Host code simulation`
3			`Copyright (C) 2002 Richard Herveille, rherveille@opencores.org`
4
5			`This file is part of OpenRISC 1000 Architectural Simulator`
6
7			`This program is free software; you can redistribute it and/or modify`
8			`it under the terms of the GNU General Public License as published by`
9			`the Free Software Foundation; either version 2 of the License, or`
10			`(at your option) any later version`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.`
20			`*/`
21
22	1364	nogj	`#include <string.h>`
23
24	1350	nogj	`#include "config.h"`
25
26			`#ifdef HAVE_INTTYPES_H`
27			`#include <inttypes.h>`
28			`#endif`
29
30			`#include "port.h"`
31			`#include "arch.h"`
32	1486	nogj	`/* get a prototype for 'reg_mem_area()', and 'adjust_rw_delay()' */`
33	876	rherveille	`#include "abstract.h"`
34			`#include "sim-config.h"`
35			`#include "sched.h"`
36	1726	nogj	`#include "pic.h"`
37	1713	nogj	`#include "debug.h"`
38	876	rherveille
39			`#include "atahost.h"`
40
41	1702	nogj	`/* default timing reset values */`
42			`#define PIO_MODE0_T1 6`
43			`#define PIO_MODE0_T2 28`
44			`#define PIO_MODE0_T4 2`
45			`#define PIO_MODE0_TEOC 23`
46
47			`#define DMA_MODE0_TM 4`
48			`#define DMA_MODE0_TD 21`
49			`#define DMA_MODE0_TEOC 21`
50
51	1713	nogj	`DEFAULT_DEBUG_CHANNEL(ata);`
52
53	876	rherveille	`/* reset and initialize ATA host core(s) */`
54	1649	nogj	`static void ata_reset(void *dat)`
55	876	rherveille	`{`
56	1364	nogj	`ata_host *ata = dat;`
57	876	rherveille
58	1364	nogj	`// reset the core registers`
59			`ata->regs.ctrl = 0x0001;`
60	1701	nogj	`ata->regs.stat = (ata->dev_id << 28) \| (ata->rev << 24);`
61	1702	nogj	`ata->regs.pctr = (ata->pio_mode0_teoc << ATA_TEOC) \|`
62			`(ata->pio_mode0_t4 << ATA_T4) \|`
63			`(ata->pio_mode0_t2 << ATA_T2) \|`
64			`(ata->pio_mode0_t1 << ATA_T1);`
65			`ata->regs.pftr0 = ata->regs.pctr;`
66			`ata->regs.pftr1 = ata->regs.pctr;`
67			`ata->regs.dtr0 = (ata->dma_mode0_teoc << ATA_TEOC) \|`
68			`(ata->dma_mode0_td << ATA_TD) \|`
69			`(ata->dma_mode0_tm << ATA_TM);`
70			`ata->regs.dtr1 = ata->regs.dtr0;`
71	1364	nogj	`ata->regs.txb = 0;`
72	919	rherveille
73	1364	nogj	`// inform simulator about new read/write delay timings`
74	1486	nogj	`adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );`
75	876	rherveille
76	1364	nogj	`/* the reset bit in the control register 'ctrl' is set, reset connect ata-devices */`
77			`ata_devices_hw_reset(&ata->devices, 1);`
78	876	rherveille	`}`
79			`/* ========================================================================= */`
80
81
82	1726	nogj	`/* Assert interrupt */`
83			`void ata_int(void *dat)`
84			`{`
85			`ata_host *ata = dat;`
86			`if(!(ata->regs.stat & ATA_IDEIS)) {`
87			`ata->regs.stat \|= ATA_IDEIS;`
88			`report_interrupt(ata->irq);`
89			`}`
90			`}`
91			`/* ========================================================================= */`
92
93
94	876	rherveille	`/*`
95			`Read a register`
96			`*/`
97	1649	nogj	`static uint32_t ata_read32( oraddr_t addr, void *dat )`
98	876	rherveille	`{`
99	1364	nogj	`ata_host *ata = dat;`
100	876	rherveille
101			`/* determine if ata_host or ata_device addressed */`
102			`if (is_ata_hostadr(addr))`
103	919	rherveille	`{`
104			`// Accesses to internal register take 2cycles`
105	1486	nogj	`adjust_rw_delay( ata->mem, 2, 2 );`
106	919	rherveille
107	876	rherveille	`switch( addr ) {`
108			`case ATA_CTRL :`
109	1713	nogj	`TRACE("Read control register: %"PRIx32"\n", ata->regs.ctrl);`
110	876	rherveille	`return ata -> regs.ctrl;`
111
112			`case ATA_STAT :`
113			`return ata -> regs.stat;`
114
115			`case ATA_PCTR :`
116			`return ata -> regs.pctr;`
117
118			`case ATA_PFTR0:`
119	1701	nogj	`return ata->dev_id > 1 ? ata->regs.pftr0 : 0;`
120	876	rherveille
121			`case ATA_PFTR1:`
122	1701	nogj	`return ata->dev_id > 1 ? ata->regs.pftr1 : 0;`
123	876	rherveille
124			`case ATA_DTR0 :`
125	1701	nogj	`return ata->dev_id > 2 ? ata->regs.dtr0 : 0;`
126	876	rherveille
127			`case ATA_DTR1 :`
128	1701	nogj	`return ata->dev_id > 2 ? ata->regs.dtr1 : 0;`
129	876	rherveille
130			`case ATA_RXB :`
131	1701	nogj	`return ata->dev_id > 2 ? ata->regs.rxb : 0;`
132	876	rherveille
133			`default:`
134			`return 0;`
135	919	rherveille	`}`
136	876	rherveille	`}`
137	1701	nogj
138	1019	rherveille	`/* check if the controller is enabled */`
139	1701	nogj	`if(ata->regs.ctrl & ATA_IDE_EN) {`
140	919	rherveille	`// make sure simulator uses correct read/write delay timings`
141	1701	nogj	`if(((addr & 0x7f) == ATA_DR) && ata->dev_id > 1) {`
142			`if(ata->dev_sel)`
143			`adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr1), ata_pio_delay(ata->regs.pftr1));`
144	919	rherveille	`else`
145	1701	nogj	`adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr0), ata_pio_delay(ata->regs.pftr0));`
146	919	rherveille	`}`
147			`else`
148	1701	nogj	`adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr));`
149	919	rherveille
150			`return ata_devices_read(&ata->devices, addr & 0x7f);`
151			`}`
152	1557	nogj	`return 0;`
153	876	rherveille	`}`
154			`/* ========================================================================= */`
155
156
157			`/*`
158			`Write a register`
159			`*/`
160	1649	nogj	`static void ata_write32( oraddr_t addr, uint32_t value, void *dat )`
161	876	rherveille	`{`
162	1364	nogj	`ata_host *ata = dat;`
163	876	rherveille
164			`/* determine if ata_host or ata_device addressed */`
165			`if (is_ata_hostadr(addr))`
166	919	rherveille	`{`
167			`// Accesses to internal register take 2cycles`
168	1486	nogj	`adjust_rw_delay( ata->mem, 2, 2 );`
169	919	rherveille
170	876	rherveille	`switch( addr ) {`
171			`case ATA_CTRL :`
172	1713	nogj	`TRACE("Writting control register: %"PRIx32"\n", value);`
173	876	rherveille	`ata -> regs.ctrl = value;`
174
175			`/* check if reset bit set, if so reset ata-devices */`
176			`if (value & ATA_RST)`
177			`ata_devices_hw_reset(&ata->devices, 1);`
178			`else`
179			`ata_devices_hw_reset(&ata->devices, 0);`
180			`break;`
181
182			`case ATA_STAT :`
183	1726	nogj	`if(!(value & ATA_IDEIS) && (ata->regs.stat & ATA_IDEIS)) {`
184			`clear_interrupt(ata->irq);`
185			`ata->regs.stat &= ~ATA_IDEIS;`
186			`}`
187	876	rherveille	`break;`
188
189			`case ATA_PCTR :`
190	1713	nogj	`TRACE("PCTR: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",`
191			`value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,`
192			`value & 0xff);`
193	876	rherveille	`ata -> regs.pctr = value;`
194			`break;`
195
196			`case ATA_PFTR0:`
197	1713	nogj	`TRACE("PFTR0: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",`
198			`value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,`
199			`value & 0xff);`
200	876	rherveille	`ata -> regs.pftr0 = value;`
201			`break;`
202
203			`case ATA_PFTR1:`
204	1713	nogj	`TRACE("PFTR1: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",`
205			`value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,`
206			`value & 0xff);`
207	876	rherveille	`ata -> regs.pftr1 = value;`
208			`break;`
209
210			`case ATA_DTR0 :`
211			`ata -> regs.dtr0 = value;`
212			`break;`
213
214			`case ATA_DTR1 :`
215			`ata -> regs.dtr1 = value;`
216			`break;`
217
218			`case ATA_TXB :`
219			`ata -> regs.txb = value;`
220			`break;`
221
222			`default:`
223			`/* ERROR-macro currently only supports simple strings. */`
224			`/*`
225			`fprintf(stderr, "ERROR : Unknown register for OCIDEC(%1d).\n", DEV_ID );`
226
227			`Tried to show some useful info here.`
228			`But when using 'DM'-simulator-command, the screen gets filled with these messages.`
229			`Thereby eradicating the usefulness of the message`
230			`*/`
231			`break;`
232			`}`
233	1701	nogj	`return;`
234	919	rherveille	`}`
235	1701	nogj
236	1019	rherveille	`/* check if the controller is enabled */`
237	1701	nogj	`if(ata->regs.ctrl & ATA_IDE_EN) {`
238	919	rherveille	`// make sure simulator uses correct read/write delay timings`
239	1701	nogj	`if(((addr & 0x7f) == ATA_DR) && (ata->dev_id > 1)) {`
240			`if(ata->dev_sel)`
241			`adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr1), ata_pio_delay(ata->regs.pftr1));`
242	919	rherveille	`else`
243	1701	nogj	`adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr0), ata_pio_delay(ata->regs.pftr0));`
244			`} else`
245			`adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );`
246	919	rherveille
247	1701	nogj	`if((addr & 0x7f) == ATA_DHR)`
248			`ata->dev_sel = value & ATA_DHR_DEV;`
249
250	876	rherveille	`ata_devices_write(&ata->devices, addr & 0x7f, value);`
251	919	rherveille	`}`
252	876	rherveille	`}`
253			`/* ========================================================================= */`
254
255
256			`/* Dump status */`
257	1649	nogj	`static void ata_status( void *dat )`
258	876	rherveille	`{`
259	1364	nogj	`ata_host *ata = dat;`
260	876	rherveille
261	1364	nogj	`if ( ata->baseaddr == 0 )`
262			`return;`
263	876	rherveille
264	1701	nogj	`PRINTF( "\nOCIDEC-%1d at: 0x%"PRIxADDR"\n", ata->dev_id, ata->baseaddr );`
265	1364	nogj	`PRINTF( "ATA CTRL : 0x%08X\n", ata->regs.ctrl );`
266			`PRINTF( "ATA STAT : 0x%08x\n", ata->regs.stat );`
267			`PRINTF( "ATA PCTR : 0x%08x\n", ata->regs.pctr );`
268	876	rherveille
269	1701	nogj	`if(ata->dev_id > 1) {`
270			`PRINTF( "ATA FCTR0 : 0x%08x\n", ata->regs.pftr0 );`
271			`PRINTF( "ATA FCTR1 : 0x%08x\n", ata->regs.pftr1 );`
272			`}`
273	876	rherveille
274	1701	nogj	`if(ata->dev_id > 2) {`
275			`PRINTF( "ATA DTR0 : 0x%08x\n", ata->regs.dtr0 );`
276			`PRINTF( "ATA DTR1 : 0x%08x\n", ata->regs.dtr1 );`
277			`PRINTF( "ATA TXD : 0x%08x\n", ata->regs.txb );`
278			`PRINTF( "ATA RXD : 0x%08x\n", ata->regs.rxb );`
279			`}`
280	876	rherveille	`}`
281			`/* ========================================================================= */`
282	1358	nogj
283			`/----------------------------------------------------[ ATA Configuration ]---/`
284	1703	nogj	`static unsigned int conf_dev;`
285
286	1649	nogj	`static void ata_baseaddr(union param_val val, void *dat)`
287	1358	nogj	`{`
288	1364	nogj	`ata_host *ata = dat;`
289			`ata->baseaddr = val.addr_val;`
290	1358	nogj	`}`
291
292	1649	nogj	`static void ata_irq(union param_val val, void *dat)`
293	1358	nogj	`{`
294	1364	nogj	`ata_host *ata = dat;`
295			`ata->irq = val.int_val;`
296	1358	nogj	`}`
297
298	1701	nogj	`static void ata_dev_id(union param_val val, void *dat)`
299			`{`
300			`ata_host *ata = dat;`
301			`if(val.int_val < 1 \|\| val.int_val > 3) {`
302			`fprintf(stderr, "Peripheral ATA: Unknown device id %d, useing 1\n",`
303			`val.int_val);`
304			`ata->dev_id = 1;`
305			`return;`
306			`}`
307
308			`ata->dev_id = val.int_val;`
309			`}`
310
311			`static void ata_rev(union param_val val, void *dat)`
312			`{`
313			`ata_host *ata = dat;`
314			`ata->rev = val.int_val;`
315			`}`
316
317	1702	nogj	`static void ata_pio_mode0_t1(union param_val val, void *dat)`
318			`{`
319			`ata_host *ata = dat;`
320
321			`if(val.int_val < 0 \|\| val.int_val > 255) {`
322			`fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t1: %d\n", val.int_val);`
323			`return;`
324			`}`
325
326			`ata->pio_mode0_t1 = val.int_val;`
327			`}`
328
329			`static void ata_pio_mode0_t2(union param_val val, void *dat)`
330			`{`
331			`ata_host *ata = dat;`
332
333			`if(val.int_val < 0 \|\| val.int_val > 255) {`
334			`fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t2: %d\n", val.int_val);`
335			`return;`
336			`}`
337
338			`ata->pio_mode0_t2 = val.int_val;`
339			`}`
340
341			`static void ata_pio_mode0_t4(union param_val val, void *dat)`
342			`{`
343			`ata_host *ata = dat;`
344
345			`if(val.int_val < 0 \|\| val.int_val > 255) {`
346			`fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t4: %d\n", val.int_val);`
347			`return;`
348			`}`
349
350			`ata->pio_mode0_t4 = val.int_val;`
351			`}`
352
353			`static void ata_pio_mode0_teoc(union param_val val, void *dat)`
354			`{`
355			`ata_host *ata = dat;`
356
357			`if(val.int_val < 0 \|\| val.int_val > 255) {`
358			`fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_teoc: %d\n", val.int_val);`
359			`return;`
360			`}`
361
362			`ata->pio_mode0_teoc = val.int_val;`
363			`}`
364
365			`static void ata_dma_mode0_tm(union param_val val, void *dat)`
366			`{`
367			`ata_host *ata = dat;`
368
369			`if(val.int_val < 0 \|\| val.int_val > 255) {`
370			`fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_tm: %d\n", val.int_val);`
371			`return;`
372			`}`
373
374			`ata->dma_mode0_tm = val.int_val;`
375			`}`
376
377			`static void ata_dma_mode0_td(union param_val val, void *dat)`
378			`{`
379			`ata_host *ata = dat;`
380
381			`if(val.int_val < 0 \|\| val.int_val > 255) {`
382			`fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_td: %d\n", val.int_val);`
383			`return;`
384			`}`
385
386			`ata->dma_mode0_td = val.int_val;`
387			`}`
388
389			`static void ata_dma_mode0_teoc(union param_val val, void *dat)`
390			`{`
391			`ata_host *ata = dat;`
392
393			`if(val.int_val < 0 \|\| val.int_val > 255) {`
394			`fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_teoc: %d\n", val.int_val);`
395			`return;`
396			`}`
397
398			`ata->dma_mode0_teoc = val.int_val;`
399			`}`
400
401	1703	nogj	`static void ata_type(union param_val val, void *dat)`
402	1358	nogj	`{`
403	1364	nogj	`ata_host *ata = dat;`
404	1703	nogj	`if(conf_dev <= 1)`
405			`ata->devices.device[conf_dev].conf.type = val.int_val;`
406	1358	nogj	`}`
407
408	1703	nogj	`static void ata_file(union param_val val, void *dat)`
409	1358	nogj	`{`
410	1364	nogj	`ata_host *ata = dat;`
411	1358	nogj
412	1703	nogj	`if(conf_dev <= 1)`
413			`if(!(ata->devices.device[conf_dev].conf.file = strdup(val.str_val))) {`
414			`fprintf(stderr, "Peripheral ATA: Run out of memory\n");`
415			`exit(-1);`
416			`}`
417	1358	nogj	`}`
418
419	1703	nogj	`static void ata_size(union param_val val, void *dat)`
420	1358	nogj	`{`
421	1364	nogj	`ata_host *ata = dat;`
422	1703	nogj	`if(conf_dev <= 1)`
423			`ata->devices.device[conf_dev].conf.size = val.int_val << 20;`
424	1358	nogj	`}`
425
426	1703	nogj	`static void ata_packet(union param_val val, void *dat)`
427	1358	nogj	`{`
428	1364	nogj	`ata_host *ata = dat;`
429	1703	nogj	`if(conf_dev <= 1)`
430			`ata->devices.device[conf_dev].conf.packet = val.int_val;`
431	1358	nogj	`}`
432
433	1703	nogj	`static void ata_enabled(union param_val val, void *dat)`
434	1358	nogj	`{`
435	1364	nogj	`ata_host *ata = dat;`
436	1703	nogj	`ata->enabled = val.int_val;`
437	1358	nogj	`}`
438
439	1712	nogj	`static void ata_heads(union param_val val, void *dat)`
440			`{`
441			`ata_host *ata = dat;`
442			`if(conf_dev <= 1)`
443			`ata->devices.device[conf_dev].conf.heads = val.int_val;`
444			`}`
445
446			`static void ata_sectors(union param_val val, void *dat)`
447			`{`
448			`ata_host *ata = dat;`
449			`if(conf_dev <= 1)`
450			`ata->devices.device[conf_dev].conf.sectors = val.int_val;`
451			`}`
452
453			`static void ata_firmware(union param_val val, void *dat)`
454			`{`
455			`ata_host *ata = dat;`
456			`if(conf_dev <= 1)`
457			`if(!(ata->devices.device[conf_dev].conf.firmware = strdup(val.str_val))) {`
458			`fprintf(stderr, "Peripheral ATA: Run out of memory\n");`
459			`exit(-1);`
460			`}`
461			`}`
462
463			`static void ata_mwdma(union param_val val, void *dat)`
464			`{`
465			`ata_host *ata = dat;`
466			`if(conf_dev <= 1)`
467			`ata->devices.device[conf_dev].conf.mwdma = val.int_val;`
468			`}`
469
470			`static void ata_pio(union param_val val, void *dat)`
471			`{`
472			`ata_host *ata = dat;`
473			`if(conf_dev <= 1)`
474			`ata->devices.device[conf_dev].conf.pio = val.int_val;`
475			`}`
476
477
478	1703	nogj	`static void ata_start_device(union param_val val, void *dat)`
479	1358	nogj	`{`
480	1703	nogj	`conf_dev = val.int_val;`
481	1358	nogj
482	1703	nogj	`if(conf_dev > 1)`
483			`fprintf(stderr, "Device %d out-of-range\n", conf_dev);`
484	1358	nogj	`}`
485
486	1703	nogj	`static void ata_enddevice(union param_val val, void *dat)`
487	1461	nogj	`{`
488	1703	nogj	`conf_dev = 2;`
489	1461	nogj	`}`
490
491	1649	nogj	`static void *ata_sec_start(void)`
492	1364	nogj	`{`
493			`ata_host *new = malloc(sizeof(ata_host));`
494
495			`if(!new) {`
496			`fprintf(stderr, "Peripheral ATA: Run out of memory\n");`
497			`exit(-1);`
498			`}`
499
500			`memset(new, 0, sizeof(ata_host));`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [peripheral/] [atahost.c] - Blame information for rev 1726