1 |
876 |
rherveille |
/*
|
2 |
|
|
atahost.h -- ATA Host code simulation
|
3 |
|
|
Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
|
4 |
|
|
|
5 |
|
|
This file is part of OpenRISC 1000 Architectural Simulator
|
6 |
|
|
|
7 |
|
|
This program is free software; you can redistribute it and/or modify
|
8 |
|
|
it under the terms of the GNU General Public License as published by
|
9 |
|
|
the Free Software Foundation; either version 2 of the License, or
|
10 |
|
|
(at your option) any later version
|
11 |
|
|
|
12 |
|
|
This program is distributed in the hope that it will be useful,
|
13 |
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 |
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
15 |
|
|
GNU General Public License for more details.
|
16 |
|
|
|
17 |
|
|
You should have received a copy of the GNU General Public License
|
18 |
|
|
along with this program; if not, write to the Free Software
|
19 |
|
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
20 |
|
|
*/
|
21 |
|
|
|
22 |
|
|
/*
|
23 |
|
|
* Definitions for the Opencores ATA Host Controller Core
|
24 |
|
|
*/
|
25 |
|
|
|
26 |
|
|
#ifndef __OR1KSIM_ATAH_H
|
27 |
|
|
#define __OR1KSIM_ATAH_H
|
28 |
|
|
|
29 |
|
|
#include "atadevice.h"
|
30 |
|
|
|
31 |
|
|
/* --- Register definitions --- */
|
32 |
|
|
|
33 |
|
|
/* ----- Core Registers */
|
34 |
|
|
#define ATA_CTRL 0x00 /* Control register */
|
35 |
|
|
#define ATA_STAT 0x04 /* Status register */
|
36 |
|
|
#define ATA_PCTR 0x08 /* PIO command timing register */
|
37 |
|
|
#define ATA_PFTR0 0x0c /* PIO Fast Timing register Device0 */
|
38 |
|
|
#define ATA_PFTR1 0x10 /* PIO Fast Timing register Device1 */
|
39 |
|
|
#define ATA_DTR0 0x14 /* DMA Timing register Device2 */
|
40 |
|
|
#define ATA_DTR1 0x18 /* DMA Timing register Device1 */
|
41 |
|
|
#define ATA_TXB 0x3c /* DMA Transmit buffer */
|
42 |
|
|
#define ATA_RXB 0x3c /* DMA Receive buffer */
|
43 |
|
|
|
44 |
|
|
|
45 |
|
|
/* ---------------------------- */
|
46 |
|
|
/* ----- Bits definitions ----- */
|
47 |
|
|
/* ---------------------------- */
|
48 |
|
|
|
49 |
|
|
/* ----- Core Control register */
|
50 |
|
|
/* bits 31-16 are reserved */
|
51 |
|
|
#define ATA_DMA_EN (0<<15) /* DMAen, DMA enable bit */
|
52 |
|
|
/* bit 14 is reserved */
|
53 |
|
|
#define ATA_DMA_WR (1<<14) /* DMA Write transaction */
|
54 |
|
|
#define ATA_DMA_RD (0<<14) /* DMA Read transaction */
|
55 |
|
|
/* bits 13-10 are reserved */
|
56 |
|
|
#define ATA_BELEC1 (1<< 9) /* Big-Little endian conversion */
|
57 |
|
|
/* enable bit for Device1 */
|
58 |
|
|
#define ATA_BELEC0 (1<< 8) /* Big-Little endian conversion */
|
59 |
|
|
/* enable bit for Device0 */
|
60 |
|
|
#define ATA_IDE_EN (1<< 7) /* IDE core enable bit */
|
61 |
|
|
#define ATA_FTE1 (1<< 6) /* Device1 Fast PIO Timing Enable bit */
|
62 |
|
|
#define ATA_FTE0 (1<< 5) /* Device0 Fast PIO Timing Enable bit */
|
63 |
|
|
#define ATA_PWPP (1<< 4) /* PIO Write Ping-Pong Enable bit */
|
64 |
|
|
#define ATA_IORDY_FTE1 (1<< 3) /* Device1 Fast PIO Timing IORDY */
|
65 |
|
|
/* enable bit */
|
66 |
|
|
#define ATA_IORDY_FTE0 (1<< 2) /* Device0 Fast PIO Timing IORDY */
|
67 |
|
|
/* enable bit */
|
68 |
|
|
#define ATA_IORDY (1<< 1) /* PIO Command Timing IORDY enable bit*/
|
69 |
|
|
#define ATA_RST (1<< 0) /* ATA Reset bit */
|
70 |
|
|
|
71 |
|
|
/* ----- Core Status register */
|
72 |
|
|
#define ATA_DEVID 0xf0000000 /* bits 31-28 Device-ID */
|
73 |
|
|
#define ATA_REVNO 0x0f000000 /* bits 27-24 Revision number */
|
74 |
|
|
/* bits 23-16 are reserved */
|
75 |
|
|
#define ATA_DMA_TIP (1<<15) /* DMA Transfer in progress */
|
76 |
|
|
/* bits 14-10 are reserved */
|
77 |
|
|
#define ATA_DRBE (1<<10) /* DMA Receive buffer empty */
|
78 |
|
|
#define ATA_DTBF (1<< 9) /* DMA Transmit buffer full */
|
79 |
|
|
#define ATA_DMARQ (1<< 8) /* DMARQ Line status */
|
80 |
|
|
#define ATA_PIO_TIP (1<< 7 /* PIO Transfer in progress */
|
81 |
|
|
#define ATA_PWPPF (1<< 6) /* PIO write ping-pong full */
|
82 |
|
|
/* bits 5-1 are reserved */
|
83 |
|
|
#define ATA_IDEIS (1<< 0) /* IDE Interrupt status */
|
84 |
|
|
|
85 |
|
|
|
86 |
|
|
/* ----- Core Timing registers */
|
87 |
|
|
#define ATA_TEOC 24 /* End of cycle time DMA/PIO */
|
88 |
|
|
#define ATA_T4 16 /* DIOW- data hold time PIO */
|
89 |
|
|
#define ATA_T2 8 /* DIOR-/DIOW- pulse width PIO */
|
90 |
|
|
#define ATA_TD 8 /* DIOR-/DIOW- pulse width DMA */
|
91 |
|
|
#define ATA_T1 0 /* Address valid to DIOR-/DIOW- PIO */
|
92 |
|
|
#define ATA_TM 0 /* CS[1:0]valid to DIOR-/DIOW- DMA */
|
93 |
|
|
|
94 |
|
|
|
95 |
|
|
/* ----------------------------- */
|
96 |
|
|
/* ----- Simulator defines ----- */
|
97 |
|
|
/* ----------------------------- */
|
98 |
|
|
#define ATA_ADDR_SPACE 0x80
|
99 |
|
|
|
100 |
|
|
|
101 |
|
|
/* ---------------------------- */
|
102 |
|
|
/* ----- Structs ----- */
|
103 |
|
|
/* ---------------------------- */
|
104 |
|
|
typedef struct{
|
105 |
1461 |
nogj |
/* Is peripheral enabled? */
|
106 |
|
|
int enabled;
|
107 |
|
|
|
108 |
876 |
rherveille |
/* Base address in memory */
|
109 |
1350 |
nogj |
oraddr_t baseaddr;
|
110 |
876 |
rherveille |
|
111 |
1486 |
nogj |
/* Registered memory area */
|
112 |
|
|
struct dev_memarea *mem;
|
113 |
|
|
|
114 |
876 |
rherveille |
/* Which IRQ to generate */
|
115 |
|
|
int irq;
|
116 |
|
|
|
117 |
1701 |
nogj |
/* Which ocidec version is implemented */
|
118 |
|
|
int dev_id;
|
119 |
|
|
|
120 |
|
|
/* OCIDEC revision */
|
121 |
|
|
int rev;
|
122 |
|
|
|
123 |
|
|
/* Current selected device */
|
124 |
|
|
int dev_sel;
|
125 |
|
|
|
126 |
1702 |
nogj |
/* PIO T1 reset value */
|
127 |
|
|
uint8_t pio_mode0_t1;
|
128 |
|
|
|
129 |
|
|
/* PIO T2 reset value */
|
130 |
|
|
uint8_t pio_mode0_t2;
|
131 |
|
|
|
132 |
|
|
/* PIO T4 reset value */
|
133 |
|
|
uint8_t pio_mode0_t4;
|
134 |
|
|
|
135 |
|
|
/* PIO Teoc reset value */
|
136 |
|
|
uint8_t pio_mode0_teoc;
|
137 |
|
|
|
138 |
|
|
/* DMA Tm reset value */
|
139 |
|
|
uint8_t dma_mode0_tm;
|
140 |
|
|
|
141 |
|
|
/* DMA Td reset value */
|
142 |
|
|
uint8_t dma_mode0_td;
|
143 |
|
|
|
144 |
|
|
/* DMA Teoc reset value */
|
145 |
|
|
uint8_t dma_mode0_teoc;
|
146 |
|
|
|
147 |
876 |
rherveille |
/* ata host registers */
|
148 |
|
|
struct {
|
149 |
1698 |
nogj |
uint32_t ctrl;
|
150 |
|
|
uint32_t stat;
|
151 |
|
|
uint32_t pctr;
|
152 |
|
|
uint32_t pftr0;
|
153 |
|
|
uint32_t pftr1;
|
154 |
|
|
uint32_t dtr0;
|
155 |
|
|
uint32_t dtr1;
|
156 |
|
|
uint32_t txb;
|
157 |
|
|
uint32_t rxb;
|
158 |
876 |
rherveille |
} regs;
|
159 |
|
|
|
160 |
|
|
/* connected ATA devices (slaves) */
|
161 |
|
|
ata_devices devices;
|
162 |
|
|
} ata_host;
|
163 |
|
|
|
164 |
|
|
/* ---------------------------- */
|
165 |
|
|
/* ----- Prototypes ----- */
|
166 |
|
|
/* ---------------------------- */
|
167 |
1726 |
nogj |
void ata_int(void *dat);
|
168 |
876 |
rherveille |
|
169 |
|
|
|
170 |
|
|
/* ---------------------------- */
|
171 |
|
|
/* ----- Macros ----- */
|
172 |
|
|
/* ---------------------------- */
|
173 |
|
|
#define is_ata_hostadr(adr) (!(adr & 0x40))
|
174 |
|
|
|
175 |
919 |
rherveille |
// FIXME
|
176 |
|
|
#define ata_pio_delay(pioreg) ( (((pioreg >> ATA_T1) & 0xff) +1) + (((pioreg >> ATA_T2) & 0xff) +1) + (((pioreg >> ATA_T4) & 0xff) +1) +1 )
|
177 |
|
|
#define ata_dma_delay(dmareg) ( (((dmareg >> ATA_TD) & 0xff) +1) + (((pioreg >> ATA_TM) & 0xff) +1) +1 )
|
178 |
|
|
|
179 |
876 |
rherveille |
#endif
|