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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's definitions                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Parameters of the OR1200 core                               ////
////                                                              ////
////  To Do:                                                      ////
////   - add parameters that are missing                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11  2002/03/28 19:13:17  lampret
// Updated defines.
//
// Revision 1.10  2002/03/14 00:30:24  lampret
// Added alternative for critical path in DU.
//
// Revision 1.9  2002/03/11 01:26:26  lampret
// Fixed async loop. Changed multiplier type for ASIC.
//
// Revision 1.8  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.7  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.6  2002/01/19 14:10:22  lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.5  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.4  2002/01/14 09:44:12  lampret
// Default ASIC configuration does not sample WB inputs.
//
// Revision 1.3  2002/01/08 00:51:08  lampret
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
//
// Revision 1.2  2002/01/03 21:23:03  lampret
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.20  2001/12/04 05:02:36  lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.19  2001/11/27 19:46:57  lampret
// Now FPGA and ASIC target are separate.
//
// Revision 1.18  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
//
// Revision 1.17  2001/11/23 08:38:51  lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.16  2001/11/20 21:30:38  lampret
// Added OR1200_REGISTERED_INPUTS.
//
// Revision 1.15  2001/11/19 14:29:48  simons
// Cashes disabled.
//
// Revision 1.14  2001/11/13 10:02:21  lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.13  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.12  2001/11/10 03:43:57  lampret
// Fixed exceptions.
//
// Revision 1.11  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.10  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.8  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/17 08:01:19  lampret
// IC enable/disable.
//
// Revision 1.2  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
//
// Dump VCD
//
//`define OR1200_VCD_DUMP
 
//
// Generate debug messages during simulation
//
//`define OR1200_VERBOSE
 
//`define OR1200_ASIC
////////////////////////////////////////////////////////
//
// Typical configuration for an ASIC
//
`ifdef OR1200_ASIC
 
//
// Target ASIC memories
//
//`define OR1200_ARTISAN_SSP
//`define OR1200_ARTISAN_SDP
//`define OR1200_ARTISAN_STP
`define OR1200_VIRTUALSILICON_SSP
`define OR1200_VIRTUALSILICON_STP_T1
//`define OR1200_VIRTUALSILICON_STP_T2
 
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
 
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
 
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
 
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
 
//
// Register OR1200 WISHBONE outputs
// (at the moment correct operation
// only with registered outputs)
//
`define OR1200_REGISTERED_OUTPUTS
 
//
// Register OR1200 WISHBNE inputs
//
//`define OR1200_REGISTERED_INPUTS
 
//
// Select between ASIC optimized and generic multiplier
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
 
//
// Size/type of insn/data cache if implemented
//
// `define OR1200_IC_1W_4KB
`define OR1200_IC_1W_8KB
// `define OR1200_DC_1W_4KB
`define OR1200_DC_1W_8KB
 
`else
 
 
/////////////////////////////////////////////////////////
//
// Typical configuration for an FPGA
//
 
//
// Target FPGA memories
//
`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
 
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
 
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
 
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
 
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
 
//
// Register OR1200 WISHBONE outputs
// (at the moment works only with
// registered outputs)
//
`define OR1200_REGISTERED_OUTPUTS
 
//
// Register OR1200 WISHBONE inputs
//
//`define OR1200_REGISTERED_INPUTS
 
//
// Select between ASIC and generic multiplier
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
 
//
// Size/type of insn/data cache if implemented
// (consider available FPGA memory resources)
//
`define OR1200_IC_1W_4KB
//`define OR1200_IC_1W_8KB
`define OR1200_DC_1W_4KB
//`define OR1200_DC_1W_8KB
 
`endif
 
 
//////////////////////////////////////////////////////////
//
// Do not change below unless you know what you are doing
//
 
// Operand width / register file address width
`define OR1200_OPERAND_WIDTH            32
`define OR1200_REGFILE_ADDR_WIDTH       5
 
//
// Implement rotate in the ALU
//
//`define OR1200_IMPL_ALU_ROTATE
 
//
// Type of ALU compare to implement
//
//`define OR1200_IMPL_ALU_COMP1
`define OR1200_IMPL_ALU_COMP2
 
//
// Select between low-power (larger) multiplier or faster multiplier
//
//`define OR1200_LOWPWR_MULT
 
//
// Clock synchronization for RISC clk and WB divided clocks
//
// If you plan to run WB:RISC clock 1:1, you can comment these two
//
`define OR1200_CLKDIV_2_SUPPORTED
//`define OR1200_CLKDIV_4_SUPPORTED
 
//
// Type of register file RAM
//
// `define OR1200_RFRAM_TWOPORT
 
//
// Type of mem2reg aligner to implement.
//
// Once OR1200_IMPL_MEM2REG2 yielded faster
// circuit, however with today tools it will
// most probably give you slower circuit.
//
`define OR1200_IMPL_MEM2REG1
//`define OR1200_IMPL_MEM2REG2
 
//
// Simulate l.div and l.divu
//
// If commented, l.div/l.divu will produce undefined result. If enabled,
// div instructions will be simulated, but not synthesized ! OR1200
// does not have a hardware divider.
//
`define OR1200_SIM_ALU_DIV
`define OR1200_SIM_ALU_DIVU
 
//
// ALUOPs
//
`define OR1200_ALUOP_WIDTH      4
`define OR1200_ALUOP_NOP        4'd4
/* Order defined by arith insns that have two source operands both in regs
   (see binutils/include/opcode/or32.h) */
`define OR1200_ALUOP_ADD        4'd0
`define OR1200_ALUOP_ADDC       4'd1
`define OR1200_ALUOP_SUB        4'd2
`define OR1200_ALUOP_AND        4'd3
`define OR1200_ALUOP_OR         4'd4
`define OR1200_ALUOP_XOR        4'd5
`define OR1200_ALUOP_MUL        4'd6
`define OR1200_ALUOP_SHROT      4'd8
`define OR1200_ALUOP_DIV        4'd9
`define OR1200_ALUOP_DIVU       4'd10
/* Order not specifically defined. */
`define OR1200_ALUOP_IMM        4'd11
`define OR1200_ALUOP_MOVHI      4'd12
`define OR1200_ALUOP_COMP       4'd13
`define OR1200_ALUOP_MTSR       4'd14
`define OR1200_ALUOP_MFSR       4'd15
 
//
// MACOPs
//
`define OR1200_MACOP_WIDTH      2
`define OR1200_MACOP_NOP        2'b00
`define OR1200_MACOP_MAC        2'b01
`define OR1200_MACOP_MSB        2'b10
 
//
// Shift/rotate ops
//
`define OR1200_SHROTOP_WIDTH    2
`define OR1200_SHROTOP_NOP      2'd0
`define OR1200_SHROTOP_SLL      2'd0
`define OR1200_SHROTOP_SRL      2'd1
`define OR1200_SHROTOP_SRA      2'd2
`define OR1200_SHROTOP_ROR      2'd3
 
// Execution cycles per instruction
`define OR1200_MULTICYCLE_WIDTH 2
`define OR1200_ONE_CYCLE                2'd0
`define OR1200_TWO_CYCLES               2'd1
 
// Operand MUX selects
`define OR1200_SEL_WIDTH                2
`define OR1200_SEL_RF                   2'd0
`define OR1200_SEL_IMM                  2'd1
`define OR1200_SEL_EX_FORW              2'd2
`define OR1200_SEL_WB_FORW              2'd3
 
//
// BRANCHOPs
//
`define OR1200_BRANCHOP_WIDTH           3
`define OR1200_BRANCHOP_NOP             3'd0
`define OR1200_BRANCHOP_J               3'd1
`define OR1200_BRANCHOP_JR              3'd2
`define OR1200_BRANCHOP_BAL             3'd3
`define OR1200_BRANCHOP_BF              3'd4
`define OR1200_BRANCHOP_BNF             3'd5
`define OR1200_BRANCHOP_RFE             3'd6
 
//
// LSUOPs
//
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define OR1200_LSUOP_WIDTH              4
`define OR1200_LSUOP_NOP                4'b0000
`define OR1200_LSUOP_LBZ                4'b0010
`define OR1200_LSUOP_LBS                4'b0011
`define OR1200_LSUOP_LHZ                4'b0100
`define OR1200_LSUOP_LHS                4'b0101
`define OR1200_LSUOP_LWZ                4'b0110
`define OR1200_LSUOP_LWS                4'b0111
`define OR1200_LSUOP_LD         4'b0001
`define OR1200_LSUOP_SD         4'b1000
`define OR1200_LSUOP_SB         4'b1010
`define OR1200_LSUOP_SH         4'b1100
`define OR1200_LSUOP_SW         4'b1110
 
// FETCHOPs
`define OR1200_FETCHOP_WIDTH            1
`define OR1200_FETCHOP_NOP              1'b0
`define OR1200_FETCHOP_LW               1'b1
 
//
// Register File Write-Back OPs
//
// Bit 0: register file write enable
// Bits 2-1: write-back mux selects
`define OR1200_RFWBOP_WIDTH             3
`define OR1200_RFWBOP_NOP               3'b000
`define OR1200_RFWBOP_ALU               3'b001
`define OR1200_RFWBOP_LSU               3'b011
`define OR1200_RFWBOP_SPRS              3'b101
`define OR1200_RFWBOP_LR                3'b111
 
// Compare instructions
`define OR1200_COP_SFEQ       3'b000
`define OR1200_COP_SFNE       3'b001
`define OR1200_COP_SFGT       3'b010
`define OR1200_COP_SFGE       3'b011
`define OR1200_COP_SFLT       3'b100
`define OR1200_COP_SFLE       3'b101
`define OR1200_COP_X          3'b111
`define OR1200_SIGNED_COMPARE 'd3
`define OR1200_COMPOP_WIDTH     4
 
//
// TAGs for instruction bus
//
`define OR1200_ITAG_IDLE        4'h0    // idle bus
`define OR1200_ITAG_NI          4'h1    // normal insn
`define OR1200_ITAG_BE          4'hb    // Bus error exception
`define OR1200_ITAG_PE          4'hc    // Page fault exception
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
 
//
// TAGs for data bus
//
`define OR1200_DTAG_IDLE        4'h0    // idle bus
`define OR1200_DTAG_ND          4'h1    // normal data
`define OR1200_DTAG_AE          4'ha    // Alignment exception
`define OR1200_DTAG_BE          4'hb    // Bus error exception
`define OR1200_DTAG_PE          4'hc    // Page fault exception
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
 
 
//////////////////////////////////////////////
//
// ORBIS32 ISA specifics
//
 
// SHROT_OP position in machine word
`define OR1200_SHROTOP_POS              7:6
 
// ALU instructions multicycle field in machine word
`define OR1200_ALUMCYC_POS              9:8
 
//
// Instruction opcode groups (basic)
//
`define OR1200_OR32_J                 6'b000000
`define OR1200_OR32_JAL               6'b000001
`define OR1200_OR32_BNF               6'b000011
`define OR1200_OR32_BF                6'b000100
`define OR1200_OR32_NOP               6'b000101
`define OR1200_OR32_MOVHI             6'b000110
`define OR1200_OR32_XSYNC             6'b001000
`define OR1200_OR32_RFE               6'b001001
/* */
`define OR1200_OR32_JR                6'b010001
`define OR1200_OR32_JALR              6'b010010
`define OR1200_OR32_MACI              6'b010011
/* */
`define OR1200_OR32_LWZ               6'b100001
`define OR1200_OR32_LBZ               6'b100011
`define OR1200_OR32_LBS               6'b100100
`define OR1200_OR32_LHZ               6'b100101
`define OR1200_OR32_LHS               6'b100110
`define OR1200_OR32_ADDI              6'b100111
`define OR1200_OR32_ADDIC             6'b101000
`define OR1200_OR32_ANDI              6'b101001
`define OR1200_OR32_ORI               6'b101010
`define OR1200_OR32_XORI              6'b101011
`define OR1200_OR32_MULI              6'b101100
`define OR1200_OR32_MFSPR             6'b101101
`define OR1200_OR32_SH_ROTI           6'b101110
`define OR1200_OR32_SFXXI             6'b101111
/* */
`define OR1200_OR32_MTSPR             6'b110000
`define OR1200_OR32_MACMSB            6'b110001
/* */
`define OR1200_OR32_SW                6'b110101
`define OR1200_OR32_SB                6'b110110
`define OR1200_OR32_SH                6'b110111
`define OR1200_OR32_ALU               6'b111000
`define OR1200_OR32_SFXX              6'b111001
 
 
/////////////////////////////////////////////////////
//
// Exceptions
//
`define OR1200_EXCEPT_WIDTH 4
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_BREAK             `OR1200_EXCEPT_WIDTH'hd
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
 
 
/////////////////////////////////////////////////////
//
// SPR groups
//
 
// Bits that define the group
`define OR1200_SPR_GROUP_BITS   15:11
 
// Width of the group bits
`define OR1200_SPR_GROUP_WIDTH  5
 
// Bits that define offset inside the group
`define OR1200_SPR_OFS_BITS 10:0
 
// List of groups
`define OR1200_SPR_GROUP_SYS    5'd00
`define OR1200_SPR_GROUP_DMMU   5'd01
`define OR1200_SPR_GROUP_IMMU   5'd02
`define OR1200_SPR_GROUP_DC     5'd03
`define OR1200_SPR_GROUP_IC     5'd04
`define OR1200_SPR_GROUP_MAC    5'd05
`define OR1200_SPR_GROUP_DU     5'd06
`define OR1200_SPR_GROUP_PM     5'd08
`define OR1200_SPR_GROUP_PIC    5'd09
`define OR1200_SPR_GROUP_TT     5'd10
 
 
/////////////////////////////////////////////////////
//
// System group
//
 
//
// System registers
//
`define OR1200_SPR_CFGR         7'd0
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
`define OR1200_SPR_NPC          11'd16
`define OR1200_SPR_SR           11'd17
`define OR1200_SPR_PPC          11'd18
`define OR1200_SPR_EPCR         11'd32
`define OR1200_SPR_EEAR         11'd48
`define OR1200_SPR_ESR          11'd64
 
//
// SR bits
//
`define OR1200_SR_WIDTH 16
`define OR1200_SR_SM   0
`define OR1200_SR_TEE  1
`define OR1200_SR_IEE  2
`define OR1200_SR_DCE  3
`define OR1200_SR_ICE  4
`define OR1200_SR_DME  5
`define OR1200_SR_IME  6
`define OR1200_SR_LEE  7
`define OR1200_SR_CE   8
`define OR1200_SR_F    9
`define OR1200_SR_CY   10       // Unused
`define OR1200_SR_OV   11       // Unused
`define OR1200_SR_OVE  12       // Unused
`define OR1200_SR_DSX  13       // Unused
`define OR1200_SR_EPH  14
`define OR1200_SR_FO   15
`define OR1200_SR_CID  31:28    // Unimplemented
 
// Bits that define offset inside the group
`define OR1200_SPROFS_BITS 10:0
 
//
// VR, UPR and Configuration Registers
//
 
// Define if you want configuration registers implemented
`define OR1200_CFGR_IMPLEMENTED
 
// Define if you want full address decode inside SYS group
`define OR1200_SYS_FULL_DECODE
 
// Offsets of VR, UPR and CFGR registers
`define OR1200_SPRGRP_SYS_VR            4'h0
`define OR1200_SPRGRP_SYS_UPR           4'h1
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
 
// VR fields
`define OR1200_VR_REV_BITS              5:0
`define OR1200_VR_RES1_BITS             15:6
`define OR1200_VR_CFG_BITS              23:16
`define OR1200_VR_VER_BITS              31:24
 
// VR values
`define OR1200_VR_REV                   6'h00
`define OR1200_VR_RES1                  10'h000
`define OR1200_VR_CFG                   8'h00
`define OR1200_VR_VER                   8'h12
 
// UPR fields
`define OR1200_UPR_UP_BITS              0
`define OR1200_UPR_DCP_BITS             1
`define OR1200_UPR_ICP_BITS             2
`define OR1200_UPR_DMP_BITS             3
`define OR1200_UPR_IMP_BITS             4
`define OR1200_UPR_MP_BITS              5
`define OR1200_UPR_DUP_BITS             6
`define OR1200_UPR_PCUP_BITS            7
`define OR1200_UPR_PMP_BITS             8
`define OR1200_UPR_PICP_BITS            9
`define OR1200_UPR_TTP_BITS             10
`define OR1200_UPR_RES1_BITS            23:11
`define OR1200_UPR_CUP_BITS             31:24
 
// UPR values
`define OR1200_UPR_UP                   1'b1
`define OR1200_UPR_DCP                  1'b1
`define OR1200_UPR_ICP                  1'b1
`define OR1200_UPR_DMP                  1'b1
`define OR1200_UPR_IMP                  1'b1
`define OR1200_UPR_MP                   1'b1
`define OR1200_UPR_DUP                  1'b1
`define OR1200_UPR_PCUP         1'b0
`define OR1200_UPR_PMP                  1'b1
`define OR1200_UPR_PICP         1'b1
`define OR1200_UPR_TTP                  1'b1
`define OR1200_UPR_RES1         13'h0000
`define OR1200_UPR_CUP                  8'h00
 
// CPUCFGR fields
`define OR1200_CPUCFGR_NSGF_BITS        3:0
`define OR1200_CPUCFGR_HGF_BITS 4
`define OR1200_CPUCFGR_OB32S_BITS       5
`define OR1200_CPUCFGR_OB64S_BITS       6
`define OR1200_CPUCFGR_OF32S_BITS       7
`define OR1200_CPUCFGR_OF64S_BITS       8
`define OR1200_CPUCFGR_OV64S_BITS       9
`define OR1200_CPUCFGR_RES1_BITS        31:10
 
// CPUCFGR values
`define OR1200_CPUCFGR_NSGF             4'h0
`define OR1200_CPUCFGR_HGF              1'b0
`define OR1200_CPUCFGR_OB32S            1'b1
`define OR1200_CPUCFGR_OB64S            1'b0
`define OR1200_CPUCFGR_OF32S            1'b0
`define OR1200_CPUCFGR_OF64S            1'b0
`define OR1200_CPUCFGR_OV64S            1'b0
`define OR1200_CPUCFGR_RES1             22'h000000
 
// DMMUCFGR fields
`define OR1200_DMMUCFGR_NTW_BITS        1:0
`define OR1200_DMMUCFGR_NTS_BITS        4:2
`define OR1200_DMMUCFGR_NAE_BITS        7:5
`define OR1200_DMMUCFGR_CRI_BITS        8
`define OR1200_DMMUCFGR_PRI_BITS        9
`define OR1200_DMMUCFGR_TEIRI_BITS      10
`define OR1200_DMMUCFGR_HTR_BITS        11
`define OR1200_DMMUCFGR_RES1_BITS       31:12
 
// DMMUCFGR values
`define OR1200_DMMUCFGR_NTW             2'h0
`define OR1200_DMMUCFGR_NTS             3'h5
`define OR1200_DMMUCFGR_NAE             3'h0
`define OR1200_DMMUCFGR_CRI             1'b0
`define OR1200_DMMUCFGR_PRI             1'b0
`define OR1200_DMMUCFGR_TEIRI           1'b1
`define OR1200_DMMUCFGR_HTR             1'b0
`define OR1200_DMMUCFGR_RES1            20'h00000
 
// IMMUCFGR fields
`define OR1200_IMMUCFGR_NTW_BITS        1:0
`define OR1200_IMMUCFGR_NTS_BITS        4:2
`define OR1200_IMMUCFGR_NAE_BITS        7:5
`define OR1200_IMMUCFGR_CRI_BITS        8
`define OR1200_IMMUCFGR_PRI_BITS        9
`define OR1200_IMMUCFGR_TEIRI_BITS      10
`define OR1200_IMMUCFGR_HTR_BITS        11
`define OR1200_IMMUCFGR_RES1_BITS       31:12
 
// IMMUCFGR values
`define OR1200_IMMUCFGR_NTW             2'h0
`define OR1200_IMMUCFGR_NTS             3'h5
`define OR1200_IMMUCFGR_NAE             3'h0
`define OR1200_IMMUCFGR_CRI             1'b0
`define OR1200_IMMUCFGR_PRI             1'b0
`define OR1200_IMMUCFGR_TEIRI           1'b1
`define OR1200_IMMUCFGR_HTR             1'b0
`define OR1200_IMMUCFGR_RES1            20'h00000
 
// DCCFGR fields
`define OR1200_DCCFGR_NCW_BITS          2:0
`define OR1200_DCCFGR_NCS_BITS          6:3
`define OR1200_DCCFGR_CBS_BITS          7
`define OR1200_DCCFGR_CWS_BITS          8
`define OR1200_DCCFGR_CCRI_BITS 9
`define OR1200_DCCFGR_CBIRI_BITS        10
`define OR1200_DCCFGR_CBPRI_BITS        11
`define OR1200_DCCFGR_CBLRI_BITS        12
`define OR1200_DCCFGR_CBFRI_BITS        13
`define OR1200_DCCFGR_CBWBRI_BITS       14
`define OR1200_DCCFGR_RES1_BITS 31:15
 
// DCCFGR values
`define OR1200_DCCFGR_NCW               3'h0
`define OR1200_DCCFGR_NCS               4'h5
`define OR1200_DCCFGR_CBS               1'b0
`define OR1200_DCCFGR_CWS               1'b0
`define OR1200_DCCFGR_CCRI              1'b1
`define OR1200_DCCFGR_CBIRI             1'b1
`define OR1200_DCCFGR_CBPRI             1'b0
`define OR1200_DCCFGR_CBLRI             1'b0
`define OR1200_DCCFGR_CBFRI             1'b0
`define OR1200_DCCFGR_CBWBRI            1'b1
`define OR1200_DCCFGR_RES1              17'h00000
 
// ICCFGR fields
`define OR1200_ICCFGR_NCW_BITS          2:0
`define OR1200_ICCFGR_NCS_BITS          6:3
`define OR1200_ICCFGR_CBS_BITS          7
`define OR1200_ICCFGR_CWS_BITS          8
`define OR1200_ICCFGR_CCRI_BITS 9
`define OR1200_ICCFGR_CBIRI_BITS        10
`define OR1200_ICCFGR_CBPRI_BITS        11
`define OR1200_ICCFGR_CBLRI_BITS        12
`define OR1200_ICCFGR_CBFRI_BITS        13
`define OR1200_ICCFGR_CBWBRI_BITS       14
`define OR1200_ICCFGR_RES1_BITS 31:15
 
// ICCFGR values
`define OR1200_ICCFGR_NCW               3'h0
`define OR1200_ICCFGR_NCS               4'h5
`define OR1200_ICCFGR_CBS               1'b0
`define OR1200_ICCFGR_CWS               1'b0
`define OR1200_ICCFGR_CCRI              1'b1
`define OR1200_ICCFGR_CBIRI             1'b1
`define OR1200_ICCFGR_CBPRI             1'b0
`define OR1200_ICCFGR_CBLRI             1'b0
`define OR1200_ICCFGR_CBFRI             1'b0
`define OR1200_ICCFGR_CBWBRI            1'b1
`define OR1200_ICCFGR_RES1              17'h00000
 
// DCFGR fields
`define OR1200_DCFGR_NDP_BITS           2:0
`define OR1200_DCFGR_WPCI_BITS          3
`define OR1200_DCFGR_RES1_BITS          31:4
 
// DCFGR values
`define OR1200_DCFGR_NDP                3'h0
`define OR1200_DCFGR_WPCI               1'b0
`define OR1200_DCFGR_RES1               28'h0000000
 
 
/////////////////////////////////////////////////////
//
// Power Management (PM)
//
 
// Define it if you want PM implemented
`define OR1200_PM_IMPLEMENTED
 
// Bit positions inside PMR (don't change)
`define OR1200_PM_PMR_SDF 3:0
`define OR1200_PM_PMR_DME 4
`define OR1200_PM_PMR_SME 5
`define OR1200_PM_PMR_DCGE 6
`define OR1200_PM_PMR_UNUSED 31:7
 
// PMR offset inside PM group of registers
`define OR1200_PM_OFS_PMR 11'b0
 
// PM group
`define OR1200_SPRGRP_PM 5'd8
 
// Define if PMR can be read/written at any address inside PM group
`define OR1200_PM_PARTIAL_DECODING
 
// Define if reading PMR is allowed
`define OR1200_PM_READREGS
 
// Define if unused PMR bits should be zero
`define OR1200_PM_UNUSED_ZERO
 
 
/////////////////////////////////////////////////////
//
// Debug Unit (DU)
//
 
// Define it if you want DU implemented
`define OR1200_DU_IMPLEMENTED
 
// Address offsets of DU registers inside DU group
`define OR1200_DU_OFS_DMR1 5'd16
`define OR1200_DU_OFS_DMR2 5'd17
`define OR1200_DU_OFS_DSR 5'd20
`define OR1200_DU_OFS_DRR 5'd21
 
// Position of offset bits inside SPR address
`define OR1200_DUOFS_BITS 4:0
 
// Define if you want these DU registers to be implemented
`define OR1200_DU_DMR1
`define OR1200_DU_DMR2
`define OR1200_DU_DSR
`define OR1200_DU_DRR
 
// DMR1 bits
`define OR1200_DU_DMR1_ST 22
 
// DSR bits
`define OR1200_DU_DSR_WIDTH     14
`define OR1200_DU_DSR_RSTE      0
`define OR1200_DU_DSR_BUSEE     1
`define OR1200_DU_DSR_DPFE      2
`define OR1200_DU_DSR_IPFE      3
`define OR1200_DU_DSR_TTE       4
`define OR1200_DU_DSR_AE        5
`define OR1200_DU_DSR_IIE       6
`define OR1200_DU_DSR_IE        7
`define OR1200_DU_DSR_DME       8
`define OR1200_DU_DSR_IME       9
`define OR1200_DU_DSR_RE        10
`define OR1200_DU_DSR_SCE       11
`define OR1200_DU_DSR_BE        12
`define OR1200_DU_DSR_TE        13
 
// DRR bits
`define OR1200_DU_DRR_RSTE      0
`define OR1200_DU_DRR_BUSEE     1
`define OR1200_DU_DRR_DPFE      2
`define OR1200_DU_DRR_IPFE      3
`define OR1200_DU_DRR_TTE       4
`define OR1200_DU_DRR_AE        5
`define OR1200_DU_DRR_IIE       6
`define OR1200_DU_DRR_IE        7
`define OR1200_DU_DRR_DME       8
`define OR1200_DU_DRR_IME       9
`define OR1200_DU_DRR_RE        10
`define OR1200_DU_DRR_SCE       11
`define OR1200_DU_DRR_BE        12
`define OR1200_DU_DRR_TE        13
 
// Define if reading DU regs is allowed
`define OR1200_DU_READREGS
 
// Define if unused DU registers bits should be zero
`define OR1200_DU_UNUSED_ZERO
 
// DU operation commands
`define OR1200_DU_OP_READSPR    3'd4
`define OR1200_DU_OP_WRITESPR   3'd5
 
// Define if IF/LSU status is not needed by devel i/f
`define OR1200_DU_STATUS_UNIMPLEMENTED
 
/////////////////////////////////////////////////////
//
// Programmable Interrupt Controller (PIC)
//
 
// Define it if you want PIC implemented
`define OR1200_PIC_IMPLEMENTED
 
// Define number of interrupt inputs (2-31)
`define OR1200_PIC_INTS 20
 
// Address offsets of PIC registers inside PIC group
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICSR 2'd2
 
// Position of offset bits inside SPR address
`define OR1200_PICOFS_BITS 1:0
 
// Define if you want these PIC registers to be implemented
`define OR1200_PIC_PICMR
`define OR1200_PIC_PICSR
 
// Define if reading PIC registers is allowed
`define OR1200_PIC_READREGS
 
// Define if unused PIC register bits should be zero
`define OR1200_PIC_UNUSED_ZERO
 
 
/////////////////////////////////////////////////////
//
// Tick Timer (TT)
//
 
// Define it if you want TT implemented
`define OR1200_TT_IMPLEMENTED
 
// Address offsets of TT registers inside TT group
`define OR1200_TT_OFS_TTMR 1'd0
`define OR1200_TT_OFS_TTCR 1'd1
 
// Position of offset bits inside SPR group
`define OR1200_TTOFS_BITS 0
 
// Define if you want these TT registers to be implemented
`define OR1200_TT_TTMR
`define OR1200_TT_TTCR
 
// TTMR bits
`define OR1200_TT_TTMR_TP 27:0
`define OR1200_TT_TTMR_IP 28
`define OR1200_TT_TTMR_IE 29
`define OR1200_TT_TTMR_M 31:30
 
// Define if reading TT registers is allowed
`define OR1200_TT_READREGS
 
 
//////////////////////////////////////////////
//
// MAC
//
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
 
 
//////////////////////////////////////////////
//
// Data MMU (DMMU)
//
 
//
// Address that selects between TLB TR and MR
//
`define OR1200_DTLB_TM_ADDR     7
 
//
// DTLBMR fields
//
`define OR1200_DTLBMR_V_BITS    0
`define OR1200_DTLBMR_CID_BITS  4:1
`define OR1200_DTLBMR_RES_BITS  11:5
`define OR1200_DTLBMR_VPN_BITS  31:13
 
//
// DTLBTR fields
//
`define OR1200_DTLBTR_CC_BITS   0
`define OR1200_DTLBTR_CI_BITS   1
`define OR1200_DTLBTR_WBC_BITS  2
`define OR1200_DTLBTR_WOM_BITS  3
`define OR1200_DTLBTR_A_BITS    4
`define OR1200_DTLBTR_D_BITS    5
`define OR1200_DTLBTR_URE_BITS  6
`define OR1200_DTLBTR_UWE_BITS  7
`define OR1200_DTLBTR_SRE_BITS  8
`define OR1200_DTLBTR_SWE_BITS  9
`define OR1200_DTLBTR_RES_BITS  11:10
`define OR1200_DTLBTR_PPN_BITS  31:13
 
//
// DTLB configuration
//
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
 
//
// Cache inhibit while DMMU is not enabled/implemented
//
// cache inhibited 0GB-4GB              1'b1
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
// cached 0GB-4GB                       1'b0
//
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
 
 
//////////////////////////////////////////////
//
// Insn MMU (IMMU)
//
 
//
// Address that selects between TLB TR and MR
//
`define OR1200_ITLB_TM_ADDR     7
 
//
// ITLBMR fields
//
`define OR1200_ITLBMR_V_BITS    0
`define OR1200_ITLBMR_CID_BITS  4:1
`define OR1200_ITLBMR_RES_BITS  11:5
`define OR1200_ITLBMR_VPN_BITS  31:13
 
//
// ITLBTR fields
//
`define OR1200_ITLBTR_CC_BITS   0
`define OR1200_ITLBTR_CI_BITS   1
`define OR1200_ITLBTR_WBC_BITS  2
`define OR1200_ITLBTR_WOM_BITS  3
`define OR1200_ITLBTR_A_BITS    4
`define OR1200_ITLBTR_D_BITS    5
`define OR1200_ITLBTR_SXE_BITS  6
`define OR1200_ITLBTR_UXE_BITS  7
`define OR1200_ITLBTR_RES_BITS  11:8
`define OR1200_ITLBTR_PPN_BITS  31:13
 
//
// ITLB configuration
//
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
 
//
// Cache inhibit while IMMU is not enabled/implemented
// Note: all combinations that use icpu_adr_i cause async loop
//
// cache inhibited 0GB-4GB              1'b1
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
// cached 0GB-4GB                       1'b0
//
`define OR1200_IMMU_CI                  1'b0
 
 
/////////////////////////////////////////////////
//
// Insn cache (IC)
//
 
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_ICLS             4
 
//
// IC configurations
//
`ifdef OR1200_IC_1W_4KB
`define OR1200_ICSIZE                   12                      // 4096
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
`define OR1200_ICTAG_W                  21
`endif
`ifdef OR1200_IC_1W_8KB
`define OR1200_ICSIZE                   13                      // 8192
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
`define OR1200_ICTAG_W                  20
`endif
 
 
/////////////////////////////////////////////////
//
// Data cache (DC)
//
 
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_DCLS             4
 
// Define to perform store refill (potential performance penalty)
// `define OR1200_DC_STORE_REFILL
 
//
// DC configurations
//
`ifdef OR1200_DC_1W_4KB
`define OR1200_DCSIZE                   12                      // 4096
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
`define OR1200_DCTAG_W                  21
`endif
`ifdef OR1200_DC_1W_8KB
`define OR1200_DCSIZE                   13                      // 8192
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
`define OR1200_DCTAG_W                  20
`endif

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's definitions ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Parameters of the OR1200 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - add parameters that are missing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	778	lampret	`// Revision 1.11 2002/03/28 19:13:17 lampret`
48			`// Updated defines.`
49			`//`
50	776	lampret	`// Revision 1.10 2002/03/14 00:30:24 lampret`
51			`// Added alternative for critical path in DU.`
52			`//`
53	737	lampret	`// Revision 1.9 2002/03/11 01:26:26 lampret`
54			`// Fixed async loop. Changed multiplier type for ASIC.`
55			`//`
56	735	lampret	`// Revision 1.8 2002/02/11 04:33:17 lampret`
57			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
58			`//`
59	660	lampret	`// Revision 1.7 2002/02/01 19:56:54 lampret`
60			`// Fixed combinational loops.`
61			`//`
62	636	lampret	`// Revision 1.6 2002/01/19 14:10:22 lampret`
63			`// Fixed OR1200_XILINX_RAM32X1D.`
64			`//`
65	597	lampret	`// Revision 1.5 2002/01/18 07:56:00 lampret`
66			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
67			`//`
68	589	lampret	`// Revision 1.4 2002/01/14 09:44:12 lampret`
69			`// Default ASIC configuration does not sample WB inputs.`
70			`//`
71	569	lampret	`// Revision 1.3 2002/01/08 00:51:08 lampret`
72			`// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.`
73			`//`
74	536	lampret	`// Revision 1.2 2002/01/03 21:23:03 lampret`
75			`// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.`
76			`//`
77	512	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
78			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
79			`//`
80	504	lampret	`// Revision 1.20 2001/12/04 05:02:36 lampret`
81			`// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32`
82			`//`
83			`// Revision 1.19 2001/11/27 19:46:57 lampret`
84			`// Now FPGA and ASIC target are separate.`
85			`//`
86			`// Revision 1.18 2001/11/23 21:42:31 simons`
87			`// Program counter divided to PPC and NPC.`
88			`//`
89			`// Revision 1.17 2001/11/23 08:38:51 lampret`
90			`// Changed DSR/DRR behavior and exception detection.`
91			`//`
92			`// Revision 1.16 2001/11/20 21:30:38 lampret`
93			`// Added OR1200_REGISTERED_INPUTS.`
94			`//`
95			`// Revision 1.15 2001/11/19 14:29:48 simons`
96			`// Cashes disabled.`
97			`//`
98			`// Revision 1.14 2001/11/13 10:02:21 lampret`
99			`// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)`
100			`//`
101			`// Revision 1.13 2001/11/12 01:45:40 lampret`
102			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
103			`//`
104			`// Revision 1.12 2001/11/10 03:43:57 lampret`
105			`// Fixed exceptions.`
106			`//`
107			`// Revision 1.11 2001/11/02 18:57:14 lampret`
108			`// Modified virtual silicon instantiations.`
109			`//`
110			`// Revision 1.10 2001/10/21 17:57:16 lampret`
111			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
112			`//`
113			`// Revision 1.9 2001/10/19 23:28:46 lampret`
114			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
115			`//`
116			`// Revision 1.8 2001/10/14 13:12:09 lampret`
117			`// MP3 version.`
118			`//`
119			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
120			`// no message`
121			`//`
122			`// Revision 1.3 2001/08/17 08:01:19 lampret`
123			`// IC enable/disable.`
124			`//`
125			`// Revision 1.2 2001/08/13 03:36:20 lampret`
126			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
127			`//`
128			`// Revision 1.1 2001/08/09 13:39:33 lampret`
129			`// Major clean-up.`
130			`//`
131			`// Revision 1.2 2001/07/22 03:31:54 lampret`
132			`// Fixed RAM's oen bug. Cache bypass under development.`
133			`//`
134			`// Revision 1.1 2001/07/20 00:46:03 lampret`
135			`// Development version of RTL. Libraries are missing.`
136			`//`
137			`//`
138
139			`//`
140			`// Dump VCD`
141			`//`
142			//`define OR1200_VCD_DUMP
143
144			`//`
145			`// Generate debug messages during simulation`
146			`//`
147			//`define OR1200_VERBOSE
148
149	737	lampret	//`define OR1200_ASIC
150	504	lampret	`////////////////////////////////////////////////////////`
151			`//`
152			`// Typical configuration for an ASIC`
153			`//`
154			`ifdef OR1200_ASIC
155
156			`//`
157			`// Target ASIC memories`
158			`//`
159			//`define OR1200_ARTISAN_SSP
160			//`define OR1200_ARTISAN_SDP
161			//`define OR1200_ARTISAN_STP
162			`define OR1200_VIRTUALSILICON_SSP
163	778	lampret	`define OR1200_VIRTUALSILICON_STP_T1
164			//`define OR1200_VIRTUALSILICON_STP_T2
165	504	lampret
166			`//`
167			`// Do not implement Data cache`
168			`//`
169			//`define OR1200_NO_DC
170
171			`//`
172			`// Do not implement Insn cache`
173			`//`
174			//`define OR1200_NO_IC
175
176			`//`
177			`// Do not implement Data MMU`
178			`//`
179			//`define OR1200_NO_DMMU
180
181			`//`
182			`// Do not implement Insn MMU`
183			`//`
184			//`define OR1200_NO_IMMU
185
186			`//`
187			`// Register OR1200 WISHBONE outputs`
188			`// (at the moment correct operation`
189			`// only with registered outputs)`
190			`//`
191	536	lampret	`define OR1200_REGISTERED_OUTPUTS
192	504	lampret
193			`//`
194			`// Register OR1200 WISHBNE inputs`
195			`//`
196	569	lampret	//`define OR1200_REGISTERED_INPUTS
197	504	lampret
198			`//`
199			`// Select between ASIC optimized and generic multiplier`
200			`//`
201	735	lampret	//`define OR1200_ASIC_MULTP2_32X32
202			`define OR1200_GENERIC_MULTP2_32X32
203	504	lampret
204			`//`
205			`// Size/type of insn/data cache if implemented`
206			`//`
207			// `define OR1200_IC_1W_4KB
208			`define OR1200_IC_1W_8KB
209			// `define OR1200_DC_1W_4KB
210			`define OR1200_DC_1W_8KB
211
212			`else
213
214
215			`/////////////////////////////////////////////////////////`
216			`//`
217			`// Typical configuration for an FPGA`
218			`//`
219
220			`//`
221			`// Target FPGA memories`
222			`//`
223			`define OR1200_XILINX_RAMB4
224	776	lampret	//`define OR1200_XILINX_RAM32X1D
225	504	lampret
226			`//`
227			`// Do not implement Data cache`
228			`//`
229			//`define OR1200_NO_DC
230
231			`//`
232			`// Do not implement Insn cache`
233			`//`
234			//`define OR1200_NO_IC
235
236			`//`
237			`// Do not implement Data MMU`
238			`//`
239			//`define OR1200_NO_DMMU
240
241			`//`
242			`// Do not implement Insn MMU`
243			`//`
244			//`define OR1200_NO_IMMU
245
246			`//`
247			`// Register OR1200 WISHBONE outputs`
248			`// (at the moment works only with`
249			`// registered outputs)`
250			`//`
251	512	lampret	`define OR1200_REGISTERED_OUTPUTS
252	504	lampret
253			`//`
254			`// Register OR1200 WISHBONE inputs`
255			`//`
256			//`define OR1200_REGISTERED_INPUTS
257
258			`//`
259			`// Select between ASIC and generic multiplier`
260			`//`
261			//`define OR1200_ASIC_MULTP2_32X32
262			`define OR1200_GENERIC_MULTP2_32X32
263
264			`//`
265			`// Size/type of insn/data cache if implemented`
266			`// (consider available FPGA memory resources)`
267			`//`
268			`define OR1200_IC_1W_4KB
269			//`define OR1200_IC_1W_8KB
270			`define OR1200_DC_1W_4KB
271			//`define OR1200_DC_1W_8KB
272
273			`endif
274
275
276			`//////////////////////////////////////////////////////////`
277			`//`
278			`// Do not change below unless you know what you are doing`
279			`//`
280
281			`// Operand width / register file address width`
282			`define OR1200_OPERAND_WIDTH 32
283			`define OR1200_REGFILE_ADDR_WIDTH 5
284
285			`//`
286			`// Implement rotate in the ALU`
287			`//`
288			//`define OR1200_IMPL_ALU_ROTATE
289
290			`//`
291			`// Type of ALU compare to implement`
292			`//`
293			//`define OR1200_IMPL_ALU_COMP1
294			`define OR1200_IMPL_ALU_COMP2
295
296			`//`
297			`// Select between low-power (larger) multiplier or faster multiplier`
298			`//`
299	776	lampret	//`define OR1200_LOWPWR_MULT
300	504	lampret
301			`//`
302			`// Clock synchronization for RISC clk and WB divided clocks`
303			`//`
304			`// If you plan to run WB:RISC clock 1:1, you can comment these two`
305			`//`
306			`define OR1200_CLKDIV_2_SUPPORTED
307	776	lampret	//`define OR1200_CLKDIV_4_SUPPORTED
308	504	lampret
309			`//`
310			`// Type of register file RAM`
311			`//`
312			// `define OR1200_RFRAM_TWOPORT
313
314			`//`
315	776	lampret	`// Type of mem2reg aligner to implement.`
316	504	lampret	`//`
317	776	lampret	`// Once OR1200_IMPL_MEM2REG2 yielded faster`
318			`// circuit, however with today tools it will`
319			`// most probably give you slower circuit.`
320			`//`
321			`define OR1200_IMPL_MEM2REG1
322			//`define OR1200_IMPL_MEM2REG2
323	504	lampret
324			`//`
325			`// Simulate l.div and l.divu`
326			`//`
327			`// If commented, l.div/l.divu will produce undefined result. If enabled,`
328			`// div instructions will be simulated, but not synthesized ! OR1200`
329			`// does not have a hardware divider.`
330			`//`
331			`define OR1200_SIM_ALU_DIV
332			`define OR1200_SIM_ALU_DIVU
333
334			`//`
335			`// ALUOPs`
336			`//`
337			`define OR1200_ALUOP_WIDTH 4
338	636	lampret	`define OR1200_ALUOP_NOP 4'd4
339	504	lampret	`/* Order defined by arith insns that have two source operands both in regs`
340			`(see binutils/include/opcode/or32.h) */`
341			`define OR1200_ALUOP_ADD 4'd0
342			`define OR1200_ALUOP_ADDC 4'd1
343			`define OR1200_ALUOP_SUB 4'd2
344			`define OR1200_ALUOP_AND 4'd3
345	636	lampret	`define OR1200_ALUOP_OR 4'd4
346	504	lampret	`define OR1200_ALUOP_XOR 4'd5
347			`define OR1200_ALUOP_MUL 4'd6
348			`define OR1200_ALUOP_SHROT 4'd8
349			`define OR1200_ALUOP_DIV 4'd9
350			`define OR1200_ALUOP_DIVU 4'd10
351			`/* Order not specifically defined. */`
352			`define OR1200_ALUOP_IMM 4'd11
353			`define OR1200_ALUOP_MOVHI 4'd12
354			`define OR1200_ALUOP_COMP 4'd13
355			`define OR1200_ALUOP_MTSR 4'd14
356			`define OR1200_ALUOP_MFSR 4'd15
357
358			`//`
359			`// MACOPs`
360			`//`
361			`define OR1200_MACOP_WIDTH 2
362			`define OR1200_MACOP_NOP 2'b00
363			`define OR1200_MACOP_MAC 2'b01
364			`define OR1200_MACOP_MSB 2'b10
365
366			`//`
367			`// Shift/rotate ops`
368			`//`
369			`define OR1200_SHROTOP_WIDTH 2
370			`define OR1200_SHROTOP_NOP 2'd0
371			`define OR1200_SHROTOP_SLL 2'd0
372			`define OR1200_SHROTOP_SRL 2'd1
373			`define OR1200_SHROTOP_SRA 2'd2
374			`define OR1200_SHROTOP_ROR 2'd3
375
376			`// Execution cycles per instruction`
377			`define OR1200_MULTICYCLE_WIDTH 2
378			`define OR1200_ONE_CYCLE 2'd0
379			`define OR1200_TWO_CYCLES 2'd1
380
381			`// Operand MUX selects`
382			`define OR1200_SEL_WIDTH 2
383			`define OR1200_SEL_RF 2'd0
384			`define OR1200_SEL_IMM 2'd1
385			`define OR1200_SEL_EX_FORW 2'd2
386			`define OR1200_SEL_WB_FORW 2'd3
387
388			`//`
389			`// BRANCHOPs`
390			`//`
391			`define OR1200_BRANCHOP_WIDTH 3
392			`define OR1200_BRANCHOP_NOP 3'd0
393			`define OR1200_BRANCHOP_J 3'd1
394			`define OR1200_BRANCHOP_JR 3'd2
395			`define OR1200_BRANCHOP_BAL 3'd3
396			`define OR1200_BRANCHOP_BF 3'd4
397			`define OR1200_BRANCHOP_BNF 3'd5
398			`define OR1200_BRANCHOP_RFE 3'd6
399
400			`//`
401			`// LSUOPs`
402			`//`
403			`// Bit 0: sign extend`
404			`// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword`
405			`// Bit 3: 0 load, 1 store`
406			`define OR1200_LSUOP_WIDTH 4
407			`define OR1200_LSUOP_NOP 4'b0000
408			`define OR1200_LSUOP_LBZ 4'b0010
409			`define OR1200_LSUOP_LBS 4'b0011
410			`define OR1200_LSUOP_LHZ 4'b0100
411			`define OR1200_LSUOP_LHS 4'b0101
412			`define OR1200_LSUOP_LWZ 4'b0110
413			`define OR1200_LSUOP_LWS 4'b0111
414			`define OR1200_LSUOP_LD 4'b0001
415			`define OR1200_LSUOP_SD 4'b1000
416			`define OR1200_LSUOP_SB 4'b1010
417			`define OR1200_LSUOP_SH 4'b1100
418			`define OR1200_LSUOP_SW 4'b1110
419
420			`// FETCHOPs`
421			`define OR1200_FETCHOP_WIDTH 1
422			`define OR1200_FETCHOP_NOP 1'b0
423			`define OR1200_FETCHOP_LW 1'b1
424
425			`//`
426			`// Register File Write-Back OPs`
427			`//`
428			`// Bit 0: register file write enable`
429			`// Bits 2-1: write-back mux selects`
430			`define OR1200_RFWBOP_WIDTH 3
431			`define OR1200_RFWBOP_NOP 3'b000
432			`define OR1200_RFWBOP_ALU 3'b001
433			`define OR1200_RFWBOP_LSU 3'b011
434			`define OR1200_RFWBOP_SPRS 3'b101
435			`define OR1200_RFWBOP_LR 3'b111
436
437			`// Compare instructions`
438			`define OR1200_COP_SFEQ 3'b000
439			`define OR1200_COP_SFNE 3'b001
440			`define OR1200_COP_SFGT 3'b010
441			`define OR1200_COP_SFGE 3'b011
442			`define OR1200_COP_SFLT 3'b100
443			`define OR1200_COP_SFLE 3'b101
444			`define OR1200_COP_X 3'b111
445			`define OR1200_SIGNED_COMPARE 'd3
446			`define OR1200_COMPOP_WIDTH 4
447
448			`//`
449			`// TAGs for instruction bus`
450			`//`
451			`define OR1200_ITAG_IDLE 4'h0 // idle bus
452			`define OR1200_ITAG_NI 4'h1 // normal insn
453			`define OR1200_ITAG_BE 4'hb // Bus error exception
454			`define OR1200_ITAG_PE 4'hc // Page fault exception
455			`define OR1200_ITAG_TE 4'hd // TLB miss exception
456
457			`//`
458			`// TAGs for data bus`
459			`//`
460			`define OR1200_DTAG_IDLE 4'h0 // idle bus
461			`define OR1200_DTAG_ND 4'h1 // normal data
462			`define OR1200_DTAG_AE 4'ha // Alignment exception
463			`define OR1200_DTAG_BE 4'hb // Bus error exception
464			`define OR1200_DTAG_PE 4'hc // Page fault exception
465			`define OR1200_DTAG_TE 4'hd // TLB miss exception
466
467
468			`//////////////////////////////////////////////`
469			`//`
470			`// ORBIS32 ISA specifics`
471			`//`
472
473			`// SHROT_OP position in machine word`
474			`define OR1200_SHROTOP_POS 7:6
475
476			`// ALU instructions multicycle field in machine word`
477			`define OR1200_ALUMCYC_POS 9:8
478
479			`//`
480			`// Instruction opcode groups (basic)`
481			`//`
482			`define OR1200_OR32_J 6'b000000
483			`define OR1200_OR32_JAL 6'b000001
484			`define OR1200_OR32_BNF 6'b000011
485			`define OR1200_OR32_BF 6'b000100
486			`define OR1200_OR32_NOP 6'b000101
487			`define OR1200_OR32_MOVHI 6'b000110
488			`define OR1200_OR32_XSYNC 6'b001000
489			`define OR1200_OR32_RFE 6'b001001
490			`/* */`
491			`define OR1200_OR32_JR 6'b010001
492			`define OR1200_OR32_JALR 6'b010010
493			`define OR1200_OR32_MACI 6'b010011
494			`/* */`
495			`define OR1200_OR32_LWZ 6'b100001
496			`define OR1200_OR32_LBZ 6'b100011
497			`define OR1200_OR32_LBS 6'b100100
498			`define OR1200_OR32_LHZ 6'b100101
499			`define OR1200_OR32_LHS 6'b100110
500			`define OR1200_OR32_ADDI 6'b100111

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