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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's generate PC                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, interface to IC.                                        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_genpc(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o,
        icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
 
        // Internal i/f
        branch_op, except_type,
        branch_addrofs, lr_restor, flag, taken, except_start,
        binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
        genpc_freeze, flushpipe
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
output  [31:0]                   icpu_adr_o;
output                          icpu_cyc_o;
output                          icpu_stb_o;
output  [3:0]                    icpu_sel_o;
output  [3:0]                    icpu_tag_o;
input                           icpu_ack_i;
input                           icpu_rty_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
 
//
// Internal i/f
//
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
input   [31:2]                  branch_addrofs;
input   [31:0]                   lr_restor;
input                           flag;
output                          taken;
input                           except_start;
input   [31:2]                  binsn_addr;
input   [31:0]                   epcr;
input   [31:0]                   spr_dat_i;
input                           spr_pc_we;
input                           genpc_refetch;
input                           genpc_freeze;
input                           flushpipe;
 
//
// Internal wires and regs
//
reg     [31:2]                  pcreg;
reg     [31:0]                   pc;
reg                             taken;  /* Set to in case of jump or taken branch */
reg                             dslot;  /* set when fetching delay slot insn */
reg                             btarget; /* set when fetching branch target insns */
 
//
// Address of insn to be fecthed
//
assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 
//
// Control access to IC subsystem
//
assign icpu_cyc_o = !genpc_freeze;
assign icpu_stb_o = icpu_cyc_o;
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
 
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
        or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i) begin
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
                {2'b00, `OR1200_BRANCHOP_NOP}: begin
                        pc = {pcreg + 'd1, 2'b0};
                        taken = 1'b0;
                end
                {2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
// synopsys translate_on
`endif
                        pc = lr_restor;
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {binsn_addr + branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BF}:
                        if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
                                pc = {pcreg + 'd1, 2'b0};
                                taken = 1'b0;
                        end
                {2'b00, `OR1200_BRANCHOP_BNF}:
                        if (flag) begin
                                pc = {pcreg + 'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
                                taken = 1'b0;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                {2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
                        pc = epcr;
                        taken = 1'b1;
                end
                {2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
                        pc = { 20'h0_0000, except_type, 8'h00};
                        taken = 1'b1;
                end
                default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
                        pc = spr_dat_i;
                        taken = 1'b0;
                end
        endcase
end
 
//
// PC register
//
always @(posedge clk or posedge rst)
        if (rst)
                pcreg <= #1 30'd63;
        else if (spr_pc_we)
                pcreg <= #1 spr_dat_i[31:2];
        else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
                pcreg <= #1 pc[31:2];
 
//
// dslot
//
always @(posedge clk or posedge rst)
        if (rst)
                dslot <= #1 1'b0;
        else if (spr_pc_we)
                dslot <= #1 1'b0;
        else if (!icpu_rty_i)
                dslot <= #1 |branch_op;
 
//
// btarget
//
always @(posedge clk or posedge rst)
        if (rst)
                btarget <= #1 1'b0;
        else if (spr_pc_we)
                btarget <= #1 1'b0;
        else if (!icpu_rty_i)
                btarget <= #1 dslot;
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// OR1200's generate PC ////`
5			`//// ////`
6			`//// This file is part of the OpenRISC 1200 project ////`
7			`//// http://www.opencores.org/cores/or1k/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// PC, interface to IC. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
49			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
50			`//`
51	504	lampret	`// Revision 1.10 2001/11/20 18:46:15 simons`
52			`// Break point bug fixed`
53			`//`
54			`// Revision 1.9 2001/11/18 09:58:28 lampret`
55			`// Fixed some l.trap typos.`
56			`//`
57			`// Revision 1.8 2001/11/18 08:36:28 lampret`
58			`// For GDB changed single stepping and disabled trap exception.`
59			`//`
60			`// Revision 1.7 2001/10/21 17:57:16 lampret`
61			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
62			`//`
63			`// Revision 1.6 2001/10/14 13:12:09 lampret`
64			`// MP3 version.`
65			`//`
66			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
67			`// no message`
68			`//`
69			`// Revision 1.1 2001/08/09 13:39:33 lampret`
70			`// Major clean-up.`
71			`//`
72			`//`
73
74			`// synopsys translate_off`
75			`include "timescale.v"
76			`// synopsys translate_on`
77			`include "or1200_defines.v"
78
79			`module or1200_genpc(`
80			`// Clock and reset`
81			`clk, rst,`
82
83			`// External i/f to IC`
84			`icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o,`
85			`icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,`
86
87			`// Internal i/f`
88			`branch_op, except_type,`
89			`branch_addrofs, lr_restor, flag, taken, except_start,`
90	562	lampret	`binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,`
91			`genpc_freeze, flushpipe`
92	504	lampret	`);`
93
94			`//`
95			`// I/O`
96			`//`
97
98			`//`
99			`// Clock and reset`
100			`//`
101			`input clk;`
102			`input rst;`
103
104			`//`
105			`// External i/f to IC`
106			`//`
107			`output [31:0] icpu_adr_o;`
108			`output icpu_cyc_o;`
109			`output icpu_stb_o;`
110			`output [3:0] icpu_sel_o;`
111			`output [3:0] icpu_tag_o;`
112			`input icpu_ack_i;`
113			`input icpu_rty_i;`
114			`input icpu_err_i;`
115			`input [31:0] icpu_adr_i;`
116
117			`//`
118			`// Internal i/f`
119			`//`
120			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
121			input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
122			`input [31:2] branch_addrofs;`
123			`input [31:0] lr_restor;`
124			`input flag;`
125			`output taken;`
126			`input except_start;`
127			`input [31:2] binsn_addr;`
128			`input [31:0] epcr;`
129			`input [31:0] spr_dat_i;`
130			`input spr_pc_we;`
131			`input genpc_refetch;`
132	562	lampret	`input genpc_freeze;`
133			`input flushpipe;`
134	504	lampret
135			`//`
136			`// Internal wires and regs`
137			`//`
138			`reg [31:2] pcreg;`
139			`reg [31:0] pc;`
140			`reg taken; /* Set to in case of jump or taken branch */`
141			`reg dslot; /* set when fetching delay slot insn */`
142			`reg btarget; /* set when fetching branch target insns */`
143
144			`//`
145			`// Address of insn to be fecthed`
146			`//`
147	562	lampret	`assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i \| genpc_refetch) ? icpu_adr_i : pc;`
148	504	lampret
149			`//`
150			`// Control access to IC subsystem`
151			`//`
152	562	lampret	`assign icpu_cyc_o = !genpc_freeze;`
153			`assign icpu_stb_o = icpu_cyc_o;`
154	504	lampret	`assign icpu_sel_o = 4'b1111;`
155			assign icpu_tag_o = `OR1200_ITAG_NI;
156
157			`//`
158			`// Async calculation of new PC value. This value is used for addressing the IC.`
159			`//`
160			`always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type`
161			`or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i) begin`
162			`casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case`
163			{2'b00, `OR1200_BRANCHOP_NOP}: begin
164			`pc = {pcreg + 'd1, 2'b0};`
165			`taken = 1'b0;`
166			`end`
167			{2'b00, `OR1200_BRANCHOP_J}: begin
168			`ifdef OR1200_VERBOSE
169			`// synopsys translate_off`
170			`$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);`
171			`// synopsys translate_on`
172			`endif
173			`pc = {branch_addrofs, 2'b0};`
174			`taken = 1'b1;`
175			`end`
176			{2'b00, `OR1200_BRANCHOP_JR}: begin
177			`ifdef OR1200_VERBOSE
178			`// synopsys translate_off`
179			`$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);`
180			`// synopsys translate_on`
181			`endif
182			`pc = lr_restor;`
183			`taken = 1'b1;`
184			`end`
185			{2'b00, `OR1200_BRANCHOP_BAL}: begin
186			`ifdef OR1200_VERBOSE
187			`// synopsys translate_off`
188			`$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
189			`// synopsys translate_on`
190			`endif
191			`pc = {binsn_addr + branch_addrofs, 2'b0};`
192			`taken = 1'b1;`
193			`end`
194			{2'b00, `OR1200_BRANCHOP_BF}:
195			`if (flag) begin`
196			`ifdef OR1200_VERBOSE
197			`// synopsys translate_off`
198			`$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
199			`// synopsys translate_on`
200			`endif
201			`pc = {binsn_addr + branch_addrofs, 2'b0};`
202			`taken = 1'b1;`
203			`end`
204			`else begin`
205			`ifdef OR1200_VERBOSE
206			`// synopsys translate_off`
207			`$display("%t: BRANCHOP_BF: not taken", $time);`
208			`// synopsys translate_on`
209			`endif
210			`pc = {pcreg + 'd1, 2'b0};`
211			`taken = 1'b0;`
212			`end`
213			{2'b00, `OR1200_BRANCHOP_BNF}:
214			`if (flag) begin`
215			`pc = {pcreg + 'd1, 2'b0};`
216			`ifdef OR1200_VERBOSE
217			`// synopsys translate_off`
218			`$display("%t: BRANCHOP_BNF: not taken", $time);`
219			`// synopsys translate_on`
220			`endif
221			`taken = 1'b0;`
222			`end`
223			`else begin`
224			`ifdef OR1200_VERBOSE
225			`// synopsys translate_off`
226			`$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
227			`// synopsys translate_on`
228			`endif
229			`pc = {binsn_addr + branch_addrofs, 2'b0};`
230			`taken = 1'b1;`
231			`end`
232			{2'b00, `OR1200_BRANCHOP_RFE}: begin
233			`ifdef OR1200_VERBOSE
234			`// synopsys translate_off`
235			`$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);`
236			`// synopsys translate_on`
237			`endif
238			`pc = epcr;`
239			`taken = 1'b1;`
240			`end`
241			`{2'b01, 3'bxxx}: begin`
242			`ifdef OR1200_VERBOSE
243			`// synopsys translate_off`
244			`$display("Starting exception: %h.", except_type);`
245			`// synopsys translate_on`
246			`endif
247			`pc = { 20'h0_0000, except_type, 8'h00};`
248			`taken = 1'b1;`
249			`end`
250			`default: begin`
251			`ifdef OR1200_VERBOSE
252			`// synopsys translate_off`
253			`$display("l.mtspr writing into PC: %h.", spr_dat_i);`
254			`// synopsys translate_on`
255			`endif
256			`pc = spr_dat_i;`
257			`taken = 1'b0;`
258			`end`
259			`endcase`
260			`end`
261
262			`//`
263			`// PC register`
264			`//`
265			`always @(posedge clk or posedge rst)`
266			`if (rst)`
267			`pcreg <= #1 30'd63;`
268			`else if (spr_pc_we)`
269			`pcreg <= #1 spr_dat_i[31:2];`
270	562	lampret	`else if (except_start \| !genpc_freeze & !icpu_rty_i & !genpc_refetch)`
271	504	lampret	`pcreg <= #1 pc[31:2];`
272
273			`//`
274			`// dslot`
275			`//`
276			`always @(posedge clk or posedge rst)`
277			`if (rst)`
278			`dslot <= #1 1'b0;`
279			`else if (spr_pc_we)`
280			`dslot <= #1 1'b0;`
281			`else if (!icpu_rty_i)`
282			`dslot <= #1 \|branch_op;`
283
284			`//`
285			`// btarget`
286			`//`
287			`always @(posedge clk or posedge rst)`
288			`if (rst)`
289			`btarget <= #1 1'b0;`
290			`else if (spr_pc_we)`
291			`btarget <= #1 1'b0;`
292			`else if (!icpu_rty_i)`
293			`btarget <= #1 dslot;`
294
295			`endmodule`

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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Blame information for rev 562