URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Blame information for rev 1780

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/03/28 19:14:10  lampret
// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_mem2reg(addr, lsu_op, memdata, regdata);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
input   [width-1:0]              memdata;
output  [width-1:0]              regdata;
 
 
//
// In the past faster implementation of mem2reg (today probably slower)
//
`ifdef OR1200_IMPL_MEM2REG2
 
`define OR1200_M2R_BYTE0 4'b0000
`define OR1200_M2R_BYTE1 4'b0001
`define OR1200_M2R_BYTE2 4'b0010
`define OR1200_M2R_BYTE3 4'b0011
`define OR1200_M2R_EXTB0 4'b0100
`define OR1200_M2R_EXTB1 4'b0101
`define OR1200_M2R_EXTB2 4'b0110
`define OR1200_M2R_EXTB3 4'b0111
`define OR1200_M2R_ZERO  4'b0000
 
reg     [7:0]                    regdata_hh;
reg     [7:0]                    regdata_hl;
reg     [7:0]                    regdata_lh;
reg     [7:0]                    regdata_ll;
reg     [width-1:0]              aligned;
reg     [3:0]                    sel_byte0, sel_byte1,
                                sel_byte2, sel_byte3;
 
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b01x, 2'b00}:                        // lbz/lbs 0
                        sel_byte0 = `OR1200_M2R_BYTE3;  // take byte 3
                {3'b01x, 2'b01},                        // lbz/lbs 1
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte0 = `OR1200_M2R_BYTE2;  // take byte 2
                {3'b01x, 2'b10}:                        // lbz/lbs 2
                        sel_byte0 = `OR1200_M2R_BYTE1;  // take byte 1
                default:                                // all other cases
                        sel_byte0 = `OR1200_M2R_BYTE0;  // take byte 0
        endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx}:                        // lbz
                        sel_byte1 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00}:                        // lbs 0
                        sel_byte1 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte1 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10}:                        // lbs 2
                        sel_byte1 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte1 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte1 = `OR1200_M2R_BYTE3;  // take byte 3
                default:                                // all other cases
                        sel_byte1 = `OR1200_M2R_BYTE1;  // take byte 1
        endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte2 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte2 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte2 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte2 = `OR1200_M2R_BYTE2;  // take byte 2
        endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr}) // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte3 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte3 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte3 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte3 = `OR1200_M2R_BYTE3;  // take byte 3
        endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
`else
        case(sel_byte0) // synopsys full_case parallel_case
`endif
                `OR1200_M2R_BYTE0: begin
                                regdata_ll = memdata[7:0];
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_ll = memdata[15:8];
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_ll = memdata[23:16];
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_ll = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
`else
        case(sel_byte1) // synopsys full_case parallel_case
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_lh = 8'h00;
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_lh = memdata[15:8];
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_lh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_lh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_lh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_lh = {8{memdata[23]}};
                        end
                `OR1200_M2R_EXTB3: begin
                                regdata_lh = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
`else
        case(sel_byte2) // synopsys full_case parallel_case
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_hl = 8'h00;
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_hl = memdata[23:16];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hl = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hl = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hl = {8{memdata[23]}};
                        end
                `OR1200_M2R_EXTB3: begin
                                regdata_hl = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
`else
        case(sel_byte3) // synopsys full_case parallel_case
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_hh = 8'h00;
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_hh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hh = {8{memdata[23]}};
                        end
                `OR1200_M2R_EXTB3: begin
                                regdata_hh = {8{memdata[31]}};
                        end
        endcase
end
 
`else
 
//
// Straightforward implementation of mem2reg
//
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(addr) // synopsys infer_mux
`else
        case(addr) // synopsys full_case parallel_case
`endif
                2'b00:
                        aligned = memdata;
                2'b01:
                        aligned = {memdata[23:0], 8'b0};
                2'b10:
                        aligned = {memdata[15:0], 16'b0};
                2'b11:
                        aligned = {memdata[7:0], 24'b0};
        endcase
end
 
//
// Bytes
//
always @(lsu_op or aligned) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(lsu_op) // synopsys infer_mux
`else
        case(lsu_op) // synopsys parallel_case
`endif
                `OR1200_LSUOP_LBZ: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = 24'b0;
                        end
                `OR1200_LSUOP_LBS: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = {24{aligned[31]}};
                        end
                `OR1200_LSUOP_LHZ: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = 16'b0;
                        end
                `OR1200_LSUOP_LHS: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = {16{aligned[31]}};
                        end
                default:
                                regdata = aligned;
        endcase
end
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's mem2reg alignment ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Two versions of Memory to register data alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	788	lampret	`// Revision 1.3 2002/03/28 19:14:10 lampret`
48			`// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2`
49			`//`
50	777	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
51			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
52			`//`
53	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
54			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
55			`//`
56	504	lampret	`// Revision 1.9 2001/10/21 17:57:16 lampret`
57			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
58			`//`
59			`// Revision 1.8 2001/10/19 23:28:46 lampret`
60			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
61			`//`
62			`// Revision 1.7 2001/10/14 13:12:09 lampret`
63			`// MP3 version.`
64			`//`
65			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
66			`// no message`
67			`//`
68			`// Revision 1.2 2001/08/09 13:39:33 lampret`
69			`// Major clean-up.`
70			`//`
71			`// Revision 1.1 2001/07/20 00:46:03 lampret`
72			`// Development version of RTL. Libraries are missing.`
73			`//`
74			`//`
75
76			`// synopsys translate_off`
77			`include "timescale.v"
78			`// synopsys translate_on`
79			`include "or1200_defines.v"
80
81			`module or1200_mem2reg(addr, lsu_op, memdata, regdata);`
82
83			parameter width = `OR1200_OPERAND_WIDTH;
84
85			`//`
86			`// I/O`
87			`//`
88			`input [1:0] addr;`
89			input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
90			`input [width-1:0] memdata;`
91			`output [width-1:0] regdata;`
92
93
94			`//`
95	777	lampret	`// In the past faster implementation of mem2reg (today probably slower)`
96	504	lampret	`//`
97	777	lampret	`ifdef OR1200_IMPL_MEM2REG2
98	504	lampret
99	562	lampret	`define OR1200_M2R_BYTE0 4'b0000
100			`define OR1200_M2R_BYTE1 4'b0001
101			`define OR1200_M2R_BYTE2 4'b0010
102			`define OR1200_M2R_BYTE3 4'b0011
103			`define OR1200_M2R_EXTB0 4'b0100
104			`define OR1200_M2R_EXTB1 4'b0101
105			`define OR1200_M2R_EXTB2 4'b0110
106			`define OR1200_M2R_EXTB3 4'b0111
107			`define OR1200_M2R_ZERO 4'b0000
108	504	lampret
109			`reg [7:0] regdata_hh;`
110			`reg [7:0] regdata_hl;`
111			`reg [7:0] regdata_lh;`
112			`reg [7:0] regdata_ll;`
113			`reg [width-1:0] aligned;`
114	562	lampret	`reg [3:0] sel_byte0, sel_byte1,`
115	504	lampret	`sel_byte2, sel_byte3;`
116
117			`assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};`
118
119			`//`
120			`// Byte select 0`
121			`//`
122			`always @(addr or lsu_op) begin`
123	562	lampret	`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
124			`{3'b01x, 2'b00}: // lbz/lbs 0`
125			sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3
126			`{3'b01x, 2'b01}, // lbz/lbs 1`
127			`{3'b10x, 2'b00}: // lhz/lhs 0`
128			sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2
129			`{3'b01x, 2'b10}: // lbz/lbs 2`
130			sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1
131			`default: // all other cases`
132			sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0
133	504	lampret	`endcase`
134			`end`
135
136			`//`
137			`// Byte select 1`
138			`//`
139			`always @(addr or lsu_op) begin`
140	562	lampret	`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
141			`{3'b010, 2'bxx}: // lbz`
142			sel_byte1 = `OR1200_M2R_ZERO; // zero extend
143			`{3'b011, 2'b00}: // lbs 0`
144			sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3
145			`{3'b011, 2'b01}: // lbs 1`
146			sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2
147			`{3'b011, 2'b10}: // lbs 2`
148			sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1
149			`{3'b011, 2'b11}: // lbs 3`
150			sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0
151			`{3'b10x, 2'b00}: // lhz/lhs 0`
152			sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3
153			`default: // all other cases`
154			sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1
155	504	lampret	`endcase`
156			`end`
157
158			`//`
159			`// Byte select 2`
160			`//`
161			`always @(addr or lsu_op) begin`
162	562	lampret	`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
163			`{3'b010, 2'bxx}, // lbz`
164			`{3'b100, 2'bxx}: // lhz`
165			sel_byte2 = `OR1200_M2R_ZERO; // zero extend
166			`{3'b011, 2'b00}, // lbs 0`
167			`{3'b101, 2'b00}: // lhs 0`
168			sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3
169			`{3'b011, 2'b01}: // lbs 1`
170			sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2
171			`{3'b011, 2'b10}, // lbs 2`
172			`{3'b101, 2'b10}: // lhs 0`
173			sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1
174			`{3'b011, 2'b11}: // lbs 3`
175			sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0
176			`default: // all other cases`
177			sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2
178	504	lampret	`endcase`
179			`end`
180
181			`//`
182			`// Byte select 3`
183			`//`
184			`always @(addr or lsu_op) begin`
185	788	lampret	`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
186	562	lampret	`{3'b010, 2'bxx}, // lbz`
187			`{3'b100, 2'bxx}: // lhz`
188			sel_byte3 = `OR1200_M2R_ZERO; // zero extend
189			`{3'b011, 2'b00}, // lbs 0`
190			`{3'b101, 2'b00}: // lhs 0`
191			sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3
192			`{3'b011, 2'b01}: // lbs 1`
193			sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2
194			`{3'b011, 2'b10}, // lbs 2`
195			`{3'b101, 2'b10}: // lhs 0`
196			sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1
197			`{3'b011, 2'b11}: // lbs 3`
198			sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0
199			`default: // all other cases`
200			sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3
201	504	lampret	`endcase`
202			`end`
203
204			`//`
205			`// Byte 0`
206			`//`
207			`always @(sel_byte0 or memdata) begin`
208	788	lampret	`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
209	504	lampret	`case(sel_byte0) // synopsys full_case parallel_case infer_mux`
210	788	lampret	`else
211			`case(sel_byte0) // synopsys full_case parallel_case`
212			`endif
213	562	lampret	`OR1200_M2R_BYTE0: begin
214	504	lampret	`regdata_ll = memdata[7:0];`
215			`end`
216	562	lampret	`OR1200_M2R_BYTE1: begin
217	504	lampret	`regdata_ll = memdata[15:8];`
218			`end`
219	562	lampret	`OR1200_M2R_BYTE2: begin
220	504	lampret	`regdata_ll = memdata[23:16];`
221			`end`
222	562	lampret	`OR1200_M2R_BYTE3: begin
223	504	lampret	`regdata_ll = memdata[31:24];`
224			`end`
225			`endcase`
226			`end`
227
228			`//`
229			`// Byte 1`
230			`//`
231			`always @(sel_byte1 or memdata) begin`
232	788	lampret	`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
233	504	lampret	`case(sel_byte1) // synopsys full_case parallel_case infer_mux`
234	788	lampret	`else
235			`case(sel_byte1) // synopsys full_case parallel_case`
236			`endif
237	562	lampret	`OR1200_M2R_ZERO: begin
238			`regdata_lh = 8'h00;`
239	504	lampret	`end`
240	562	lampret	`OR1200_M2R_BYTE1: begin
241	504	lampret	`regdata_lh = memdata[15:8];`
242			`end`
243	562	lampret	`OR1200_M2R_BYTE3: begin
244			`regdata_lh = memdata[31:24];`
245			`end`
246			`OR1200_M2R_EXTB0: begin
247	504	lampret	`regdata_lh = {8{memdata[7]}};`
248			`end`
249	562	lampret	`OR1200_M2R_EXTB1: begin
250			`regdata_lh = {8{memdata[15]}};`
251	504	lampret	`end`
252	562	lampret	`OR1200_M2R_EXTB2: begin
253			`regdata_lh = {8{memdata[23]}};`
254			`end`
255			`OR1200_M2R_EXTB3: begin
256			`regdata_lh = {8{memdata[31]}};`
257			`end`
258	504	lampret	`endcase`
259			`end`
260
261			`//`
262			`// Byte 2`
263			`//`
264			`always @(sel_byte2 or memdata) begin`
265	788	lampret	`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
266	504	lampret	`case(sel_byte2) // synopsys full_case parallel_case infer_mux`
267	788	lampret	`else
268			`case(sel_byte2) // synopsys full_case parallel_case`
269			`endif
270	562	lampret	`OR1200_M2R_ZERO: begin
271			`regdata_hl = 8'h00;`
272	504	lampret	`end`
273	562	lampret	`OR1200_M2R_BYTE2: begin
274			`regdata_hl = memdata[23:16];`
275			`end`
276			`OR1200_M2R_EXTB0: begin
277	504	lampret	`regdata_hl = {8{memdata[7]}};`
278			`end`
279	562	lampret	`OR1200_M2R_EXTB1: begin
280	504	lampret	`regdata_hl = {8{memdata[15]}};`
281			`end`
282	562	lampret	`OR1200_M2R_EXTB2: begin
283			`regdata_hl = {8{memdata[23]}};`
284			`end`
285			`OR1200_M2R_EXTB3: begin
286			`regdata_hl = {8{memdata[31]}};`
287			`end`
288	504	lampret	`endcase`
289			`end`
290
291			`//`
292			`// Byte 3`
293			`//`
294			`always @(sel_byte3 or memdata) begin`
295	788	lampret	`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
296	504	lampret	`case(sel_byte3) // synopsys full_case parallel_case infer_mux`
297	788	lampret	`else
298			`case(sel_byte3) // synopsys full_case parallel_case`
299			`endif
300	562	lampret	`OR1200_M2R_ZERO: begin
301			`regdata_hh = 8'h00;`
302	504	lampret	`end`
303	562	lampret	`OR1200_M2R_BYTE3: begin
304			`regdata_hh = memdata[31:24];`
305			`end`
306			`OR1200_M2R_EXTB0: begin
307	504	lampret	`regdata_hh = {8{memdata[7]}};`
308			`end`
309	562	lampret	`OR1200_M2R_EXTB1: begin
310	504	lampret	`regdata_hh = {8{memdata[15]}};`
311			`end`
312	562	lampret	`OR1200_M2R_EXTB2: begin
313			`regdata_hh = {8{memdata[23]}};`
314	504	lampret	`end`
315	562	lampret	`OR1200_M2R_EXTB3: begin
316			`regdata_hh = {8{memdata[31]}};`
317			`end`
318	504	lampret	`endcase`
319			`end`
320
321			`else
322
323			`//`
324	788	lampret	`// Straightforward implementation of mem2reg`
325	504	lampret	`//`
326
327			`reg [width-1:0] regdata;`
328			`reg [width-1:0] aligned;`
329
330			`//`
331			`// Alignment`
332			`//`
333			`always @(addr or memdata) begin`
334	788	lampret	`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
335	504	lampret	`case(addr) // synopsys infer_mux`
336	788	lampret	`else
337			`case(addr) // synopsys full_case parallel_case`
338			`endif
339	504	lampret	`2'b00:`
340			`aligned = memdata;`
341			`2'b01:`
342			`aligned = {memdata[23:0], 8'b0};`
343			`2'b10:`
344			`aligned = {memdata[15:0], 16'b0};`
345			`2'b11:`
346			`aligned = {memdata[7:0], 24'b0};`
347			`endcase`
348			`end`
349
350			`//`
351			`// Bytes`
352			`//`
353			`always @(lsu_op or aligned) begin`
354	788	lampret	`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
355	504	lampret	`case(lsu_op) // synopsys infer_mux`
356	788	lampret	`else
357			`case(lsu_op) // synopsys parallel_case`
358			`endif
359	504	lampret	`OR1200_LSUOP_LBZ: begin
360			`regdata[7:0] = aligned[31:24];`
361			`regdata[31:8] = 24'b0;`
362			`end`
363			`OR1200_LSUOP_LBS: begin
364			`regdata[7:0] = aligned[31:24];`
365			`regdata[31:8] = {24{aligned[31]}};`
366			`end`
367			`OR1200_LSUOP_LHZ: begin
368			`regdata[15:0] = aligned[31:16];`
369			`regdata[31:16] = 16'b0;`
370			`end`
371			`OR1200_LSUOP_LHS: begin
372			`regdata[15:0] = aligned[31:16];`
373			`regdata[31:16] = {16{aligned[31]}};`
374			`end`
375			`default:`
376			`regdata = aligned;`
377			`endcase`
378			`end`
379
380			`endif
381
382			`endmodule`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Blame information for rev 1780