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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Blame information for rev 1780

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Top level multiplier and MAC                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Multiplier is 32x32 however multiply instructions only      ////
////  use lower 32 bits of the result. MAC is 32x32=64+64.        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.2  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:38  igorm
// no message
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_mult_mac(
        // Clock and reset
        clk, rst,
 
        // Multiplier/MAC interface
        ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
 
        // SPR interface
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Multiplier/MAC interface
//
input                           ex_freeze;
input                           id_macrc_op;
input                           macrc_op;
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [`OR1200_MACOP_WIDTH-1:0]        mac_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
output  [width-1:0]              result;
output                          mac_stall_r;
 
//
// SPR interface
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
wire    [width-1:0]              result;
reg     [2*width-1:0]            mul_prod_r;
reg     [2*width-1:0]            mac_r;
wire    [2*width-1:0]            mul_prod;
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r1;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r2;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r3;
reg                             mac_stall_r;
wire    [width-1:0]              x;
wire    [width-1:0]              y;
wire                            spr_maclo_we;
wire                            spr_machi_we;
 
//
// Combinatorial logic
//
assign result = (alu_op == `OR1200_ALUOP_MUL) ? mul_prod_r[31:0] : mac_r[59:28];
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
`ifdef OR1200_LOWPWR_MULT
assign x = (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
assign y = (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
`else
assign x = a;
assign y = b;
`endif
 
//
// Instantiation of the multiplier
//
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
        .X(x),
        .Y(y),
        .RST(rst),
        .CLK(clk),
        .P(mul_prod)
);
`else
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
        .X(x),
        .Y(y),
        .RST(rst),
        .CLK(clk),
        .P(mul_prod)
);
`endif
 
//
// Registered output from the multiplier
//
always @(posedge rst or posedge clk)
        if (rst)
                mul_prod_r <= #1 64'h0000_0000_0000_0000;
        else
                mul_prod_r <= #1 mul_prod[63:0];
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r1 <= #1 mac_op;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r2 <= #1 mac_op_r1;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r3 <= #1 mac_op_r2;
 
//
// Implementation of MAC
//
always @(posedge rst or posedge clk)
        if (rst)
                mac_r <= #1 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
        else if (spr_maclo_we)
                mac_r[31:0] <= #1 spr_dat_i;
        else if (spr_machi_we)
                mac_r[63:32] <= #1 spr_dat_i;
`endif
        else if (mac_op_r3 == `OR1200_MACOP_MAC)
                mac_r <= #1 mac_r + mul_prod_r;
        else if (mac_op_r3 == `OR1200_MACOP_MSB)
                mac_r <= #1 mac_r - mul_prod_r;
        else if (macrc_op & !ex_freeze)
                mac_r <= #1 64'h0000_0000_0000_0000;
 
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
//
always @(posedge rst or posedge clk)
        if (rst)
                mac_stall_r <= #1 1'b0;
        else
                mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op;
 
endmodule

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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Blame information for rev 1780

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Top level multiplier and MAC ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Multiplier is 32x32 however multiply instructions only ////`
10			`//// use lower 32 bits of the result. MAC is 32x32=64+64. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.3 2001/10/21 17:57:16 lampret`
49			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
50			`//`
51			`// Revision 1.2 2001/10/14 13:12:09 lampret`
52			`// MP3 version.`
53			`//`
54			`// Revision 1.1.1.1 2001/10/06 10:18:38 igorm`
55			`// no message`
56			`//`
57			`//`
58
59			`// synopsys translate_off`
60			`include "timescale.v"
61			`// synopsys translate_on`
62			`include "or1200_defines.v"
63
64			`module or1200_mult_mac(`
65			`// Clock and reset`
66			`clk, rst,`
67
68			`// Multiplier/MAC interface`
69			`ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,`
70
71			`// SPR interface`
72			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
73			`);`
74
75			parameter width = `OR1200_OPERAND_WIDTH;
76
77			`//`
78			`// I/O`
79			`//`
80
81			`//`
82			`// Clock and reset`
83			`//`
84			`input clk;`
85			`input rst;`
86
87			`//`
88			`// Multiplier/MAC interface`
89			`//`
90			`input ex_freeze;`
91			`input id_macrc_op;`
92			`input macrc_op;`
93			`input [width-1:0] a;`
94			`input [width-1:0] b;`
95			input [`OR1200_MACOP_WIDTH-1:0] mac_op;
96			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
97			`output [width-1:0] result;`
98			`output mac_stall_r;`
99
100			`//`
101			`// SPR interface`
102			`//`
103			`input spr_cs;`
104			`input spr_write;`
105			`input [31:0] spr_addr;`
106			`input [31:0] spr_dat_i;`
107			`output [31:0] spr_dat_o;`
108
109			`//`
110			`// Internal wires and regs`
111			`//`
112			`wire [width-1:0] result;`
113			`reg [2*width-1:0] mul_prod_r;`
114			`reg [2*width-1:0] mac_r;`
115			`wire [2*width-1:0] mul_prod;`
116			wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
117			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
118			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
119			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
120			`reg mac_stall_r;`
121			`wire [width-1:0] x;`
122			`wire [width-1:0] y;`
123			`wire spr_maclo_we;`
124			`wire spr_machi_we;`
125
126			`//`
127			`// Combinatorial logic`
128			`//`
129			assign result = (alu_op == `OR1200_ALUOP_MUL) ? mul_prod_r[31:0] : mac_r[59:28];
130			assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
131			assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
132			assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
133			`ifdef OR1200_LOWPWR_MULT
134			assign x = (alu_op == `OR1200_ALUOP_MUL) \| (\|mac_op) ? a : 32'h0000_0000;
135			assign y = (alu_op == `OR1200_ALUOP_MUL) \| (\|mac_op) ? b : 32'h0000_0000;
136			`else
137			`assign x = a;`
138			`assign y = b;`
139			`endif
140
141			`//`
142			`// Instantiation of the multiplier`
143			`//`
144			`ifdef OR1200_ASIC_MULTP2_32X32
145			`or1200_amultp2_32x32 or1200_amultp2_32x32(`
146			`.X(x),`
147			`.Y(y),`
148			`.RST(rst),`
149			`.CLK(clk),`
150			`.P(mul_prod)`
151			`);`
152			`else
153			`or1200_gmultp2_32x32 or1200_gmultp2_32x32(`
154			`.X(x),`
155			`.Y(y),`
156			`.RST(rst),`
157			`.CLK(clk),`
158			`.P(mul_prod)`
159			`);`
160			`endif
161
162			`//`
163			`// Registered output from the multiplier`
164			`//`
165			`always @(posedge rst or posedge clk)`
166			`if (rst)`
167			`mul_prod_r <= #1 64'h0000_0000_0000_0000;`
168			`else`
169			`mul_prod_r <= #1 mul_prod[63:0];`
170
171			`//`
172			`// Propagation of l.mac opcode`
173			`//`
174			`always @(posedge clk or posedge rst)`
175			`if (rst)`
176			mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
177			`else`
178			`mac_op_r1 <= #1 mac_op;`
179
180			`//`
181			`// Propagation of l.mac opcode`
182			`//`
183			`always @(posedge clk or posedge rst)`
184			`if (rst)`
185			mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
186			`else`
187			`mac_op_r2 <= #1 mac_op_r1;`
188
189			`//`
190			`// Propagation of l.mac opcode`
191			`//`
192			`always @(posedge clk or posedge rst)`
193			`if (rst)`
194			mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
195			`else`
196			`mac_op_r3 <= #1 mac_op_r2;`
197
198			`//`
199			`// Implementation of MAC`
200			`//`
201			`always @(posedge rst or posedge clk)`
202			`if (rst)`
203			`mac_r <= #1 64'h0000_0000_0000_0000;`
204			`ifdef OR1200_MAC_SPR_WE
205			`else if (spr_maclo_we)`
206			`mac_r[31:0] <= #1 spr_dat_i;`
207			`else if (spr_machi_we)`
208			`mac_r[63:32] <= #1 spr_dat_i;`
209			`endif
210			else if (mac_op_r3 == `OR1200_MACOP_MAC)
211			`mac_r <= #1 mac_r + mul_prod_r;`
212			else if (mac_op_r3 == `OR1200_MACOP_MSB)
213			`mac_r <= #1 mac_r - mul_prod_r;`
214			`else if (macrc_op & !ex_freeze)`
215			`mac_r <= #1 64'h0000_0000_0000_0000;`
216
217			`//`
218			`// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions`
219			`// in EX stage (e.g. inside multiplier)`
220			`//`
221			`always @(posedge rst or posedge clk)`
222			`if (rst)`
223			`mac_stall_r <= #1 1'b0;`
224			`else`
225			`mac_stall_r <= #1 (\|mac_op \| (\|mac_op_r1) \| (\|mac_op_r2)) & id_macrc_op;`
226
227			`endmodule`