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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs (Altera etc)                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_1024x32(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 32;
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] do;     // output data bus
 
//
// Internal wires and registers
//
 
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hdsp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
art_hdsp_1024x32 artisan_ssp(
`endif
        .clk(clk),
        .cen(~ce),
        .wen(~we),
        .a(addr),
        .d(di),
        .oen(~oe),
        .q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_1024x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
vs_hdsp_1024x32 vs_ssp(
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:0]),
        .EN(ce),
        .WE(we),
        .DO(do[3:0])
);
 
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:4]),
        .EN(ce),
        .WE(we),
        .DO(do[7:4])
);
 
//
// Block 2
//
RAMB4_S4 ramb4_s4_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:8]),
        .EN(ce),
        .WE(we),
        .DO(do[11:8])
);
 
//
// Block 3
//
RAMB4_S4 ramb4_s4_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:12]),
        .EN(ce),
        .WE(we),
        .DO(do[15:12])
);
 
//
// Block 4
//
RAMB4_S4 ramb4_s4_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:16]),
        .EN(ce),
        .WE(we),
        .DO(do[19:16])
);
 
//
// Block 5
//
RAMB4_S4 ramb4_s4_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:20]),
        .EN(ce),
        .WE(we),
        .DO(do[23:20])
);
 
//
// Block 6
//
RAMB4_S4 ramb4_s4_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:24]),
        .EN(ce),
        .WE(we),
        .DO(do[27:24])
);
 
//
// Block 7
//
RAMB4_S4 ramb4_s4_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:28]),
        .EN(ce),
        .WE(we),
        .DO(do[31:28])
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'bz}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we)
                do_reg <= #1 mem[addr];
        else if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x32.v] - Blame information for rev 1780

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// ////`
27			`//// To Do: ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - fix avant! two-port ram ////`
30			`//// - add additional RAMs (Altera etc) ////`
31			`//// ////`
32			`//// Author(s): ////`
33			`//// - Damjan Lampret, lampret@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65			`// Revision 1.8 2001/11/02 18:57:14 lampret`
66			`// Modified virtual silicon instantiations.`
67			`//`
68			`// Revision 1.7 2001/10/21 17:57:16 lampret`
69			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
70			`//`
71			`// Revision 1.6 2001/10/14 13:12:09 lampret`
72			`// MP3 version.`
73			`//`
74			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
75			`// no message`
76			`//`
77			`// Revision 1.1 2001/08/09 13:39:33 lampret`
78			`// Major clean-up.`
79			`//`
80			`// Revision 1.2 2001/07/30 05:38:02 lampret`
81			`// Adding empty directories required by HDL coding guidelines`
82			`//`
83			`//`
84
85			`// synopsys translate_off`
86			`include "timescale.v"
87			`// synopsys translate_on`
88			`include "or1200_defines.v"
89
90			`module or1200_spram_1024x32(`
91			`// Generic synchronous single-port RAM interface`
92			`clk, rst, ce, we, oe, addr, di, do`
93			`);`
94
95			`//`
96			`// Default address and data buses width`
97			`//`
98			`parameter aw = 10;`
99			`parameter dw = 32;`
100
101			`//`
102			`// Generic synchronous single-port RAM interface`
103			`//`
104			`input clk; // Clock`
105			`input rst; // Reset`
106			`input ce; // Chip enable input`
107			`input we; // Write enable input`
108			`input oe; // Output enable input`
109			`input [aw-1:0] addr; // address bus inputs`
110			`input [dw-1:0] di; // input data bus`
111			`output [dw-1:0] do; // output data bus`
112
113			`//`
114			`// Internal wires and registers`
115			`//`
116
117
118			`ifdef OR1200_ARTISAN_SSP
119
120			`//`
121			`// Instantiation of ASIC memory:`
122			`//`
123			`// Artisan Synchronous Single-Port RAM (ra1sh)`
124			`//`
125			`ifdef UNUSED
126			`art_hdsp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(`
127			`else
128			`art_hdsp_1024x32 artisan_ssp(`
129			`endif
130			`.clk(clk),`
131			`.cen(~ce),`
132			`.wen(~we),`
133			`.a(addr),`
134			`.d(di),`
135			`.oen(~oe),`
136			`.q(do)`
137			`);`
138
139			`else
140
141			`ifdef OR1200_AVANT_ATP
142
143			`//`
144			`// Instantiation of ASIC memory:`
145			`//`
146			`// Avant! Asynchronous Two-Port RAM`
147			`//`
148			`avant_atp avant_atp(`
149			`.web(~we),`
150			`.reb(),`
151			`.oeb(~oe),`
152			`.rcsb(),`
153			`.wcsb(),`
154			`.ra(addr),`
155			`.wa(addr),`
156			`.di(di),`
157			`.do(do)`
158			`);`
159
160			`else
161
162			`ifdef OR1200_VIRAGE_SSP
163
164			`//`
165			`// Instantiation of ASIC memory:`
166			`//`
167			`// Virage Synchronous 1-port R/W RAM`
168			`//`
169			`virage_ssp virage_ssp(`
170			`.clk(clk),`
171			`.adr(addr),`
172			`.d(di),`
173			`.we(we),`
174			`.oe(oe),`
175			`.me(ce),`
176			`.q(do)`
177			`);`
178
179			`else
180
181			`ifdef OR1200_VIRTUALSILICON_SSP
182
183			`//`
184			`// Instantiation of ASIC memory:`
185			`//`
186			`// Virtual Silicon Single-Port Synchronous SRAM`
187			`//`
188			`ifdef UNUSED
189			`vs_hdsp_1024x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
190			`else
191			`vs_hdsp_1024x32 vs_ssp(`
192			`endif
193			`.CK(clk),`
194			`.ADR(addr),`
195			`.DI(di),`
196			`.WEN(~we),`
197			`.CEN(~ce),`
198			`.OEN(~oe),`
199			`.DOUT(do)`
200			`);`
201
202			`else
203
204			`ifdef OR1200_XILINX_RAMB4
205
206			`//`
207			`// Instantiation of FPGA memory:`
208			`//`
209			`// Virtex/Spartan2`
210			`//`
211
212			`//`
213			`// Block 0`
214			`//`
215			`RAMB4_S4 ramb4_s4_0(`
216			`.CLK(clk),`
217			`.RST(rst),`
218			`.ADDR(addr),`
219			`.DI(di[3:0]),`
220			`.EN(ce),`
221			`.WE(we),`
222			`.DO(do[3:0])`
223			`);`
224
225			`//`
226			`// Block 1`
227			`//`
228			`RAMB4_S4 ramb4_s4_1(`
229			`.CLK(clk),`
230			`.RST(rst),`
231			`.ADDR(addr),`
232			`.DI(di[7:4]),`
233			`.EN(ce),`
234			`.WE(we),`
235			`.DO(do[7:4])`
236			`);`
237
238			`//`
239			`// Block 2`
240			`//`
241			`RAMB4_S4 ramb4_s4_2(`
242			`.CLK(clk),`
243			`.RST(rst),`
244			`.ADDR(addr),`
245			`.DI(di[11:8]),`
246			`.EN(ce),`
247			`.WE(we),`
248			`.DO(do[11:8])`
249			`);`
250
251			`//`
252			`// Block 3`
253			`//`
254			`RAMB4_S4 ramb4_s4_3(`
255			`.CLK(clk),`
256			`.RST(rst),`
257			`.ADDR(addr),`
258			`.DI(di[15:12]),`
259			`.EN(ce),`
260			`.WE(we),`
261			`.DO(do[15:12])`
262			`);`
263
264			`//`
265			`// Block 4`
266			`//`
267			`RAMB4_S4 ramb4_s4_4(`
268			`.CLK(clk),`
269			`.RST(rst),`
270			`.ADDR(addr),`
271			`.DI(di[19:16]),`
272			`.EN(ce),`
273			`.WE(we),`
274			`.DO(do[19:16])`
275			`);`
276
277			`//`
278			`// Block 5`
279			`//`
280			`RAMB4_S4 ramb4_s4_5(`
281			`.CLK(clk),`
282			`.RST(rst),`
283			`.ADDR(addr),`
284			`.DI(di[23:20]),`
285			`.EN(ce),`
286			`.WE(we),`
287			`.DO(do[23:20])`
288			`);`
289
290			`//`
291			`// Block 6`
292			`//`
293			`RAMB4_S4 ramb4_s4_6(`
294			`.CLK(clk),`
295			`.RST(rst),`
296			`.ADDR(addr),`
297			`.DI(di[27:24]),`
298			`.EN(ce),`
299			`.WE(we),`
300			`.DO(do[27:24])`
301			`);`
302
303			`//`
304			`// Block 7`
305			`//`
306			`RAMB4_S4 ramb4_s4_7(`
307			`.CLK(clk),`
308			`.RST(rst),`
309			`.ADDR(addr),`
310			`.DI(di[31:28]),`
311			`.EN(ce),`
312			`.WE(we),`
313			`.DO(do[31:28])`
314			`);`
315
316			`else
317
318			`//`
319			`// Generic single-port synchronous RAM model`
320			`//`
321
322			`//`
323			`// Generic RAM's registers and wires`
324			`//`
325			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
326			`reg [dw-1:0] do_reg; // RAM data output register`
327
328			`//`
329			`// Data output drivers`
330			`//`
331			`assign do = (oe) ? do_reg : {dw{1'bz}};`
332
333			`//`
334			`// RAM read and write`
335			`//`
336			`always @(posedge clk)`
337			`if (ce && !we)`
338			`do_reg <= #1 mem[addr];`
339			`else if (ce && we)`
340			`mem[addr] <= #1 di;`
341
342			`endif // !OR1200_XILINX_RAMB4_S16
343			`endif // !OR1200_VIRTUALSILICON_SSP
344			`endif // !OR1200_VIRAGE_SSP
345			`endif // !OR1200_AVANT_ATP
346			`endif // !OR1200_ARTISAN_SSP
347
348			`endmodule`