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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs (Altera etc)                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2001/11/27 21:24:04  lampret
// Changed instantiation name of VS RAMs.
//
// Revision 1.9  2001/11/27 19:45:04  lampret
// Fixed VS RAM instantiation - again.
//
// Revision 1.8  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_512x20(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
//
// Default address and data buses width
//
parameter aw = 9;
parameter dw = 20;
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] do;     // output data bus
 
//
// Internal wires and registers
//
wire    [3:0]            unconnected;
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
        .clk(clk),
        .cen(~ce),
        .wen(~we),
        .a(addr),
        .d(di),
        .oen(~oe),
        .q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S8 ramb4_s8_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:0]),
        .EN(ce),
        .WE(we),
        .DO(do[7:0])
);
 
//
// Block 1
//
RAMB4_S8 ramb4_s8_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:8]),
        .EN(ce),
        .WE(we),
        .DO(do[15:8])
);
 
//
// Block 2
//
RAMB4_S8 ramb4_s8_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI({4'b0000, di[19:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, do[19:16]})
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'bz}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we)
                do_reg <= #1 mem[addr];
        else if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_spram_512x20.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// ////`
27			`//// To Do: ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - fix avant! two-port ram ////`
30			`//// - add additional RAMs (Altera etc) ////`
31			`//// ////`
32			`//// Author(s): ////`
33			`//// - Damjan Lampret, lampret@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65			`// Revision 1.10 2001/11/27 21:24:04 lampret`
66			`// Changed instantiation name of VS RAMs.`
67			`//`
68			`// Revision 1.9 2001/11/27 19:45:04 lampret`
69			`// Fixed VS RAM instantiation - again.`
70			`//`
71			`// Revision 1.8 2001/11/23 21:42:31 simons`
72			`// Program counter divided to PPC and NPC.`
73			`//`
74			`// Revision 1.6 2001/10/21 17:57:16 lampret`
75			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
76			`//`
77			`// Revision 1.5 2001/10/14 13:12:09 lampret`
78			`// MP3 version.`
79			`//`
80			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
81			`// no message`
82			`//`
83			`// Revision 1.1 2001/08/09 13:39:33 lampret`
84			`// Major clean-up.`
85			`//`
86			`// Revision 1.2 2001/07/30 05:38:02 lampret`
87			`// Adding empty directories required by HDL coding guidelines`
88			`//`
89			`//`
90
91			`// synopsys translate_off`
92			`include "timescale.v"
93			`// synopsys translate_on`
94			`include "or1200_defines.v"
95
96			`module or1200_spram_512x20(`
97			`// Generic synchronous single-port RAM interface`
98			`clk, rst, ce, we, oe, addr, di, do`
99			`);`
100
101			`//`
102			`// Default address and data buses width`
103			`//`
104			`parameter aw = 9;`
105			`parameter dw = 20;`
106
107			`//`
108			`// Generic synchronous single-port RAM interface`
109			`//`
110			`input clk; // Clock`
111			`input rst; // Reset`
112			`input ce; // Chip enable input`
113			`input we; // Write enable input`
114			`input oe; // Output enable input`
115			`input [aw-1:0] addr; // address bus inputs`
116			`input [dw-1:0] di; // input data bus`
117			`output [dw-1:0] do; // output data bus`
118
119			`//`
120			`// Internal wires and registers`
121			`//`
122			`wire [3:0] unconnected;`
123
124			`ifdef OR1200_ARTISAN_SSP
125
126			`//`
127			`// Instantiation of ASIC memory:`
128			`//`
129			`// Artisan Synchronous Single-Port RAM (ra1sh)`
130			`//`
131			`ifdef UNUSED
132			`art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(`
133			`else
134			`art_hssp_512x20 artisan_ssp(`
135			`endif
136			`.clk(clk),`
137			`.cen(~ce),`
138			`.wen(~we),`
139			`.a(addr),`
140			`.d(di),`
141			`.oen(~oe),`
142			`.q(do)`
143			`);`
144
145			`else
146
147			`ifdef OR1200_AVANT_ATP
148
149			`//`
150			`// Instantiation of ASIC memory:`
151			`//`
152			`// Avant! Asynchronous Two-Port RAM`
153			`//`
154			`avant_atp avant_atp(`
155			`.web(~we),`
156			`.reb(),`
157			`.oeb(~oe),`
158			`.rcsb(),`
159			`.wcsb(),`
160			`.ra(addr),`
161			`.wa(addr),`
162			`.di(di),`
163			`.do(do)`
164			`);`
165
166			`else
167
168			`ifdef OR1200_VIRAGE_SSP
169
170			`//`
171			`// Instantiation of ASIC memory:`
172			`//`
173			`// Virage Synchronous 1-port R/W RAM`
174			`//`
175			`virage_ssp virage_ssp(`
176			`.clk(clk),`
177			`.adr(addr),`
178			`.d(di),`
179			`.we(we),`
180			`.oe(oe),`
181			`.me(ce),`
182			`.q(do)`
183			`);`
184
185			`else
186
187			`ifdef OR1200_VIRTUALSILICON_SSP
188
189			`//`
190			`// Instantiation of ASIC memory:`
191			`//`
192			`// Virtual Silicon Single-Port Synchronous SRAM`
193			`//`
194			`ifdef UNUSED
195			`vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(`
196			`else
197			`vs_hdsp_512x20 vs_ssp(`
198			`endif
199			`.CK(clk),`
200			`.ADR(addr),`
201			`.DI(di),`
202			`.WEN(~we),`
203			`.CEN(~ce),`
204			`.OEN(~oe),`
205			`.DOUT(do)`
206			`);`
207
208			`else
209
210			`ifdef OR1200_XILINX_RAMB4
211
212			`//`
213			`// Instantiation of FPGA memory:`
214			`//`
215			`// Virtex/Spartan2`
216			`//`
217
218			`//`
219			`// Block 0`
220			`//`
221			`RAMB4_S8 ramb4_s8_0(`
222			`.CLK(clk),`
223			`.RST(rst),`
224			`.ADDR(addr),`
225			`.DI(di[7:0]),`
226			`.EN(ce),`
227			`.WE(we),`
228			`.DO(do[7:0])`
229			`);`
230
231			`//`
232			`// Block 1`
233			`//`
234			`RAMB4_S8 ramb4_s8_1(`
235			`.CLK(clk),`
236			`.RST(rst),`
237			`.ADDR(addr),`
238			`.DI(di[15:8]),`
239			`.EN(ce),`
240			`.WE(we),`
241			`.DO(do[15:8])`
242			`);`
243
244			`//`
245			`// Block 2`
246			`//`
247			`RAMB4_S8 ramb4_s8_2(`
248			`.CLK(clk),`
249			`.RST(rst),`
250			`.ADDR(addr),`
251			`.DI({4'b0000, di[19:16]}),`
252			`.EN(ce),`
253			`.WE(we),`
254			`.DO({unconnected, do[19:16]})`
255			`);`
256
257			`else
258
259			`//`
260			`// Generic single-port synchronous RAM model`
261			`//`
262
263			`//`
264			`// Generic RAM's registers and wires`
265			`//`
266			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
267			`reg [dw-1:0] do_reg; // RAM data output register`
268
269			`//`
270			`// Data output drivers`
271			`//`
272			`assign do = (oe) ? do_reg : {dw{1'bz}};`
273
274			`//`
275			`// RAM read and write`
276			`//`
277			`always @(posedge clk)`
278			`if (ce && !we)`
279			`do_reg <= #1 mem[addr];`
280			`else if (ce && we)`
281			`mem[addr] <= #1 di;`
282
283			`endif // !OR1200_XILINX_RAMB4_S16
284			`endif // !OR1200_VIRTUALSILICON_SSP
285			`endif // !OR1200_VIRAGE_SSP
286			`endif // !OR1200_AVANT_ATP
287			`endif // !OR1200_ARTISAN_SSP
288
289			`endmodule`