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[/] [or1k/] [tags/] [rel_1/] [or1200/] [syn/] [scr/] [cons_fake_rams.inc] - Blame information for rev 1765

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Line No. Rev Author Line
1 159 lampret 
/* We "model" fake ram black boxes by setting input/output delays */
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current_design art_hssp_128x34
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create_clock clk -period CLK_PERIOD
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set_output_delay 1.12 -clock clk q
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set_input_delay 0.3 -clock clk cen
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set_input_delay 0.35 -clock clk wen
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set_input_delay 0.1 -clock clk oen
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set_input_delay 0.2 -clock clk a
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set_input_delay 0.16 -clock clk d
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current_design art_hssp_512x19
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create_clock clk -period CLK_PERIOD
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set_output_delay 1.12 -clock clk q
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set_input_delay 0.3 -clock clk cen
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set_input_delay 0.32 -clock clk wen
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set_input_delay 0.1 -clock clk oen
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set_input_delay 0.3 -clock clk a
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set_input_delay 0.17 -clock clk d
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current_design art_hssp_2048x8
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create_clock clk -period CLK_PERIOD
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set_output_delay 1.12 -clock clk q
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set_input_delay 0.35 -clock clk cen
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set_input_delay 0.37 -clock clk wen
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set_input_delay 0.1 -clock clk oen
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set_input_delay 0.35 -clock clk a
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set_input_delay 0.2 -clock clk d
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current_design art_hdsp_2048x32
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create_clock clk -period CLK_PERIOD
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set_output_delay 1.22 -clock clk q
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set_input_delay 0.35 -clock clk cen
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set_input_delay 0.41 -clock clk wen
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set_input_delay 0.1 -clock clk oen
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set_input_delay 0.34 -clock clk a
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set_input_delay 0.2 -clock clk d
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current_design TOPLEVEL

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