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/* Enable Verilog HDL preprocessor */
hdlin_enable_vpp = true
 
/* Enable power analysis */
power_preserve_rtl_hier_names = true
 
/* Set log path */
LOG_PATH = "../logs/"
 
/* Set gate-level netlist path */
GATE_PATH = "../gate/"
 
/* Set RAMS_PATH */
RAMS_PATH = "../../lib/"
 
/* Set RTL source path */
RTL_PATH = "../../rtl/"
 
/* Optimize adders */
synlib_model_map_effort = high
hlo_share_effort = medium

Line No.	Rev	Author	Line
1	159	lampret	`/* Enable Verilog HDL preprocessor */`
2			`hdlin_enable_vpp = true`
3
4			`/* Enable power analysis */`
5			`power_preserve_rtl_hier_names = true`
6
7			`/* Set log path */`
8			`LOG_PATH = "../logs/"`
9
10			`/* Set gate-level netlist path */`
11			`GATE_PATH = "../gate/"`
12
13			`/* Set RAMS_PATH */`
14			`RAMS_PATH = "../../lib/"`
15
16			`/* Set RTL source path */`
17			`RTL_PATH = "../../rtl/"`
18
19			`/* Optimize adders */`
20			`synlib_model_map_effort = high`
21			`hlo_share_effort = medium`

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