URL
https://opencores.org/ocsvn/or1k/or1k/trunk
[/] [or1k/] [tags/] [rel_1/] [or1200/] [syn/] [scr/] [tech_art_rams18.inc] - Blame information for rev 1780
Go to most recent revision |
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
159 |
lampret |
/* Set Artisan 0.18u RAMs */
|
| 2 |
|
|
|
| 3 |
|
|
search_path = search_path + { RAMS_PATH + art_hssp_2048x8/ } + { RAMS_PATH + art_hdsp_2048x32/ } \
|
| 4 |
|
|
+ { RAMS_PATH + art_hssp_512x19/ } + { RAMS_PATH + art_hssp_128x34/ } + \
|
| 5 |
|
|
{ RAMS_PATH + art_hsdp_32x32/ }
|
| 6 |
|
|
/*
|
| 7 |
|
|
add_module art_hssp_2048x8_typical_syn.lib art_hssp_2048x8_typical_syn
|
| 8 |
|
|
add_module art_hdsp_2048x32_typical_syn.lib art_hdsp_2048x32_typical_syn
|
| 9 |
|
|
add_module art_hssp_512x19_typical_syn.lib art_hssp_512x19_typical_syn
|
| 10 |
|
|
add_module -overwrite art_hssp_128x34_typical_syn.lib typical
|
| 11 |
|
|
*/
|
| 12 |
|
|
|
| 13 |
|
|
target_library = target_library + { art_hssp_2048x8_typical_syn.db } + \
|
| 14 |
|
|
{ art_hdsp_2048x32_typical_syn.db } + \
|
| 15 |
|
|
{ art_hssp_512x19_typical_syn.db } + \
|
| 16 |
|
|
{ art_hssp_128x34_typical_syn.db } + \
|
| 17 |
|
|
{ art_hsdp_32x32_typical_syn.db }
|
| 18 |
|
|
link_library = link_library + target_library
|
| 19 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.