URL
https://opencores.org/ocsvn/or1k/or1k/trunk
[/] [or1k/] [tags/] [rel_1/] [or1200/] [syn/] [scr/] [tech_vs_umc18.inc] - Blame information for rev 1780
Go to most recent revision |
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
159 |
lampret |
/* Set Virtual Silicon UMC 0.18u standard cell library */
|
| 2 |
|
|
|
| 3 |
|
|
search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ }
|
| 4 |
|
|
snps = get_unix_variable("SYNOPSYS")
|
| 5 |
|
|
synthetic_library = { \
|
| 6 |
|
|
snps + "/libraries/syn/dw01.sldb" \
|
| 7 |
|
|
snps + "/libraries/syn/dw02.sldb" \
|
| 8 |
|
|
snps + "/libraries/syn/dw03.sldb" \
|
| 9 |
|
|
snps + "/libraries/syn/dw04.sldb" \
|
| 10 |
|
|
snps + "/libraries/syn/dw05.sldb" \
|
| 11 |
|
|
snps + "/libraries/syn/dw06.sldb" \
|
| 12 |
|
|
snps + "/libraries/syn/dw07.sldb" }
|
| 13 |
|
|
target_library = { umcl18u250t2_typ.db }
|
| 14 |
|
|
link_library = target_library + synthetic_library
|
| 15 |
|
|
symbol_library = { umcl18u250t2.sdb }
|
| 16 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
