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/*
 * User defines for synthesizing data cache / DMMU unit
 *
 */
TOPLEVEL = dc
include select_tech.inc
CLK = clk
RST = rst
CLK_PERIOD = 1.8        /* 555 MHz */
MAX_AREA = 0            /* Push hard */
DO_UNGROUP = yes        /* yes, no */
DO_VERIFY = yes         /* yes, no */
RAMS = art_rams18       /* fake, art_rams18 */
 
/* Starting timestamp */
sh date
 
/* Set some basic variables related to environment */
include set_env.inc
STAGE = initial
 
/* Load libraries */
include tech_ + TECH + .inc
 
/* Load RAMs */
if (RAMS == "art_rams18") {
        include tech_art_rams18.inc
} else if (RAMS == "fake") {
        include read_fake_rams.inc
} else {
        echo "Unsupported RAMs"
        exit
}
 
/* Load HDL source files */
include read_design.inc         > LOG_PATH + read_design_ + TOPLEVEL + .log
 
/* Set design top */
current_design TOPLEVEL
 
/* Link all blocks and uniquify them */
link
transform_csa -group
uniquify
check_design                    > LOG_PATH + check_design_ + TOPLEVEL + .log
 
/* Apply constraints */
if (TECH == "vs_umc18") {
        include cons_vs_umc18.inc
} else if (TECH == "art_umc18") {
        include cons_art_umc18.inc
} else {
        echo "Error: Unsupported technology"
        exit
}
 
/* Transform arithmetics */
transform_csa -group
 
/* Lets do basic synthesis */
if (DO_UNGROUP == "yes") {
        ungroup -all -flatten
}
compile -boundary_optimization -map_effort low
 
/* Generate reports for basic synthesis */
include reports.inc
 
/* Dump gate-level from basic synthesis */
include save_design.inc
 
/* Advance to incremental synthesis, push hard */
STAGE = incremental
compile -incremental -boundary_optimization -ungroup_all -map_effort high
 
/* Optimize registers */
optimize_registers
 
/* Dump gate-level from incremental synthesis */
include save_design.inc
 
/* Generate reports for incremental synthesis */
include reports.inc
 
/* Set area constraint */
STAGE = final
set_max_area MAX_AREA
compile -incremental -boundary_optimization -auto_ungroup -map_effort medium
 
/* Dump gate-level from final synthesis */
include save_design.inc
 
/* Generate reports for final synthesis */
include reports.inc
 
/* Verify design */
if (DO_VERIFY == "yes") {
        compile -no_map -verify         > LOG_PATH + verify_ + TOPLEVEL + .log
}
 
/* Finish */
sh date
exit
 
 
 
 

Line No.	Rev	Author	Line
1	159	lampret	`/*`
2			`* User defines for synthesizing data cache / DMMU unit`
3			`*`
4			`*/`
5			`TOPLEVEL = dc`
6			`include select_tech.inc`
7			`CLK = clk`
8			`RST = rst`
9			`CLK_PERIOD = 1.8 /* 555 MHz */`
10			`MAX_AREA = 0 /* Push hard */`
11			`DO_UNGROUP = yes /* yes, no */`
12			`DO_VERIFY = yes /* yes, no */`
13			`RAMS = art_rams18 /* fake, art_rams18 */`
14
15			`/* Starting timestamp */`
16			`sh date`
17
18			`/* Set some basic variables related to environment */`
19			`include set_env.inc`
20			`STAGE = initial`
21
22			`/* Load libraries */`
23			`include tech_ + TECH + .inc`
24
25			`/* Load RAMs */`
26			`if (RAMS == "art_rams18") {`
27			`include tech_art_rams18.inc`
28			`} else if (RAMS == "fake") {`
29			`include read_fake_rams.inc`
30			`} else {`
31			`echo "Unsupported RAMs"`
32			`exit`
33			`}`
34
35			`/* Load HDL source files */`
36			`include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log`
37
38			`/* Set design top */`
39			`current_design TOPLEVEL`
40
41			`/* Link all blocks and uniquify them */`
42			`link`
43			`transform_csa -group`
44			`uniquify`
45			`check_design > LOG_PATH + check_design_ + TOPLEVEL + .log`
46
47			`/* Apply constraints */`
48			`if (TECH == "vs_umc18") {`
49			`include cons_vs_umc18.inc`
50			`} else if (TECH == "art_umc18") {`
51			`include cons_art_umc18.inc`
52			`} else {`
53			`echo "Error: Unsupported technology"`
54			`exit`
55			`}`
56
57			`/* Transform arithmetics */`
58			`transform_csa -group`
59
60			`/* Lets do basic synthesis */`
61			`if (DO_UNGROUP == "yes") {`
62			`ungroup -all -flatten`
63			`}`
64			`compile -boundary_optimization -map_effort low`
65
66			`/* Generate reports for basic synthesis */`
67			`include reports.inc`
68
69			`/* Dump gate-level from basic synthesis */`
70			`include save_design.inc`
71
72			`/* Advance to incremental synthesis, push hard */`
73			`STAGE = incremental`
74			`compile -incremental -boundary_optimization -ungroup_all -map_effort high`
75
76			`/* Optimize registers */`
77			`optimize_registers`
78
79			`/* Dump gate-level from incremental synthesis */`
80			`include save_design.inc`
81
82			`/* Generate reports for incremental synthesis */`
83			`include reports.inc`
84
85			`/* Set area constraint */`
86			`STAGE = final`
87			`set_max_area MAX_AREA`
88			`compile -incremental -boundary_optimization -auto_ungroup -map_effort medium`
89
90			`/* Dump gate-level from final synthesis */`
91			`include save_design.inc`
92
93			`/* Generate reports for final synthesis */`
94			`include reports.inc`
95
96			`/* Verify design */`
97			`if (DO_VERIFY == "yes") {`
98			`compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log`
99			`}`
100
101			`/* Finish */`
102			`sh date`
103			`exit`
104
105
106
107

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[/] [or1k/] [tags/] [rel_1/] [or1200/] [syn/] [scr/] [top_dc.scr] - Blame information for rev 1780