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/*
 * User defines for synthesizing multiplier
 *
 */
TOPLEVEL = multp2_32x32
include select_tech.inc
CLK = CLK
RST = rst
CLK_PERIOD = 2          /* 500 MHz */
MAX_AREA = 0            /* Push hard */
DO_UNGROUP = yes        /* yes, no */
DO_VERIFY = no          /* yes, no */
 
/* Starting timestamp */
sh date
 
/* Set some basic variables related to environment */
include set_env.inc
STAGE = initial
 
/* Load libraries */
include tech_ + TECH + .inc
 
/* Load HDL source files */
include read_design.inc         > LOG_PATH + read_design_ + TOPLEVEL + .log
 
/* Set design top */
current_design TOPLEVEL
 
/* Link all blocks and uniquify them */
link
uniquify
check_design                    > LOG_PATH + check_design_ + TOPLEVEL + .log
 
/* Apply constraints */
if (TECH == "vs_umc18") {
        include cons_vs_umc18.inc
} else if (TECH == "art_umc18") {
        include cons_art_umc18.inc
} else {
        echo "Error: Unsupported technology"
        exit
}
 
/* Transform arithmetics */
transform_csa -group
 
/* Lets do basic synthesis */
if (DO_UNGROUP == "yes") {
        ungroup -all -flatten
}
compile -boundary_optimization -map_effort low
 
/* Generate reports for basic synthesis */
include reports.inc
 
/* Dump gate-level from basic synthesis */
include save_design.inc
 
/* Advance to incremental synthesis, push hard */
STAGE = incremental
compile -incremental -boundary_optimization -auto_ungroup -map_effort medium
 
/* Optimize registers */
optimize_registers
 
/* Dump gate-level from incremental synthesis */
include save_design.inc
 
/* Generate reports for incremental synthesis */
include reports.inc
 
/* Set area constraint */
STAGE = final
set_max_area MAX_AREA
compile -incremental -boundary_optimization -auto_ungroup -map_effort medium
 
/* Dump gate-level from final synthesis */
include save_design.inc
 
/* Generate reports for final synthesis */
include reports.inc
 
/* Verify design */
if (DO_VERIFY == "yes") {
        compile -no_map -verify         > LOG_PATH + verify_ + TOPLEVEL + .log
}
 
/* Finish */
sh date
exit
 
 
 
 

Line No.	Rev	Author	Line
1	159	lampret	`/*`
2			`* User defines for synthesizing multiplier`
3			`*`
4			`*/`
5			`TOPLEVEL = multp2_32x32`
6			`include select_tech.inc`
7			`CLK = CLK`
8			`RST = rst`
9			`CLK_PERIOD = 2 /* 500 MHz */`
10			`MAX_AREA = 0 /* Push hard */`
11			`DO_UNGROUP = yes /* yes, no */`
12			`DO_VERIFY = no /* yes, no */`
13
14			`/* Starting timestamp */`
15			`sh date`
16
17			`/* Set some basic variables related to environment */`
18			`include set_env.inc`
19			`STAGE = initial`
20
21			`/* Load libraries */`
22			`include tech_ + TECH + .inc`
23
24			`/* Load HDL source files */`
25			`include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log`
26
27			`/* Set design top */`
28			`current_design TOPLEVEL`
29
30			`/* Link all blocks and uniquify them */`
31			`link`
32			`uniquify`
33			`check_design > LOG_PATH + check_design_ + TOPLEVEL + .log`
34
35			`/* Apply constraints */`
36			`if (TECH == "vs_umc18") {`
37			`include cons_vs_umc18.inc`
38			`} else if (TECH == "art_umc18") {`
39			`include cons_art_umc18.inc`
40			`} else {`
41			`echo "Error: Unsupported technology"`
42			`exit`
43			`}`
44
45			`/* Transform arithmetics */`
46			`transform_csa -group`
47
48			`/* Lets do basic synthesis */`
49			`if (DO_UNGROUP == "yes") {`
50			`ungroup -all -flatten`
51			`}`
52			`compile -boundary_optimization -map_effort low`
53
54			`/* Generate reports for basic synthesis */`
55			`include reports.inc`
56
57			`/* Dump gate-level from basic synthesis */`
58			`include save_design.inc`
59
60			`/* Advance to incremental synthesis, push hard */`
61			`STAGE = incremental`
62			`compile -incremental -boundary_optimization -auto_ungroup -map_effort medium`
63
64			`/* Optimize registers */`
65			`optimize_registers`
66
67			`/* Dump gate-level from incremental synthesis */`
68			`include save_design.inc`
69
70			`/* Generate reports for incremental synthesis */`
71			`include reports.inc`
72
73			`/* Set area constraint */`
74			`STAGE = final`
75			`set_max_area MAX_AREA`
76			`compile -incremental -boundary_optimization -auto_ungroup -map_effort medium`
77
78			`/* Dump gate-level from final synthesis */`
79			`include save_design.inc`
80
81			`/* Generate reports for final synthesis */`
82			`include reports.inc`
83
84			`/* Verify design */`
85			`if (DO_VERIFY == "yes") {`
86			`compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log`
87			`}`
88
89			`/* Finish */`
90			`sh date`
91			`exit`
92
93
94
95

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