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[/] [or1k/] [tags/] [rel_10/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's IC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of Instruction cache data rams                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_ic_ram(
        // Clock and reset
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
        // Internal i/f
        addr, en, we, datain, dataout
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                           scanb_rst,
                                scanb_si,
                                scanb_en,
                                scanb_clk;
output                          scanb_so;
`endif
 
`ifdef OR1200_NO_IC
 
//
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
 
`else
 
//
// Instantiation of IC RAM block
//
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si),
        .scanb_so(scanb_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[0]),
        .oe(1'b1),
        .addr(addr),
        .di(datain),
        .do(dataout)
);
 
`endif
 
endmodule
 

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's IC RAMs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of Instruction cache data rams ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	1063	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50	504	lampret	`// Revision 1.9 2001/10/21 17:57:16 lampret`
51			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
52			`//`
53			`// Revision 1.8 2001/10/14 13:12:09 lampret`
54			`// MP3 version.`
55			`//`
56			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
57			`// no message`
58			`//`
59			`// Revision 1.3 2001/08/09 13:39:33 lampret`
60			`// Major clean-up.`
61			`//`
62			`// Revision 1.2 2001/07/22 03:31:54 lampret`
63			`// Fixed RAM's oen bug. Cache bypass under development.`
64			`//`
65			`// Revision 1.1 2001/07/20 00:46:03 lampret`
66			`// Development version of RTL. Libraries are missing.`
67			`//`
68			`//`
69
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "or1200_defines.v"
74
75			`module or1200_ic_ram(`
76			`// Clock and reset`
77			`clk, rst,`
78
79	1063	lampret	`ifdef OR1200_BIST
80			`// RAM BIST`
81			`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`
82			`endif
83
84	504	lampret	`// Internal i/f`
85			`addr, en, we, datain, dataout`
86			`);`
87
88			parameter dw = `OR1200_OPERAND_WIDTH;
89			parameter aw = `OR1200_ICINDX;
90
91			`//`
92			`// I/O`
93			`//`
94			`input clk;`
95			`input rst;`
96			`input [aw-1:0] addr;`
97			`input en;`
98			`input [3:0] we;`
99			`input [dw-1:0] datain;`
100			`output [dw-1:0] dataout;`
101
102	1063	lampret	`ifdef OR1200_BIST
103			`//`
104			`// RAM BIST`
105			`//`
106			`input scanb_rst,`
107			`scanb_si,`
108			`scanb_en,`
109			`scanb_clk;`
110			`output scanb_so;`
111			`endif
112
113	504	lampret	`ifdef OR1200_NO_IC
114
115			`//`
116			`// Insn cache not implemented`
117			`//`
118			`assign dataout = {dw{1'b0}};`
119	1063	lampret	`ifdef OR1200_BIST
120			`assign scanb_so = scanb_si;`
121			`endif
122	504	lampret
123			`else
124
125			`//`
126			`// Instantiation of IC RAM block`
127			`//`
128			`ifdef OR1200_IC_1W_4KB
129			`or1200_spram_1024x32 ic_ram0(`
130			`endif
131			`ifdef OR1200_IC_1W_8KB
132			`or1200_spram_2048x32 ic_ram0(`
133			`endif
134	1063	lampret	`ifdef OR1200_BIST
135			`// RAM BIST`
136			`.scanb_rst(scanb_rst),`
137			`.scanb_si(scanb_si),`
138			`.scanb_so(scanb_so),`
139			`.scanb_en(scanb_en),`
140			`.scanb_clk(scanb_clk),`
141			`endif
142	504	lampret	`.clk(clk),`
143			`.rst(rst),`
144			`.ce(en),`
145			`.we(we[0]),`
146			`.oe(1'b1),`
147			`.addr(addr),`
148			`.di(datain),`
149			`.do(dataout)`
150			`);`
151
152			`endif
153
154			`endmodule`
155

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[/] [or1k/] [tags/] [rel_10/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Blame information for rev 1765