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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2003/08/11 13:32:19  simons
// BIST interface added for Artisan memory instances.
//
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_1024x32(
`ifdef OR1200_BIST
        // RAM BIST
        scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 32;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                   scanb_rst,
                        scanb_si,
                        scanb_en,
                        scanb_clk;
output                  scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] do;     // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x32_bist artisan_ssp(
`else
art_hssp_1024x32 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si),
        .scanb_so(scanb_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_1024x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x32_bist vs_ssp(
`else
vs_hdsp_1024x32 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si),
        .scanb_so(scanb_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:0]),
        .EN(ce),
        .WE(we),
        .DO(do[3:0])
);
 
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:4]),
        .EN(ce),
        .WE(we),
        .DO(do[7:4])
);
 
//
// Block 2
//
RAMB4_S4 ramb4_s4_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:8]),
        .EN(ce),
        .WE(we),
        .DO(do[11:8])
);
 
//
// Block 3
//
RAMB4_S4 ramb4_s4_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:12]),
        .EN(ce),
        .WE(we),
        .DO(do[15:12])
);
 
//
// Block 4
//
RAMB4_S4 ramb4_s4_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:16]),
        .EN(ce),
        .WE(we),
        .DO(do[19:16])
);
 
//
// Block 5
//
RAMB4_S4 ramb4_s4_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:20]),
        .EN(ce),
        .WE(we),
        .DO(do[23:20])
);
 
//
// Block 6
//
RAMB4_S4 ramb4_s4_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:24]),
        .EN(ce),
        .WE(we),
        .DO(do[27:24])
);
 
//
// Block 7
//
RAMB4_S4 ramb4_s4_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:28]),
        .EN(ce),
        .WE(we),
        .DO(do[31:28])
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(do)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'b0}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we)
                do_reg <= #1 mem[addr];
        else if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26	1129	lampret	`//// - Altera LPM ////`
27	504	lampret	`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31	1129	lampret	`//// - add additional RAMs ////`
32	504	lampret	`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66	1184	simons	`// Revision 1.4 2003/08/11 13:32:19 simons`
67			`// BIST interface added for Artisan memory instances.`
68			`//`
69	1179	simons	`// Revision 1.3 2003/04/07 01:19:07 lampret`
70			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
71			`//`
72	1129	lampret	`// Revision 1.2 2002/10/17 20:04:40 lampret`
73			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
74			`//`
75	1063	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
76			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
77			`//`
78	504	lampret	`// Revision 1.8 2001/11/02 18:57:14 lampret`
79			`// Modified virtual silicon instantiations.`
80			`//`
81			`// Revision 1.7 2001/10/21 17:57:16 lampret`
82			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
83			`//`
84			`// Revision 1.6 2001/10/14 13:12:09 lampret`
85			`// MP3 version.`
86			`//`
87			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
88			`// no message`
89			`//`
90			`// Revision 1.1 2001/08/09 13:39:33 lampret`
91			`// Major clean-up.`
92			`//`
93			`// Revision 1.2 2001/07/30 05:38:02 lampret`
94			`// Adding empty directories required by HDL coding guidelines`
95			`//`
96			`//`
97
98			`// synopsys translate_off`
99			`include "timescale.v"
100			`// synopsys translate_on`
101			`include "or1200_defines.v"
102
103			`module or1200_spram_1024x32(`
104	1063	lampret	`ifdef OR1200_BIST
105			`// RAM BIST`
106			`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`
107			`endif
108	504	lampret	`// Generic synchronous single-port RAM interface`
109			`clk, rst, ce, we, oe, addr, di, do`
110			`);`
111
112			`//`
113			`// Default address and data buses width`
114			`//`
115			`parameter aw = 10;`
116			`parameter dw = 32;`
117
118	1063	lampret	`ifdef OR1200_BIST
119	504	lampret	`//`
120	1063	lampret	`// RAM BIST`
121			`//`
122			`input scanb_rst,`
123			`scanb_si,`
124			`scanb_en,`
125			`scanb_clk;`
126			`output scanb_so;`
127			`endif
128
129			`//`
130	504	lampret	`// Generic synchronous single-port RAM interface`
131			`//`
132			`input clk; // Clock`
133			`input rst; // Reset`
134			`input ce; // Chip enable input`
135			`input we; // Write enable input`
136			`input oe; // Output enable input`
137			`input [aw-1:0] addr; // address bus inputs`
138			`input [dw-1:0] di; // input data bus`
139			`output [dw-1:0] do; // output data bus`
140
141			`//`
142			`// Internal wires and registers`
143			`//`
144
145	1184	simons	`ifdef OR1200_ARTISAN_SSP
146			`else
147			`ifdef OR1200_VIRTUALSILICON_SSP
148			`else
149	1063	lampret	`ifdef OR1200_BIST
150			`assign scanb_so = scanb_si;`
151			`endif
152	1184	simons	`endif
153			`endif
154	504	lampret
155			`ifdef OR1200_ARTISAN_SSP
156
157			`//`
158			`// Instantiation of ASIC memory:`
159			`//`
160			`// Artisan Synchronous Single-Port RAM (ra1sh)`
161			`//`
162			`ifdef UNUSED
163	1179	simons	`art_hssp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(`
164	504	lampret	`else
165	1179	simons	`ifdef OR1200_BIST
166			`art_hssp_1024x32_bist artisan_ssp(`
167			`else
168			`art_hssp_1024x32 artisan_ssp(`
169	504	lampret	`endif
170	1179	simons	`endif
171			`ifdef OR1200_BIST
172			`// RAM BIST`
173			`.scanb_rst(scanb_rst),`
174			`.scanb_si(scanb_si),`
175			`.scanb_so(scanb_so),`
176			`.scanb_en(scanb_en),`
177			`.scanb_clk(scanb_clk),`
178			`endif
179			`.CLK(clk),`
180			`.CEN(~ce),`
181			`.WEN(~we),`
182			`.A(addr),`
183			`.D(di),`
184			`.OEN(~oe),`
185			`.Q(do)`
186	504	lampret	`);`
187
188			`else
189
190			`ifdef OR1200_AVANT_ATP
191
192			`//`
193			`// Instantiation of ASIC memory:`
194			`//`
195			`// Avant! Asynchronous Two-Port RAM`
196			`//`
197			`avant_atp avant_atp(`
198			`.web(~we),`
199			`.reb(),`
200			`.oeb(~oe),`
201			`.rcsb(),`
202			`.wcsb(),`
203			`.ra(addr),`
204			`.wa(addr),`
205			`.di(di),`
206			`.do(do)`
207			`);`
208
209			`else
210
211			`ifdef OR1200_VIRAGE_SSP
212
213			`//`
214			`// Instantiation of ASIC memory:`
215			`//`
216			`// Virage Synchronous 1-port R/W RAM`
217			`//`
218			`virage_ssp virage_ssp(`
219			`.clk(clk),`
220			`.adr(addr),`
221			`.d(di),`
222			`.we(we),`
223			`.oe(oe),`
224			`.me(ce),`
225			`.q(do)`
226			`);`
227
228			`else
229
230			`ifdef OR1200_VIRTUALSILICON_SSP
231
232			`//`
233			`// Instantiation of ASIC memory:`
234			`//`
235			`// Virtual Silicon Single-Port Synchronous SRAM`
236			`//`
237			`ifdef UNUSED
238			`vs_hdsp_1024x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
239			`else
240	1063	lampret	`ifdef OR1200_BIST
241			`vs_hdsp_1024x32_bist vs_ssp(`
242			`else
243	504	lampret	`vs_hdsp_1024x32 vs_ssp(`
244			`endif
245	1063	lampret	`endif
246			`ifdef OR1200_BIST
247			`// RAM BIST`
248			`.scanb_rst(scanb_rst),`
249			`.scanb_si(scanb_si),`
250			`.scanb_so(scanb_so),`
251			`.scanb_en(scanb_en),`
252			`.scanb_clk(scanb_clk),`
253			`endif
254	504	lampret	`.CK(clk),`
255			`.ADR(addr),`
256			`.DI(di),`
257			`.WEN(~we),`
258			`.CEN(~ce),`
259			`.OEN(~oe),`
260			`.DOUT(do)`
261			`);`
262
263			`else
264
265			`ifdef OR1200_XILINX_RAMB4
266
267			`//`
268			`// Instantiation of FPGA memory:`
269			`//`
270			`// Virtex/Spartan2`
271			`//`
272
273			`//`
274			`// Block 0`
275			`//`
276			`RAMB4_S4 ramb4_s4_0(`
277			`.CLK(clk),`
278			`.RST(rst),`
279			`.ADDR(addr),`
280			`.DI(di[3:0]),`
281			`.EN(ce),`
282			`.WE(we),`
283			`.DO(do[3:0])`
284			`);`
285
286			`//`
287			`// Block 1`
288			`//`
289			`RAMB4_S4 ramb4_s4_1(`
290			`.CLK(clk),`
291			`.RST(rst),`
292			`.ADDR(addr),`
293			`.DI(di[7:4]),`
294			`.EN(ce),`
295			`.WE(we),`
296			`.DO(do[7:4])`
297			`);`
298
299			`//`
300			`// Block 2`
301			`//`
302			`RAMB4_S4 ramb4_s4_2(`
303			`.CLK(clk),`
304			`.RST(rst),`
305			`.ADDR(addr),`
306			`.DI(di[11:8]),`
307			`.EN(ce),`
308			`.WE(we),`
309			`.DO(do[11:8])`
310			`);`
311
312			`//`
313			`// Block 3`
314			`//`
315			`RAMB4_S4 ramb4_s4_3(`
316			`.CLK(clk),`
317			`.RST(rst),`
318			`.ADDR(addr),`
319			`.DI(di[15:12]),`
320			`.EN(ce),`
321			`.WE(we),`
322			`.DO(do[15:12])`
323			`);`
324
325			`//`
326			`// Block 4`
327			`//`
328			`RAMB4_S4 ramb4_s4_4(`
329			`.CLK(clk),`
330			`.RST(rst),`
331			`.ADDR(addr),`
332			`.DI(di[19:16]),`
333			`.EN(ce),`
334			`.WE(we),`
335			`.DO(do[19:16])`
336			`);`
337
338			`//`
339			`// Block 5`
340			`//`
341			`RAMB4_S4 ramb4_s4_5(`
342			`.CLK(clk),`
343			`.RST(rst),`
344			`.ADDR(addr),`
345			`.DI(di[23:20]),`
346			`.EN(ce),`
347			`.WE(we),`
348			`.DO(do[23:20])`
349			`);`
350
351			`//`
352			`// Block 6`
353			`//`
354			`RAMB4_S4 ramb4_s4_6(`
355			`.CLK(clk),`
356			`.RST(rst),`
357			`.ADDR(addr),`
358			`.DI(di[27:24]),`
359			`.EN(ce),`
360			`.WE(we),`
361			`.DO(do[27:24])`
362			`);`
363
364			`//`
365			`// Block 7`
366			`//`
367			`RAMB4_S4 ramb4_s4_7(`
368			`.CLK(clk),`
369			`.RST(rst),`
370			`.ADDR(addr),`
371			`.DI(di[31:28]),`
372			`.EN(ce),`
373			`.WE(we),`
374			`.DO(do[31:28])`
375			`);`
376
377			`else
378
379	1129	lampret	`ifdef OR1200_ALTERA_LPM
380
381	504	lampret	`//`
382	1129	lampret	`// Instantiation of FPGA memory:`
383			`//`
384			`// Altera LPM`
385			`//`
386			`// Added By Jamil Khatib`
387			`//`
388
389			`wire wr;`
390
391			`assign wr = ce & we;`
392
393			`initial $display("Using Altera LPM.");`
394
395			`lpm_ram_dq lpm_ram_dq_component (`
396			`.address(addr),`
397			`.inclock(clk),`
398			`.outclock(clk),`
399			`.data(di),`
400			`.we(wr),`
401			`.q(do)`
402			`);`
403
404			`defparam lpm_ram_dq_component.lpm_width = dw,`
405			`lpm_ram_dq_component.lpm_widthad = aw,`
406			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
407			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
408			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
409			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
410			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
411
412			`else
413
414			`//`
415	504	lampret	`// Generic single-port synchronous RAM model`
416			`//`
417
418			`//`
419			`// Generic RAM's registers and wires`
420			`//`
421			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
422			`reg [dw-1:0] do_reg; // RAM data output register`
423
424			`//`
425			`// Data output drivers`
426			`//`
427	1129	lampret	`assign do = (oe) ? do_reg : {dw{1'b0}};`
428	504	lampret
429			`//`
430			`// RAM read and write`
431			`//`
432			`always @(posedge clk)`
433			`if (ce && !we)`
434			`do_reg <= #1 mem[addr];`
435			`else if (ce && we)`
436			`mem[addr] <= #1 di;`
437
438	1129	lampret	`endif // !OR1200_ALTERA_LPM
439	504	lampret	`endif // !OR1200_XILINX_RAMB4_S16
440			`endif // !OR1200_VIRTUALSILICON_SSP
441			`endif // !OR1200_VIRAGE_SSP
442			`endif // !OR1200_AVANT_ATP
443			`endif // !OR1200_ARTISAN_SSP
444
445			`endmodule`

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