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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Double-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common double-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  double-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (Altera, VS etc)                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/01/19 14:10:22  lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.2  2002/01/15 06:12:22  lampret
// Fixed module name when compiling with OR1200_XILINX_RAM32X1D
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/05 14:48:00  lampret
// Added missing endif
//
// Revision 1.9  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.8  2001/10/22 19:39:56  lampret
// Fixed parameters in generic sprams.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dpram_32x32(
        // Generic synchronous double-port RAM interface
        clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
        clk_b, rst_b, ce_b, we_b, addr_b, di_b
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
 
//
// Generic synchronous double-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SDP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef UNUSED
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
`else
art_hsdp_32x32 artisan_sdp(
`endif
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(1'b1),
        .aa(addr_a),
        .da(32'h00000000),
        .oena(~oe_a),
        .qb(),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(1'b1)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_STP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
        .QA(do_a),
        .QB(),
 
        .ADRA(addr_a),
        .DA(32'h00000000),
        .WEA(1'b0),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(addr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(1'b1),
        .MEB(ce_b),
        .CLKB(clk_b)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_STP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Two-port R/W SRAM
//
`ifdef UNUSED
vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
vs_hdtp_32x32 vs_ssp(
`endif
        .RCK(clk_a),
        .REN(~ce_a),
        .OEN(~oe_a),
        .RADR(addr_a),
        .DI(di_b),
        .WCK(clk_b),
        .WEN(~ce_b),
        .WADR(addr_b),
        .DOUT(do_a)
);
 
`else
 
`ifdef OR1200_XILINX_RAM32X1D
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
reg     [4:0]    addr_a_r;
 
always @(posedge clk_a or posedge rst_a)
        if (rst_a)
                addr_a_r <= #1 5'b00000;
        else if (ce_a)
                addr_a_r <= #1 addr_a;
 
//
// Block 0
//
or1200_xcv_ram32x8d xcv_ram32x8d_0 (
        .DPO(do_a[7:0]),
        .SPO(),
        .A(addr_b),
        .D(di_b[7:0]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 1
//
or1200_xcv_ram32x8d xcv_ram32x8d_1 (
        .DPO(do_a[15:8]),
        .SPO(),
        .A(addr_b),
        .D(di_b[15:8]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
 
//
// Block 2
//
or1200_xcv_ram32x8d xcv_ram32x8d_2 (
        .DPO(do_a[23:16]),
        .SPO(),
        .A(addr_b),
        .D(di_b[23:16]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 3
//
or1200_xcv_ram32x8d xcv_ram32x8d_3 (
        .DPO(do_a[31:24]),
        .SPO(),
        .A(addr_b),
        .D(di_b[31:24]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
`else
 
//
// Generic double-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do_a = (oe_a) ? do_reg : {dw{1'bz}};
 
//
// RAM read
//
always @(posedge clk_a)
        if (ce_a)
                do_reg <= #1 mem[addr_a];
 
//
// RAM write
//
always @(posedge clk_b)
        if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
 
`endif  // !OR1200_XILINX_RAMB4_S16_S16
`endif  // !OR1200_XILINX_RAM32X1D
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_STP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SDP
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Double-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common double-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// double-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25			`//// ////`
26			`//// To Do: ////`
27			`//// - fix Avant! ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - add additional RAMs (Altera, VS etc) ////`
30			`//// ////`
31			`//// Author(s): ////`
32			`//// - Damjan Lampret, lampret@opencores.org ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35			`//// ////`
36			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
37			`//// ////`
38			`//// This source file may be used and distributed without ////`
39			`//// restriction provided that this copyright statement is not ////`
40			`//// removed from the file and that any derivative work contains ////`
41			`//// the original copyright notice and the associated disclaimer. ////`
42			`//// ////`
43			`//// This source file is free software; you can redistribute it ////`
44			`//// and/or modify it under the terms of the GNU Lesser General ////`
45			`//// Public License as published by the Free Software Foundation; ////`
46			`//// either version 2.1 of the License, or (at your option) any ////`
47			`//// later version. ////`
48			`//// ////`
49			`//// This source is distributed in the hope that it will be ////`
50			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
51			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
52			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
53			`//// details. ////`
54			`//// ////`
55			`//// You should have received a copy of the GNU Lesser General ////`
56			`//// Public License along with this source; if not, download it ////`
57			`//// from http://www.opencores.org/lgpl.shtml ////`
58			`//// ////`
59			`//////////////////////////////////////////////////////////////////////`
60			`//`
61			`// CVS Revision History`
62			`//`
63			`// $Log: not supported by cvs2svn $`
64	610	lampret	`// Revision 1.3 2002/01/19 14:10:22 lampret`
65			`// Fixed OR1200_XILINX_RAM32X1D.`
66			`//`
67	597	lampret	`// Revision 1.2 2002/01/15 06:12:22 lampret`
68			`// Fixed module name when compiling with OR1200_XILINX_RAM32X1D`
69			`//`
70	573	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
71			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
72			`//`
73	504	lampret	`// Revision 1.10 2001/11/05 14:48:00 lampret`
74			`// Added missing endif`
75			`//`
76			`// Revision 1.9 2001/11/02 18:57:14 lampret`
77			`// Modified virtual silicon instantiations.`
78			`//`
79			`// Revision 1.8 2001/10/22 19:39:56 lampret`
80			`// Fixed parameters in generic sprams.`
81			`//`
82			`// Revision 1.7 2001/10/21 17:57:16 lampret`
83			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
84			`//`
85			`// Revision 1.6 2001/10/14 13:12:09 lampret`
86			`// MP3 version.`
87			`//`
88			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
89			`// no message`
90			`//`
91			`// Revision 1.1 2001/08/09 13:39:33 lampret`
92			`// Major clean-up.`
93			`//`
94			`// Revision 1.2 2001/07/30 05:38:02 lampret`
95			`// Adding empty directories required by HDL coding guidelines`
96			`//`
97			`//`
98
99			`// synopsys translate_off`
100			`include "timescale.v"
101			`// synopsys translate_on`
102			`include "or1200_defines.v"
103
104			`module or1200_dpram_32x32(`
105			`// Generic synchronous double-port RAM interface`
106			`clk_a, rst_a, ce_a, oe_a, addr_a, do_a,`
107			`clk_b, rst_b, ce_b, we_b, addr_b, di_b`
108			`);`
109
110			`//`
111			`// Default address and data buses width`
112			`//`
113			`parameter aw = 5;`
114			`parameter dw = 32;`
115
116			`//`
117			`// Generic synchronous double-port RAM interface`
118			`//`
119			`input clk_a; // Clock`
120			`input rst_a; // Reset`
121			`input ce_a; // Chip enable input`
122			`input oe_a; // Output enable input`
123			`input [aw-1:0] addr_a; // address bus inputs`
124			`output [dw-1:0] do_a; // output data bus`
125			`input clk_b; // Clock`
126			`input rst_b; // Reset`
127			`input ce_b; // Chip enable input`
128			`input we_b; // Write enable input`
129			`input [aw-1:0] addr_b; // address bus inputs`
130			`input [dw-1:0] di_b; // input data bus`
131
132			`//`
133			`// Internal wires and registers`
134			`//`
135
136			`ifdef OR1200_ARTISAN_SDP
137
138			`//`
139			`// Instantiation of ASIC memory:`
140			`//`
141			`// Artisan Synchronous Double-Port RAM (ra2sh)`
142			`//`
143			`ifdef UNUSED
144			`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`
145			`else
146			`art_hsdp_32x32 artisan_sdp(`
147			`endif
148			`.qa(do_a),`
149			`.clka(clk_a),`
150			`.cena(~ce_a),`
151			`.wena(1'b1),`
152			`.aa(addr_a),`
153			`.da(32'h00000000),`
154			`.oena(~oe_a),`
155			`.qb(),`
156			`.clkb(clk_b),`
157			`.cenb(~ce_b),`
158			`.wenb(~we_b),`
159			`.ab(addr_b),`
160			`.db(di_b),`
161			`.oenb(1'b1)`
162			`);`
163
164			`else
165
166			`ifdef OR1200_AVANT_ATP
167
168			`//`
169			`// Instantiation of ASIC memory:`
170			`//`
171			`// Avant! Asynchronous Two-Port RAM`
172			`//`
173			`avant_atp avant_atp(`
174			`.web(~we),`
175			`.reb(),`
176			`.oeb(~oe),`
177			`.rcsb(),`
178			`.wcsb(),`
179			`.ra(addr),`
180			`.wa(addr),`
181			`.di(di),`
182			`.do(do)`
183			`);`
184
185			`else
186
187			`ifdef OR1200_VIRAGE_STP
188
189			`//`
190			`// Instantiation of ASIC memory:`
191			`//`
192			`// Virage Synchronous 2-port R/W RAM`
193			`//`
194			`virage_stp virage_stp(`
195			`.QA(do_a),`
196			`.QB(),`
197
198			`.ADRA(addr_a),`
199			`.DA(32'h00000000),`
200			`.WEA(1'b0),`
201			`.OEA(oe_a),`
202			`.MEA(ce_a),`
203			`.CLKA(clk_a),`
204
205			`.ADRB(addr_b),`
206			`.DB(di_b),`
207			`.WEB(we_b),`
208			`.OEB(1'b1),`
209			`.MEB(ce_b),`
210			`.CLKB(clk_b)`
211			`);`
212
213			`else
214
215			`ifdef OR1200_VIRTUALSILICON_STP
216
217			`//`
218			`// Instantiation of ASIC memory:`
219			`//`
220			`// Virtual Silicon Two-port R/W SRAM`
221			`//`
222			`ifdef UNUSED
223			`vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
224			`else
225			`vs_hdtp_32x32 vs_ssp(`
226			`endif
227			`.RCK(clk_a),`
228			`.REN(~ce_a),`
229			`.OEN(~oe_a),`
230			`.RADR(addr_a),`
231			`.DI(di_b),`
232			`.WCK(clk_b),`
233			`.WEN(~ce_b),`
234			`.WADR(addr_b),`
235			`.DOUT(do_a)`
236			`);`
237
238			`else
239
240			`ifdef OR1200_XILINX_RAM32X1D
241
242			`//`
243			`// Instantiation of FPGA memory:`
244			`//`
245			`// Virtex/Spartan2`
246			`//`
247
248	597	lampret	`reg [4:0] addr_a_r;`
249
250			`always @(posedge clk_a or posedge rst_a)`
251	610	lampret	`if (rst_a)`
252			`addr_a_r <= #1 5'b00000;`
253			`else if (ce_a)`
254	597	lampret	`addr_a_r <= #1 addr_a;`
255
256	504	lampret	`//`
257			`// Block 0`
258			`//`
259	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_0 (`
260	504	lampret	`.DPO(do_a[7:0]),`
261			`.SPO(),`
262			`.A(addr_b),`
263			`.D(di_b[7:0]),`
264	597	lampret	`.DPRA(addr_a_r),`
265	504	lampret	`.WCLK(clk_b),`
266			`.WE(we_b)`
267			`);`
268
269			`//`
270			`// Block 1`
271			`//`
272	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_1 (`
273	504	lampret	`.DPO(do_a[15:8]),`
274			`.SPO(),`
275			`.A(addr_b),`
276			`.D(di_b[15:8]),`
277	597	lampret	`.DPRA(addr_a_r),`
278	504	lampret	`.WCLK(clk_b),`
279			`.WE(we_b)`
280			`);`
281
282
283			`//`
284			`// Block 2`
285			`//`
286	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_2 (`
287	504	lampret	`.DPO(do_a[23:16]),`
288			`.SPO(),`
289			`.A(addr_b),`
290			`.D(di_b[23:16]),`
291	597	lampret	`.DPRA(addr_a_r),`
292	504	lampret	`.WCLK(clk_b),`
293			`.WE(we_b)`
294			`);`
295
296			`//`
297			`// Block 3`
298			`//`
299	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_3 (`
300	504	lampret	`.DPO(do_a[31:24]),`
301			`.SPO(),`
302			`.A(addr_b),`
303			`.D(di_b[31:24]),`
304	597	lampret	`.DPRA(addr_a_r),`
305	504	lampret	`.WCLK(clk_b),`
306			`.WE(we_b)`
307			`);`
308
309			`else
310
311			`ifdef OR1200_XILINX_RAMB4
312
313			`//`
314			`// Instantiation of FPGA memory:`
315			`//`
316			`// Virtex/Spartan2`
317			`//`
318
319			`//`
320			`// Block 0`
321			`//`
322			`RAMB4_S16_S16 ramb4_s16_0(`
323			`.CLKA(clk_a),`
324			`.RSTA(rst_a),`
325			`.ADDRA({3'b000, addr_a}),`
326			`.DIA(16'h0000),`
327			`.ENA(ce_a),`
328			`.WEA(1'b0),`
329			`.DOA(do_a[15:0]),`
330
331			`.CLKB(clk_b),`
332			`.RSTB(rst_b),`
333			`.ADDRB({3'b000, addr_b}),`
334			`.DIB(di_b[15:0]),`
335			`.ENB(ce_b),`
336			`.WEB(we_b),`
337			`.DOB()`
338			`);`
339
340			`//`
341			`// Block 1`
342			`//`
343			`RAMB4_S16_S16 ramb4_s16_1(`
344			`.CLKA(clk_a),`
345			`.RSTA(rst_a),`
346			`.ADDRA({3'b000, addr_a}),`
347			`.DIA(16'h0000),`
348			`.ENA(ce_a),`
349			`.WEA(1'b0),`
350			`.DOA(do_a[31:16]),`
351
352			`.CLKB(clk_b),`
353			`.RSTB(rst_b),`
354			`.ADDRB({3'b000, addr_b}),`
355			`.DIB(di_b[31:16]),`
356			`.ENB(ce_b),`
357			`.WEB(we_b),`
358			`.DOB()`
359			`);`
360
361			`else
362
363			`//`
364			`// Generic double-port synchronous RAM model`
365			`//`
366
367			`//`
368			`// Generic RAM's registers and wires`
369			`//`
370			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
371			`reg [dw-1:0] do_reg; // RAM data output register`
372
373			`//`
374			`// Data output drivers`
375			`//`
376			`assign do_a = (oe_a) ? do_reg : {dw{1'bz}};`
377
378			`//`
379			`// RAM read`
380			`//`
381			`always @(posedge clk_a)`
382			`if (ce_a)`
383			`do_reg <= #1 mem[addr_a];`
384
385			`//`
386			`// RAM write`
387			`//`
388			`always @(posedge clk_b)`
389			`if (ce_b && we_b)`
390			`mem[addr_b] <= #1 di_b;`
391
392			`endif // !OR1200_XILINX_RAMB4_S16_S16
393			`endif // !OR1200_XILINX_RAM32X1D
394			`endif // !OR1200_VIRTUALSILICON_SSP
395			`endif // !OR1200_VIRAGE_STP
396			`endif // !OR1200_AVANT_ATP
397			`endif // !OR1200_ARTISAN_SDP
398
399			`endmodule`

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