URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] [or1200_except.v] - Blame information for rev 562

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Exception logic                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Handles all OR1K exceptions inside CPU block.               ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.15  2001/11/27 23:13:11  lampret
// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
//
// Revision 1.14  2001/11/23 08:38:51  lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.13  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.12  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.11  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.10  2001/11/13 10:02:21  lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.9  2001/11/10 03:43:57  lampret
// Fixed exceptions.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_EXCEPTFSM_WIDTH 3
`define OR1200_EXCEPTFSM_IDLE   `OR1200_EXCEPTFSM_WIDTH'd0
`define OR1200_EXCEPTFSM_FLU1   `OR1200_EXCEPTFSM_WIDTH'd1
`define OR1200_EXCEPTFSM_FLU2   `OR1200_EXCEPTFSM_WIDTH'd2
`define OR1200_EXCEPTFSM_FLU3   `OR1200_EXCEPTFSM_WIDTH'd3
`define OR1200_EXCEPTFSM_FLU4   `OR1200_EXCEPTFSM_WIDTH'd4
`define OR1200_EXCEPTFSM_FLU5   `OR1200_EXCEPTFSM_WIDTH'd5
 
//
// Exception recognition and sequencing
//
 
module or1200_except(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
        sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,
        branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
        if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
        except_started, except_stop,
        wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
        esr, sr, lsu_addr
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           sig_ibuserr;
input                           sig_dbuserr;
input                           sig_illegal;
input                           sig_align;
input                           sig_range;
input                           sig_dtlbmiss;
input                           sig_dmmufault;
input                           sig_inthigh;
input                           sig_syscall;
input                           sig_trap;
input                           sig_itlbmiss;
input                           sig_immufault;
input                           sig_intlow;
input                           branch_taken;
input                           id_freeze;
input                           ex_freeze;
input                           wb_freeze;
input                           if_stall;
input   [31:0]                   if_pc;
output  [31:2]                  lr_sav;
input   [31:0]                   datain;
input   [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
input                           epcr_we;
input                           eear_we;
input                           esr_we;
input                           pc_we;
output  [31:0]                   epcr;
output  [31:0]                   eear;
output  [`OR1200_SR_WIDTH-1:0]           esr;
input   [`OR1200_SR_WIDTH-1:0]           sr;
input   [31:0]                   lsu_addr;
output                          flushpipe;
output                          extend_flush;
output  [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
output                          except_start;
output                          except_started;
output  [12:0]                   except_stop;
output  [31:0]                   wb_pc;
output  [31:0]                   ex_pc;
output  [31:0]                   id_pc;
 
//
// Internal regs and wires
//
reg     [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
reg     [31:0]                   id_pc;
reg     [31:0]                   ex_pc;
reg     [31:0]                   wb_pc;
reg     [31:0]                   epcr;
reg     [31:0]                   eear;
reg     [`OR1200_SR_WIDTH-1:0]           esr;
reg     [3:0]                    id_exceptflags;
reg     [3:0]                    ex_exceptflags;
reg     [`OR1200_EXCEPTFSM_WIDTH-1:0]    state;
reg                             extend_flush;
reg                             extend_flush_last;
reg                             ex_dslot;
reg                             delayed1_ex_dslot;
reg                             delayed2_ex_dslot;
wire                            except_started;
wire    [12:0]                   except_trig;
wire                            except_flushpipe;
reg     [2:0]                    delayed_eir;
wire                            inthigh_pending;
wire                            intlow_pending;
 
//
// Simple combinatorial logic
//
assign except_started = extend_flush & except_start;
assign lr_sav = ex_pc[31:2];
//assign except_start = (except_type != `OR1200_EXCEPT_NONE);  // damjan
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
 
//
// Order defines exception detection priority
//
assign except_trig = {
                        inthigh_pending         & ~du_dsr[`OR1200_DU_DSR_HPINTE],
                        ex_exceptflags[2]       & ~du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[1]       & ~du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[3]       & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_illegal             & ~du_dsr[`OR1200_DU_DSR_IIE],
                        sig_align               & ~du_dsr[`OR1200_DU_DSR_AE],
                        sig_dtlbmiss            & ~du_dsr[`OR1200_DU_DSR_DME],
                        sig_dmmufault           & ~du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dbuserr             & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        ex_exceptflags[0]        & ~du_dsr[`OR1200_DU_DSR_LPINTE],
                        sig_syscall             & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
                        sig_trap                & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
                        sig_range               & ~du_dsr[`OR1200_DU_DSR_RE]
                };
assign except_stop = {
                        inthigh_pending         & du_dsr[`OR1200_DU_DSR_HPINTE],
                        ex_exceptflags[2]       & du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[1]       & du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[3]       & du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_illegal             & du_dsr[`OR1200_DU_DSR_IIE],
                        sig_align               & du_dsr[`OR1200_DU_DSR_AE],
                        sig_dtlbmiss            & du_dsr[`OR1200_DU_DSR_DME],
                        sig_dmmufault           & du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dbuserr             & du_dsr[`OR1200_DU_DSR_BUSEE],
                        ex_exceptflags[0]        & du_dsr[`OR1200_DU_DSR_LPINTE],
                        sig_syscall             & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
                        sig_trap                & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
                        sig_range               & du_dsr[`OR1200_DU_DSR_RE]
                };
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                id_pc <= #1 32'd0;
                id_exceptflags <= #1 4'b0000;
        end
        else if (flushpipe) begin
                id_pc <= #1 32'h0000_0000;
                id_exceptflags <= #1 4'b0000;
        end
        else if (!id_freeze) begin
                id_pc <= #1 if_pc;
                id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };
        end
end
 
//
// delayed_eir
//
// SR[EIR] should not enable interrupts right away
// when it is restored with l.rfe. Instead delayed_eir
// together with SR[EIR] enables interrupts once
// pipeline is again ready.
//
always @(posedge rst or posedge clk)
        if (rst)
                delayed_eir <= #1 3'b000;
        else if (!sr[`OR1200_SR_EIR])
                delayed_eir <= #1 3'b000;
        else
                delayed_eir <= #1 {delayed_eir[1:0], 1'b1};
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 32'd0;
                ex_exceptflags <= #1 4'b0000;
                delayed1_ex_dslot <= #1 1'b0;
                delayed2_ex_dslot <= #1 1'b0;
        end
        else if (flushpipe) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 32'h0000_0000;
                ex_exceptflags <= #1 4'b0000;
                delayed1_ex_dslot <= #1 1'b0;
                delayed2_ex_dslot <= #1 1'b0;
        end
        else if (!ex_freeze & id_freeze) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 id_pc;
                ex_exceptflags <= #1 4'b0000;
                delayed1_ex_dslot <= #1 ex_dslot;
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
        end
        else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: ex_pc <= %h", $time, id_pc);
// synopsys translate_on
`endif
                ex_dslot <= #1 branch_taken;
                ex_pc <= #1 id_pc;
                ex_exceptflags <= #1 id_exceptflags;
                delayed1_ex_dslot <= #1 ex_dslot;
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
        end
end
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                wb_pc <= #1 32'd0;
        end
        else if (!wb_freeze) begin
                wb_pc <= #1 ex_pc;
        end
end
 
//
// Flush pipeline
//
assign flushpipe = except_flushpipe | pc_we | extend_flush;
 
//
// We have started execution of exception handler:
//  1. Asserted for 3 clock cycles
//  2. Don't execute any instruction that is still in pipeline and is not part of exception handler
//
assign except_flushpipe = |except_trig & !state;
 
//
// Exception FSM that sequences execution of exception handler
//
// except_type signals which exception handler we start fetching in:
//  1. Asserted in next clock cycle after exception is recognized
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_EXCEPTFSM_IDLE;
                except_type <= #1 `OR1200_EXCEPT_NONE;
                extend_flush <= #1 1'b0;
                epcr <= #1 32'b0;
                eear <= #1 32'b0;
                esr <= #1 `OR1200_SR_WIDTH'b010;
                extend_flush_last <= #1 1'b0;
        end
        else begin
                case (state)    // synopsys full_case parallel_case
                        `OR1200_EXCEPTFSM_IDLE:
                                if (except_flushpipe) begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        extend_flush <= #1 1'b1;
                                        if (ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during first delay slot instruction.");
// synopsys translate_on
`endif
                                        end
                                        else if (delayed1_ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during second (NOP) delay slot instruction.");
// synopsys translate_on
`endif
                                        end
                                        else if (delayed2_ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");
// synopsys translate_on
`endif
                                        end
                                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during normal (no delay slot) instruction.");
// synopsys translate_on
`endif
                                        end
 
                                        esr <= #1 sr;
                                        casex (except_trig)
                                                13'b1_xxxx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_HPINT;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_1xxx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_01xx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_IPF;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_001x_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0001_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_1xxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ALIGN;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_01xx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_001x_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_DPF;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_0001_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_0000_1xxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_LPINT;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_01xx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_RANGE;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_001x: begin
                                                        except_type <= #1 `OR1200_EXCEPT_TRAP;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_0001: begin
                                                        except_type <= #1 `OR1200_EXCEPT_SYSCALL;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                default:
                                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                        endcase
                                end
                                else if (pc_we) begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        extend_flush <= #1 1'b1;
                                end
                                else begin
                                        if (epcr_we)
                                                epcr <= #1 datain;
                                        if (eear_we)
                                                eear <= #1 datain;
                                        if (esr_we)
                                                esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
                                end
                        `OR1200_EXCEPTFSM_FLU1:
//                              if (!if_stall & !id_freeze)
                                        state <= #1 `OR1200_EXCEPTFSM_FLU2;
                        `OR1200_EXCEPTFSM_FLU2:
                                if (except_type == `OR1200_EXCEPT_TRAP) begin
                                        state <= #1 `OR1200_EXCEPTFSM_IDLE;
                                        extend_flush <= #1 1'b0;
                                        extend_flush_last <= #1 1'b0;
                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                end
                                else
//                              if (!if_stall & !id_freeze)
                                        state <= #1 `OR1200_EXCEPTFSM_FLU3;
                        `OR1200_EXCEPTFSM_FLU3:
//                              if (!if_stall && !id_freeze)
                                        begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                if (except_flushpipe)
                                                        $display(" INFO: EPCR0 %h  EEAR %h  ESR %h", epcr, eear, esr);
// synopsys translate_on
`endif
                                                state <= #1 `OR1200_EXCEPTFSM_FLU4;
                                        end
                        `OR1200_EXCEPTFSM_FLU4: begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU5;
                                        extend_flush <= #1 1'b0;
                                        extend_flush_last <= #1 1'b0; // damjan
                                end
                        `OR1200_EXCEPTFSM_FLU5: begin
                                if (!if_stall && !id_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display(" INFO: Just finished flushing pipeline.");
// synopsys translate_on
`endif
                                state <= #1 `OR1200_EXCEPTFSM_IDLE;
                                except_type <= #1 `OR1200_EXCEPT_NONE;
                                extend_flush_last <= #1 1'b0;
                        end
                        end
                endcase
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Exception logic ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Handles all OR1K exceptions inside CPU block. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50	504	lampret	`// Revision 1.15 2001/11/27 23:13:11 lampret`
51			`// Fixed except_stop width and fixed EX PC for 1400444f no-ops.`
52			`//`
53			`// Revision 1.14 2001/11/23 08:38:51 lampret`
54			`// Changed DSR/DRR behavior and exception detection.`
55			`//`
56			`// Revision 1.13 2001/11/20 18:46:15 simons`
57			`// Break point bug fixed`
58			`//`
59			`// Revision 1.12 2001/11/18 09:58:28 lampret`
60			`// Fixed some l.trap typos.`
61			`//`
62			`// Revision 1.11 2001/11/18 08:36:28 lampret`
63			`// For GDB changed single stepping and disabled trap exception.`
64			`//`
65			`// Revision 1.10 2001/11/13 10:02:21 lampret`
66			`// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)`
67			`//`
68			`// Revision 1.9 2001/11/10 03:43:57 lampret`
69			`// Fixed exceptions.`
70			`//`
71			`// Revision 1.8 2001/10/21 17:57:16 lampret`
72			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
73			`//`
74			`// Revision 1.7 2001/10/14 13:12:09 lampret`
75			`// MP3 version.`
76			`//`
77			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
78			`// no message`
79			`//`
80			`// Revision 1.2 2001/08/09 13:39:33 lampret`
81			`// Major clean-up.`
82			`//`
83			`// Revision 1.1 2001/07/20 00:46:03 lampret`
84			`// Development version of RTL. Libraries are missing.`
85			`//`
86			`//`
87
88			`// synopsys translate_off`
89			`include "timescale.v"
90			`// synopsys translate_on`
91			`include "or1200_defines.v"
92
93			`define OR1200_EXCEPTFSM_WIDTH 3
94			`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
95			`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
96			`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
97			`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
98			`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
99			`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
100
101			`//`
102			`// Exception recognition and sequencing`
103			`//`
104
105			`module or1200_except(`
106			`// Clock and reset`
107			`clk, rst,`
108
109			`// Internal i/f`
110			`sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,`
111			`sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,`
112			`branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,`
113			`if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,`
114			`except_started, except_stop,`
115	562	lampret	`wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,`
116	504	lampret	`esr, sr, lsu_addr`
117			`);`
118
119			`//`
120			`// I/O`
121			`//`
122			`input clk;`
123			`input rst;`
124			`input sig_ibuserr;`
125			`input sig_dbuserr;`
126			`input sig_illegal;`
127			`input sig_align;`
128			`input sig_range;`
129			`input sig_dtlbmiss;`
130			`input sig_dmmufault;`
131			`input sig_inthigh;`
132			`input sig_syscall;`
133			`input sig_trap;`
134			`input sig_itlbmiss;`
135			`input sig_immufault;`
136			`input sig_intlow;`
137			`input branch_taken;`
138			`input id_freeze;`
139			`input ex_freeze;`
140			`input wb_freeze;`
141			`input if_stall;`
142			`input [31:0] if_pc;`
143			`output [31:2] lr_sav;`
144			`input [31:0] datain;`
145			input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
146			`input epcr_we;`
147			`input eear_we;`
148			`input esr_we;`
149			`input pc_we;`
150			`output [31:0] epcr;`
151			`output [31:0] eear;`
152			output [`OR1200_SR_WIDTH-1:0] esr;
153			input [`OR1200_SR_WIDTH-1:0] sr;
154			`input [31:0] lsu_addr;`
155			`output flushpipe;`
156			`output extend_flush;`
157			output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
158			`output except_start;`
159			`output except_started;`
160			`output [12:0] except_stop;`
161			`output [31:0] wb_pc;`
162			`output [31:0] ex_pc;`
163	562	lampret	`output [31:0] id_pc;`
164	504	lampret
165			`//`
166			`// Internal regs and wires`
167			`//`
168			reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
169			`reg [31:0] id_pc;`
170			`reg [31:0] ex_pc;`
171			`reg [31:0] wb_pc;`
172			`reg [31:0] epcr;`
173			`reg [31:0] eear;`
174			reg [`OR1200_SR_WIDTH-1:0] esr;
175			`reg [3:0] id_exceptflags;`
176			`reg [3:0] ex_exceptflags;`
177			reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
178			`reg extend_flush;`
179			`reg extend_flush_last;`
180			`reg ex_dslot;`
181			`reg delayed1_ex_dslot;`
182			`reg delayed2_ex_dslot;`
183			`wire except_started;`
184			`wire [12:0] except_trig;`
185			`wire except_flushpipe;`
186			`reg [2:0] delayed_eir;`
187			`wire inthigh_pending;`
188			`wire intlow_pending;`
189
190			`//`
191			`// Simple combinatorial logic`
192			`//`
193			`assign except_started = extend_flush & except_start;`
194			`assign lr_sav = ex_pc[31:2];`
195	562	lampret	//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
196			assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
197			assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
198	504	lampret	assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
199
200			`//`
201			`// Order defines exception detection priority`
202			`//`
203			`assign except_trig = {`
204			inthigh_pending & ~du_dsr[`OR1200_DU_DSR_HPINTE],
205			ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_IME],
206			ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IPFE],
207			ex_exceptflags[3] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
208			sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
209			sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
210			sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
211			sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
212			sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
213			ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
214			sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
215	562	lampret	sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
216	504	lampret	sig_range & ~du_dsr[`OR1200_DU_DSR_RE]
217			`};`
218			`assign except_stop = {`
219			inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
220			ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_IME],
221			ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IPFE],
222			ex_exceptflags[3] & du_dsr[`OR1200_DU_DSR_BUSEE],
223			sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
224			sig_align & du_dsr[`OR1200_DU_DSR_AE],
225			sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
226			sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
227			sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
228			ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
229			sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
230	562	lampret	sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
231	504	lampret	sig_range & du_dsr[`OR1200_DU_DSR_RE]
232			`};`
233
234			`//`
235			`// PC and Exception flags pipelines`
236			`//`
237			`always @(posedge clk or posedge rst) begin`
238			`if (rst) begin`
239			`id_pc <= #1 32'd0;`
240			`id_exceptflags <= #1 4'b0000;`
241			`end`
242	562	lampret	`else if (flushpipe) begin`
243			`id_pc <= #1 32'h0000_0000;`
244			`id_exceptflags <= #1 4'b0000;`
245			`end`
246	504	lampret	`else if (!id_freeze) begin`
247			`id_pc <= #1 if_pc;`
248			`id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };`
249			`end`
250			`end`
251
252			`//`
253			`// delayed_eir`
254			`//`
255			`// SR[EIR] should not enable interrupts right away`
256			`// when it is restored with l.rfe. Instead delayed_eir`
257			`// together with SR[EIR] enables interrupts once`
258			`// pipeline is again ready.`
259			`//`
260			`always @(posedge rst or posedge clk)`
261			`if (rst)`
262			`delayed_eir <= #1 3'b000;`
263			else if (!sr[`OR1200_SR_EIR])
264			`delayed_eir <= #1 3'b000;`
265			`else`
266			`delayed_eir <= #1 {delayed_eir[1:0], 1'b1};`
267
268			`//`
269			`// PC and Exception flags pipelines`
270			`//`
271			`always @(posedge clk or posedge rst) begin`
272			`if (rst) begin`
273			`ex_dslot <= #1 1'b0;`
274			`ex_pc <= #1 32'd0;`
275			`ex_exceptflags <= #1 4'b0000;`
276			`delayed1_ex_dslot <= #1 1'b0;`
277			`delayed2_ex_dslot <= #1 1'b0;`
278			`end`
279	562	lampret	`else if (flushpipe) begin`
280			`ex_dslot <= #1 1'b0;`
281			`ex_pc <= #1 32'h0000_0000;`
282			`ex_exceptflags <= #1 4'b0000;`
283			`delayed1_ex_dslot <= #1 1'b0;`
284			`delayed2_ex_dslot <= #1 1'b0;`
285			`end`
286	504	lampret	`else if (!ex_freeze & id_freeze) begin`
287			`ex_dslot <= #1 1'b0;`
288			`ex_pc <= #1 id_pc;`
289			`ex_exceptflags <= #1 4'b0000;`
290			`delayed1_ex_dslot <= #1 ex_dslot;`
291			`delayed2_ex_dslot <= #1 delayed1_ex_dslot;`
292			`end`
293			`else if (!ex_freeze) begin`
294			`ifdef OR1200_VERBOSE
295			`// synopsys translate_off`
296			`$display("%t: ex_pc <= %h", $time, id_pc);`
297			`// synopsys translate_on`
298			`endif
299			`ex_dslot <= #1 branch_taken;`
300			`ex_pc <= #1 id_pc;`
301			`ex_exceptflags <= #1 id_exceptflags;`
302			`delayed1_ex_dslot <= #1 ex_dslot;`
303			`delayed2_ex_dslot <= #1 delayed1_ex_dslot;`
304			`end`
305			`end`
306
307			`//`
308			`// PC and Exception flags pipelines`
309			`//`
310			`always @(posedge clk or posedge rst) begin`
311			`if (rst) begin`
312			`wb_pc <= #1 32'd0;`
313			`end`
314			`else if (!wb_freeze) begin`
315			`wb_pc <= #1 ex_pc;`
316			`end`
317			`end`
318
319			`//`
320			`// Flush pipeline`
321			`//`
322	562	lampret	`assign flushpipe = except_flushpipe \| pc_we \| extend_flush;`
323	504	lampret
324			`//`
325			`// We have started execution of exception handler:`
326			`// 1. Asserted for 3 clock cycles`
327			`// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler`
328			`//`
329	562	lampret	`assign except_flushpipe = \|except_trig & !state;`
330	504	lampret
331			`//`
332			`// Exception FSM that sequences execution of exception handler`
333			`//`
334			`// except_type signals which exception handler we start fetching in:`
335			`// 1. Asserted in next clock cycle after exception is recognized`
336			`//`
337			`always @(posedge clk or posedge rst) begin`
338			`if (rst) begin`
339			state <= #1 `OR1200_EXCEPTFSM_IDLE;
340			except_type <= #1 `OR1200_EXCEPT_NONE;
341			`extend_flush <= #1 1'b0;`
342			`epcr <= #1 32'b0;`
343			`eear <= #1 32'b0;`
344			esr <= #1 `OR1200_SR_WIDTH'b010;
345			`extend_flush_last <= #1 1'b0;`
346			`end`
347			`else begin`
348			`case (state) // synopsys full_case parallel_case`
349			`OR1200_EXCEPTFSM_IDLE:
350			`if (except_flushpipe) begin`
351			state <= #1 `OR1200_EXCEPTFSM_FLU1;
352			`extend_flush <= #1 1'b1;`
353			`if (ex_dslot) begin`
354			`ifdef OR1200_VERBOSE
355			`// synopsys translate_off`
356			`$display(" INFO: Exception during first delay slot instruction.");`
357			`// synopsys translate_on`
358			`endif
359			`end`
360			`else if (delayed1_ex_dslot) begin`
361			`ifdef OR1200_VERBOSE
362			`// synopsys translate_off`
363			`$display(" INFO: Exception during second (NOP) delay slot instruction.");`
364			`// synopsys translate_on`
365			`endif
366			`end`
367			`else if (delayed2_ex_dslot) begin`
368			`ifdef OR1200_VERBOSE
369			`// synopsys translate_off`
370			`$display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");`
371			`// synopsys translate_on`
372			`endif
373			`end`
374			`else begin`
375			`ifdef OR1200_VERBOSE
376			`// synopsys translate_off`
377			`$display(" INFO: Exception during normal (no delay slot) instruction.");`
378			`// synopsys translate_on`
379			`endif
380			`end`
381
382			`esr <= #1 sr;`
383			`casex (except_trig)`
384			`13'b1_xxxx_xxxx_xxxx: begin`
385			except_type <= #1 `OR1200_EXCEPT_HPINT;
386			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
387			`end`
388			`13'b0_1xxx_xxxx_xxxx: begin`
389			except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
390			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
391			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
392			`end`
393			`13'b0_01xx_xxxx_xxxx: begin`
394			except_type <= #1 `OR1200_EXCEPT_IPF;
395			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
396			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
397			`end`
398			`13'b0_001x_xxxx_xxxx: begin`
399			except_type <= #1 `OR1200_EXCEPT_BUSERR;
400			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
401			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
402			`end`
403			`13'b0_0001_xxxx_xxxx: begin`
404			except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
405			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
406			`end`
407			`13'b0_0000_1xxx_xxxx: begin`
408			except_type <= #1 `OR1200_EXCEPT_ALIGN;
409			`eear <= #1 lsu_addr;`
410			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
411			`end`
412			`13'b0_0000_01xx_xxxx: begin`
413			except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
414			`eear <= #1 lsu_addr;`
415			`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
416			`end`
417			`13'b0_0000_001x_xxxx: begin`
418			except_type <= #1 `OR1200_EXCEPT_DPF;
419			`eear <= #1 lsu_addr;`
420			`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
421			`end`
422			`13'b0_0000_0001_xxxx: begin`
423			except_type <= #1 `OR1200_EXCEPT_BUSERR;
424			`eear <= #1 lsu_addr;`
425	562	lampret	`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
426	504	lampret	`end`
427			`13'b0_0000_0000_1xxx: begin`
428			except_type <= #1 `OR1200_EXCEPT_LPINT;
429			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
430			`end`
431			`13'b0_0000_0000_01xx: begin`
432			except_type <= #1 `OR1200_EXCEPT_RANGE;
433			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
434			`end`
435			`13'b0_0000_0000_001x: begin`
436			except_type <= #1 `OR1200_EXCEPT_TRAP;
437			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
438			`end`
439			`13'b0_0000_0000_0001: begin`
440			except_type <= #1 `OR1200_EXCEPT_SYSCALL;
441			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
442			`end`
443			`default:`
444			except_type <= #1 `OR1200_EXCEPT_NONE;
445			`endcase`
446			`end`
447			`else if (pc_we) begin`
448			state <= #1 `OR1200_EXCEPTFSM_FLU1;
449			`extend_flush <= #1 1'b1;`
450			`end`
451			`else begin`
452			`if (epcr_we)`
453			`epcr <= #1 datain;`
454			`if (eear_we)`
455			`eear <= #1 datain;`
456			`if (esr_we)`
457			esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
458			`end`
459			`OR1200_EXCEPTFSM_FLU1:
460	562	lampret	`// if (!if_stall & !id_freeze)`
461	504	lampret	state <= #1 `OR1200_EXCEPTFSM_FLU2;
462			`OR1200_EXCEPTFSM_FLU2:
463			if (except_type == `OR1200_EXCEPT_TRAP) begin
464			state <= #1 `OR1200_EXCEPTFSM_IDLE;
465			`extend_flush <= #1 1'b0;`
466			`extend_flush_last <= #1 1'b0;`
467			except_type <= #1 `OR1200_EXCEPT_NONE;
468			`end`
469	562	lampret	`else`
470			`// if (!if_stall & !id_freeze)`
471	504	lampret	state <= #1 `OR1200_EXCEPTFSM_FLU3;
472			`OR1200_EXCEPTFSM_FLU3:
473	562	lampret	`// if (!if_stall && !id_freeze)`
474	504	lampret	`begin`
475			`ifdef OR1200_VERBOSE
476			`// synopsys translate_off`
477			`if (except_flushpipe)`
478			`$display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr);`
479			`// synopsys translate_on`
480			`endif
481			state <= #1 `OR1200_EXCEPTFSM_FLU4;
482			`end`
483			`OR1200_EXCEPTFSM_FLU4: begin
484	562	lampret	state <= #1 `OR1200_EXCEPTFSM_FLU5;
485			`extend_flush <= #1 1'b0;`
486			`extend_flush_last <= #1 1'b0; // damjan`
487			`end`
488	504	lampret	`OR1200_EXCEPTFSM_FLU5: begin
489	562	lampret	`if (!if_stall && !id_freeze) begin`
490	504	lampret	`ifdef OR1200_VERBOSE
491			`// synopsys translate_off`
492			`$display(" INFO: Just finished flushing pipeline.");`
493			`// synopsys translate_on`
494			`endif
495			state <= #1 `OR1200_EXCEPTFSM_IDLE;
496			except_type <= #1 `OR1200_EXCEPT_NONE;
497			`extend_flush_last <= #1 1'b0;`
498			`end`
499	562	lampret	`end`
500	504	lampret	`endcase`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] [or1200_except.v] - Blame information for rev 562