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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Debug Unit                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Basic OR1200 debug unit.                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12  2001/11/30 18:58:00  simons
// Trap insn couses break after exits ex_insn.
//
// Revision 1.11  2001/11/23 08:38:51  lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.10  2001/11/20 21:25:44  lampret
// Fixed dbg_is_o assignment width.
//
// Revision 1.9  2001/11/20 18:46:14  simons
// Break point bug fixed
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 18:09:53  lampret
// Fixed sensitivity list.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Debug unit
//
 
module or1200_du(
        // RISC Internal Interface
        clk, rst,
        dcpu_cyc_i, dcpu_stb_i, dcpu_we_i,
        icpu_cyc_i, icpu_stb_i, ex_freeze, branch_op, ex_insn, du_dsr,
        du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
        // External Debug Interface
        dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
        dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// RISC Internal Interface
//
input                           clk;            // Clock
input                           rst;            // Reset
input                           dcpu_cyc_i;     // LSU status
input                           dcpu_stb_i;     // LSU status
input                           dcpu_we_i;      // LSU status
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cyc_i;     // IFETCH unit status
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_stb_i;     // IFETCH unit status
input                           ex_freeze;      // EX stage freeze
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
input   [dw-1:0]         ex_insn;        // EX insn
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
output                          du_stall;       // Debug Unit Stall
output  [aw-1:0]         du_addr;        // Debug Unit Address
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
output                          du_read;        // Debug Unit Read Enable
output                          du_write;       // Debug Unit Write Enable
input   [12:0]                   du_except;      // Exception masked by DSR
input                           spr_cs;         // SPR Chip Select
input                           spr_write;      // SPR Read/Write
input   [aw-1:0]         spr_addr;       // SPR Address
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
 
//
// External Debug Interface
//
input                           dbg_stall_i;    // External Stall Input
input   [dw-1:0]         dbg_dat_i;      // External Data Input
input   [aw-1:0]         dbg_adr_i;      // External Address Input
input   [2:0]                    dbg_op_i;       // External Operation Select Input
input                           dbg_ewt_i;      // External Watchpoint Trigger Input
output  [3:0]                    dbg_lss_o;      // External Load/Store Unit Status
output  [1:0]                    dbg_is_o;       // External Insn Fetch Status
output  [10:0]                   dbg_wp_o;       // Watchpoints Outputs
output                          dbg_bp_o;       // Breakpoint Output
output  [dw-1:0]         dbg_dat_o;      // External Data Output
 
 
//
// Some connections go directly from the CPU through DU to Debug I/F
//
assign dbg_lss_o = dcpu_cyc_i & dcpu_stb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
assign dbg_is_o = {1'b0, icpu_cyc_i & icpu_stb_i};
assign dbg_wp_o = 11'b000_0000_0000;
assign dbg_dat_o = du_dat_i;
 
//
// Some connections go directly from Debug I/F through DU to the CPU
//
assign du_stall = dbg_stall_i;
assign du_addr = dbg_adr_i;
assign du_dat_o = dbg_dat_i;
assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
 
`ifdef OR1200_DU_IMPLEMENTED
 
//
// Debug Mode Register 1 (only ST and BT implemented)
//
`ifdef OR1200_DU_DMR1
reg     [23:22]                 dmr1;           // DMR1 implemented (ST & BT)
`else
wire    [23:22]                 dmr1;           // DMR1 not implemented
`endif
 
//
// Debug Mode Register 2 (not implemented)
//
`ifdef OR1200_DU_DMR2
wire    [31:0]                   dmr2;           // DMR not implemented
`endif
 
//
// Debug Stop Register
//
`ifdef OR1200_DU_DSR
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
`else
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
`endif
 
//
// Debug Reason Register
//
`ifdef OR1200_DU_DRR
reg     [13:0]                   drr;            // DRR implemented
`else
wire    [13:0]                   drr;            // DRR not implemented
`endif
 
//
// Internal wires
//
wire                            dmr1_sel;       // DMR1 select
wire                            dsr_sel;        // DSR select
wire                            drr_sel;        // DRR select
reg                             dbg_bp_r;
`ifdef OR1200_DU_READREGS
reg     [31:0]                   spr_dat_o;
`endif
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
 
//
// DU registers address decoder
//
`ifdef OR1200_DU_DMR1
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DMR1));
`endif
`ifdef OR1200_DU_DSR
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DSR));
`endif
`ifdef OR1200_DU_DRR
assign drr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DRR));
`endif
 
//
// Decode started exception
//
always @(du_except) begin
        except_stop = 14'b0000_0000_0000;
        casex (du_except)
                13'b1_xxxx_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
                end
                13'b0_1xxx_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
                end
                13'b0_01xx_xxxx_xxxx:
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
                13'b0_001x_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
                end
                13'b0_0001_xxxx_xxxx:
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
                13'b0_0000_1xxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
                end
                13'b0_0000_01xx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
                end
                13'b0_0000_001x_xxxx:
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
                13'b0_0000_0001_xxxx:
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
                13'b0_0000_0000_1xxx:
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
                13'b0_0000_0000_01xx: begin
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
                end
                13'b0_0000_0000_001x: begin
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
                end
                13'b0_0000_0000_0001:
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
                default:
                        except_stop = 14'b0000_0000_0000;
        endcase
end
 
//
// dbg_bp_o is registered
//
assign dbg_bp_o = dbg_bp_r;
 
//
// Breakpoint activation register
//
always @(posedge clk or posedge rst)
        if (rst)
                dbg_bp_r <= #1 1'b0;
        else if (!ex_freeze)
                dbg_bp_r <= #1 |except_stop
`ifdef OR1200_DU_DMR1_ST
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
`endif
`ifdef OR1200_DU_DMR1_BT
                        | (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
`endif
                        ;
        else
                dbg_bp_r <= #1 |except_stop;
 
//
// Write to DMR1
//
`ifdef OR1200_DU_DMR1
always @(posedge clk or posedge rst)
        if (rst)
                dmr1 <= 2'b00;
        else if (dmr1_sel && spr_write)
                dmr1 <= #1 spr_dat_i[23:22];
`else
assign dmr1 = 2'b00;
`endif
 
//
// DMR2 bits tied to zero
//
`ifdef OR1200_DU_DMR2
assign dmr2 = 32'h0000_0000;
`endif
 
//
// Write to DSR
//
`ifdef OR1200_DU_DSR
always @(posedge clk or posedge rst)
        if (rst)
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
        else if (dsr_sel && spr_write)
                dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
`else
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
`endif
 
//
// Write to DRR
//
`ifdef OR1200_DU_DRR
always @(posedge clk or posedge rst)
        if (rst)
                drr <= 14'b0;
        else if (drr_sel && spr_write)
                drr <= #1 spr_dat_i[13:0];
        else
                drr <= #1 drr | except_stop;
`else
assign drr = 14'b0;
`endif
 
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
always @(spr_addr or dsr or drr or dmr1 or dmr2)
        case (spr_addr[`OR1200_SPR_OFS_BITS])
`ifdef OR1200_DU_DMR1
                `OR1200_DU_OFS_DMR1:
                        spr_dat_o = {8'b0, dmr1, 22'b0};
`endif
`ifdef OR1200_DU_DMR2
                `OR1200_DU_OFS_DMR2:
                        spr_dat_o = dmr2;
`endif
`ifdef OR1200_DU_DSR
                `OR1200_DU_OFS_DSR:
                        spr_dat_o = {18'b0, dsr};
`endif
`ifdef OR1200_DU_DRR
                `OR1200_DU_OFS_DRR:
                        spr_dat_o = {18'b0, drr};
`endif
                default:
                        spr_dat_o = 32'h0000_0000;
        endcase
`endif
 
//
// DSR alias
//
assign du_dsr = dsr;
 
`else
 
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_bp_o = 1'b0;
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
 
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
assign spr_dat_o = 32'h0000_0000;
`ifdef OR1200_DU_UNUSED_ZERO
`endif
`endif
 
`endif
 
endmodule

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[/] [or1k/] [tags/] [rel_16/] [or1200/] [rtl/] [verilog/] [or1200_du.v] - Blame information for rev 589

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Debug Unit ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Basic OR1200 debug unit. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	589	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
48			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
49			`//`
50	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
51			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
52			`//`
53	504	lampret	`// Revision 1.12 2001/11/30 18:58:00 simons`
54			`// Trap insn couses break after exits ex_insn.`
55			`//`
56			`// Revision 1.11 2001/11/23 08:38:51 lampret`
57			`// Changed DSR/DRR behavior and exception detection.`
58			`//`
59			`// Revision 1.10 2001/11/20 21:25:44 lampret`
60			`// Fixed dbg_is_o assignment width.`
61			`//`
62			`// Revision 1.9 2001/11/20 18:46:14 simons`
63			`// Break point bug fixed`
64			`//`
65			`// Revision 1.8 2001/11/18 08:36:28 lampret`
66			`// For GDB changed single stepping and disabled trap exception.`
67			`//`
68			`// Revision 1.7 2001/10/21 18:09:53 lampret`
69			`// Fixed sensitivity list.`
70			`//`
71			`// Revision 1.6 2001/10/14 13:12:09 lampret`
72			`// MP3 version.`
73			`//`
74			`//`
75
76			`// synopsys translate_off`
77			`include "timescale.v"
78			`// synopsys translate_on`
79			`include "or1200_defines.v"
80
81			`//`
82			`// Debug unit`
83			`//`
84
85			`module or1200_du(`
86			`// RISC Internal Interface`
87			`clk, rst,`
88			`dcpu_cyc_i, dcpu_stb_i, dcpu_we_i,`
89			`icpu_cyc_i, icpu_stb_i, ex_freeze, branch_op, ex_insn, du_dsr,`
90			`du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,`
91			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
92
93			`// External Debug Interface`
94			`dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,`
95			`dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o`
96			`);`
97
98			parameter dw = `OR1200_OPERAND_WIDTH;
99			parameter aw = `OR1200_OPERAND_WIDTH;
100
101			`//`
102			`// I/O`
103			`//`
104
105			`//`
106			`// RISC Internal Interface`
107			`//`
108			`input clk; // Clock`
109			`input rst; // Reset`
110			`input dcpu_cyc_i; // LSU status`
111			`input dcpu_stb_i; // LSU status`
112			`input dcpu_we_i; // LSU status`
113			input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cyc_i; // IFETCH unit status
114			input [`OR1200_FETCHOP_WIDTH-1:0] icpu_stb_i; // IFETCH unit status
115			`input ex_freeze; // EX stage freeze`
116			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
117			`input [dw-1:0] ex_insn; // EX insn`
118			output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
119			`output du_stall; // Debug Unit Stall`
120			`output [aw-1:0] du_addr; // Debug Unit Address`
121			`input [dw-1:0] du_dat_i; // Debug Unit Data In`
122			`output [dw-1:0] du_dat_o; // Debug Unit Data Out`
123			`output du_read; // Debug Unit Read Enable`
124			`output du_write; // Debug Unit Write Enable`
125			`input [12:0] du_except; // Exception masked by DSR`
126			`input spr_cs; // SPR Chip Select`
127			`input spr_write; // SPR Read/Write`
128			`input [aw-1:0] spr_addr; // SPR Address`
129			`input [dw-1:0] spr_dat_i; // SPR Data Input`
130			`output [dw-1:0] spr_dat_o; // SPR Data Output`
131
132			`//`
133			`// External Debug Interface`
134			`//`
135			`input dbg_stall_i; // External Stall Input`
136			`input [dw-1:0] dbg_dat_i; // External Data Input`
137			`input [aw-1:0] dbg_adr_i; // External Address Input`
138			`input [2:0] dbg_op_i; // External Operation Select Input`
139			`input dbg_ewt_i; // External Watchpoint Trigger Input`
140			`output [3:0] dbg_lss_o; // External Load/Store Unit Status`
141			`output [1:0] dbg_is_o; // External Insn Fetch Status`
142			`output [10:0] dbg_wp_o; // Watchpoints Outputs`
143			`output dbg_bp_o; // Breakpoint Output`
144			`output [dw-1:0] dbg_dat_o; // External Data Output`
145
146
147			`//`
148			`// Some connections go directly from the CPU through DU to Debug I/F`
149			`//`
150			`assign dbg_lss_o = dcpu_cyc_i & dcpu_stb_i ? {dcpu_we_i, 3'b000} : 4'b0000;`
151			`assign dbg_is_o = {1'b0, icpu_cyc_i & icpu_stb_i};`
152			`assign dbg_wp_o = 11'b000_0000_0000;`
153			`assign dbg_dat_o = du_dat_i;`
154
155			`//`
156			`// Some connections go directly from Debug I/F through DU to the CPU`
157			`//`
158			`assign du_stall = dbg_stall_i;`
159			`assign du_addr = dbg_adr_i;`
160			`assign du_dat_o = dbg_dat_i;`
161			assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
162			assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
163
164			`ifdef OR1200_DU_IMPLEMENTED
165
166			`//`
167			`// Debug Mode Register 1 (only ST and BT implemented)`
168			`//`
169			`ifdef OR1200_DU_DMR1
170			`reg [23:22] dmr1; // DMR1 implemented (ST & BT)`
171			`else
172			`wire [23:22] dmr1; // DMR1 not implemented`
173			`endif
174
175			`//`
176			`// Debug Mode Register 2 (not implemented)`
177			`//`
178			`ifdef OR1200_DU_DMR2
179			`wire [31:0] dmr2; // DMR not implemented`
180			`endif
181
182			`//`
183			`// Debug Stop Register`
184			`//`
185			`ifdef OR1200_DU_DSR
186			reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
187			`else
188			wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
189			`endif
190
191			`//`
192			`// Debug Reason Register`
193			`//`
194			`ifdef OR1200_DU_DRR
195			`reg [13:0] drr; // DRR implemented`
196			`else
197			`wire [13:0] drr; // DRR not implemented`
198			`endif
199
200			`//`
201			`// Internal wires`
202			`//`
203			`wire dmr1_sel; // DMR1 select`
204			`wire dsr_sel; // DSR select`
205			`wire drr_sel; // DRR select`
206			`reg dbg_bp_r;`
207			`ifdef OR1200_DU_READREGS
208			`reg [31:0] spr_dat_o;`
209			`endif
210			`reg [13:0] except_stop; // Exceptions that stop because of DSR`
211
212			`//`
213			`// DU registers address decoder`
214			`//`
215			`ifdef OR1200_DU_DMR1
216			assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DMR1));
217			`endif
218			`ifdef OR1200_DU_DSR
219			assign dsr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DSR));
220			`endif
221			`ifdef OR1200_DU_DRR
222			assign drr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DRR));
223			`endif
224
225			`//`
226			`// Decode started exception`
227			`//`
228			`always @(du_except) begin`
229			`except_stop = 14'b0000_0000_0000;`
230			`casex (du_except)`
231			`13'b1_xxxx_xxxx_xxxx: begin`
232	589	lampret	except_stop[`OR1200_DU_DRR_IE] = 1'b1;
233	504	lampret	`end`
234			`13'b0_1xxx_xxxx_xxxx: begin`
235			except_stop[`OR1200_DU_DRR_IME] = 1'b1;
236			`end`
237			`13'b0_01xx_xxxx_xxxx:`
238			except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
239			`13'b0_001x_xxxx_xxxx: begin`
240			except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
241			`end`
242			`13'b0_0001_xxxx_xxxx:`
243			except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
244			`13'b0_0000_1xxx_xxxx: begin`
245			except_stop[`OR1200_DU_DRR_AE] = 1'b1;
246			`end`
247			`13'b0_0000_01xx_xxxx: begin`
248			except_stop[`OR1200_DU_DRR_DME] = 1'b1;
249			`end`
250			`13'b0_0000_001x_xxxx:`
251			except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
252			`13'b0_0000_0001_xxxx:`
253			except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
254			`13'b0_0000_0000_1xxx:`
255	589	lampret	except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
256	504	lampret	`13'b0_0000_0000_01xx: begin`
257			except_stop[`OR1200_DU_DRR_RE] = 1'b1;
258			`end`
259			`13'b0_0000_0000_001x: begin`
260			except_stop[`OR1200_DU_DRR_TE] = 1'b1;
261			`end`
262			`13'b0_0000_0000_0001:`
263			except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
264			`default:`
265			`except_stop = 14'b0000_0000_0000;`
266			`endcase`
267			`end`
268
269			`//`
270			`// dbg_bp_o is registered`
271			`//`
272			`assign dbg_bp_o = dbg_bp_r;`
273
274			`//`
275			`// Breakpoint activation register`
276			`//`
277			`always @(posedge clk or posedge rst)`
278			`if (rst)`
279			`dbg_bp_r <= #1 1'b0;`
280			`else if (!ex_freeze)`
281			`dbg_bp_r <= #1 \|except_stop`
282			`ifdef OR1200_DU_DMR1_ST
283			\| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
284			`endif
285			`ifdef OR1200_DU_DMR1_BT
286			\| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
287			`endif
288			`;`
289			`else`
290	562	lampret	`dbg_bp_r <= #1 \|except_stop;`
291	504	lampret
292			`//`
293			`// Write to DMR1`
294			`//`
295			`ifdef OR1200_DU_DMR1
296			`always @(posedge clk or posedge rst)`
297			`if (rst)`
298			`dmr1 <= 2'b00;`
299			`else if (dmr1_sel && spr_write)`
300			`dmr1 <= #1 spr_dat_i[23:22];`
301			`else
302			`assign dmr1 = 2'b00;`
303			`endif
304
305			`//`
306			`// DMR2 bits tied to zero`
307			`//`
308			`ifdef OR1200_DU_DMR2
309			`assign dmr2 = 32'h0000_0000;`
310			`endif
311
312			`//`
313			`// Write to DSR`
314			`//`
315			`ifdef OR1200_DU_DSR
316			`always @(posedge clk or posedge rst)`
317			`if (rst)`
318			dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
319			`else if (dsr_sel && spr_write)`
320			dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
321			`else
322			assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
323			`endif
324
325			`//`
326			`// Write to DRR`
327			`//`
328			`ifdef OR1200_DU_DRR
329			`always @(posedge clk or posedge rst)`
330			`if (rst)`
331			`drr <= 14'b0;`
332			`else if (drr_sel && spr_write)`
333			`drr <= #1 spr_dat_i[13:0];`
334			`else`
335			`drr <= #1 drr \| except_stop;`
336			`else
337			`assign drr = 14'b0;`
338			`endif
339
340			`//`
341			`// Read DU registers`
342			`//`
343			`ifdef OR1200_DU_READREGS
344			`always @(spr_addr or dsr or drr or dmr1 or dmr2)`
345			case (spr_addr[`OR1200_SPR_OFS_BITS])
346			`ifdef OR1200_DU_DMR1
347			`OR1200_DU_OFS_DMR1:
348			`spr_dat_o = {8'b0, dmr1, 22'b0};`
349			`endif
350			`ifdef OR1200_DU_DMR2
351			`OR1200_DU_OFS_DMR2:
352			`spr_dat_o = dmr2;`
353			`endif
354			`ifdef OR1200_DU_DSR
355			`OR1200_DU_OFS_DSR:
356			`spr_dat_o = {18'b0, dsr};`
357			`endif
358			`ifdef OR1200_DU_DRR
359			`OR1200_DU_OFS_DRR:
360			`spr_dat_o = {18'b0, drr};`
361			`endif
362			`default:`
363			`spr_dat_o = 32'h0000_0000;`
364			`endcase`
365			`endif
366
367			`//`
368			`// DSR alias`
369			`//`
370			`assign du_dsr = dsr;`
371
372			`else
373
374			`//`
375			`// When DU is not implemented, drive all outputs as would when DU is disabled`
376			`//`
377			`assign dbg_bp_o = 1'b0;`
378			assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
379
380			`//`
381			`// Read DU registers`
382			`//`
383			`ifdef OR1200_DU_READREGS
384			`assign spr_dat_o = 32'h0000_0000;`
385			`ifdef OR1200_DU_UNUSED_ZERO
386			`endif
387			`endif
388
389			`endif
390
391			`endmodule`