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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's generate PC                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, interface to IC.                                        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
//
// Revision 1.7  2003/04/20 22:23:57  lampret
// No functional change. Only added customization for exception vectors.
//
// Revision 1.6  2002/03/29 15:16:55  lampret
// Some of the warnings fixed.
//
// Revision 1.5  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.3  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_genpc(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
        icpu_rty_i, icpu_adr_i,
 
        // Internal i/f
        branch_op, except_type, except_prefix,
        branch_addrofs, lr_restor, flag, taken, except_start,
        binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
        genpc_freeze, genpc_stop_prefetch, no_more_dslot
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
output  [31:0]                   icpu_adr_o;
output                          icpu_cycstb_o;
output  [3:0]                    icpu_sel_o;
output  [3:0]                    icpu_tag_o;
input                           icpu_rty_i;
input   [31:0]                   icpu_adr_i;
 
//
// Internal i/f
//
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
input                                   except_prefix;
input   [31:2]                  branch_addrofs;
input   [31:0]                   lr_restor;
input                           flag;
output                          taken;
input                           except_start;
input   [31:2]                  binsn_addr;
input   [31:0]                   epcr;
input   [31:0]                   spr_dat_i;
input                           spr_pc_we;
input                           genpc_refetch;
input                           genpc_stop_prefetch;
input                           genpc_freeze;
input                           no_more_dslot;
 
//
// Internal wires and regs
//
reg     [31:2]                  pcreg;
reg     [31:0]                   pc;
reg                             taken;  /* Set to in case of jump or taken branch */
reg                             genpc_refetch_r;
 
//
// Address of insn to be fecthed
//
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 
//
// Control access to IC subsystem
//
// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store
//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r);
//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch);
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
 
//
// genpc_freeze_r
//
always @(posedge clk or posedge rst)
        if (rst)
                genpc_refetch_r <= #1 1'b0;
        else if (genpc_refetch)
                genpc_refetch_r <= #1 1'b1;
        else
                genpc_refetch_r <= #1 1'b0;
 
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
        or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
                {2'b00, `OR1200_BRANCHOP_NOP}: begin
                        pc = {pcreg + 1'd1, 2'b0};
                        taken = 1'b0;
                end
                {2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
// synopsys translate_on
`endif
                        pc = lr_restor;
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {binsn_addr + branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BF}:
                        if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
                                pc = {pcreg + 1'd1, 2'b0};
                                taken = 1'b0;
                        end
                {2'b00, `OR1200_BRANCHOP_BNF}:
                        if (flag) begin
                                pc = {pcreg + 1'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
                                taken = 1'b0;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                {2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
                        pc = epcr;
                        taken = 1'b1;
                end
                {2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
                        pc = { {4{except_prefix}}, `OR1200_EXCEPT_MMMM, except_type, `OR1200_EXCEPT_VV};
                        taken = 1'b1;
                end
                default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
                        pc = spr_dat_i;
                        taken = 1'b0;
                end
        endcase
end
 
//
// PC register
//
always @(posedge clk or posedge rst)
        if (rst)
//              pcreg <= #1 30'd63;
                pcreg <= #1 ({{4{except_prefix}}, `OR1200_EXCEPT_MMMM, `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_VV} - 1) >> 2;
        else if (spr_pc_we)
                pcreg <= #1 spr_dat_i[31:2];
        else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
//      else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
                pcreg <= #1 pc[31:2];
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's generate PC ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PC, interface to IC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	1206	lampret	`// Revision 1.7.4.1 2003/07/08 15:36:37 lampret`
48			`// Added embedded memory QMEM.`
49			`//`
50	1171	lampret	`// Revision 1.7 2003/04/20 22:23:57 lampret`
51			`// No functional change. Only added customization for exception vectors.`
52			`//`
53	1155	lampret	`// Revision 1.6 2002/03/29 15:16:55 lampret`
54			`// Some of the warnings fixed.`
55			`//`
56	788	lampret	`// Revision 1.5 2002/02/11 04:33:17 lampret`
57			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
58			`//`
59	660	lampret	`// Revision 1.4 2002/01/28 01:16:00 lampret`
60			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
61			`//`
62	617	lampret	`// Revision 1.3 2002/01/18 07:56:00 lampret`
63			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
64			`//`
65	589	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
66			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
67			`//`
68	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
69			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
70			`//`
71	504	lampret	`// Revision 1.10 2001/11/20 18:46:15 simons`
72			`// Break point bug fixed`
73			`//`
74			`// Revision 1.9 2001/11/18 09:58:28 lampret`
75			`// Fixed some l.trap typos.`
76			`//`
77			`// Revision 1.8 2001/11/18 08:36:28 lampret`
78			`// For GDB changed single stepping and disabled trap exception.`
79			`//`
80			`// Revision 1.7 2001/10/21 17:57:16 lampret`
81			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
82			`//`
83			`// Revision 1.6 2001/10/14 13:12:09 lampret`
84			`// MP3 version.`
85			`//`
86			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
87			`// no message`
88			`//`
89			`// Revision 1.1 2001/08/09 13:39:33 lampret`
90			`// Major clean-up.`
91			`//`
92			`//`
93
94			`// synopsys translate_off`
95			`include "timescale.v"
96			`// synopsys translate_on`
97			`include "or1200_defines.v"
98
99			`module or1200_genpc(`
100			`// Clock and reset`
101			`clk, rst,`
102
103			`// External i/f to IC`
104	660	lampret	`icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,`
105	788	lampret	`icpu_rty_i, icpu_adr_i,`
106	504	lampret
107			`// Internal i/f`
108	589	lampret	`branch_op, except_type, except_prefix,`
109	504	lampret	`branch_addrofs, lr_restor, flag, taken, except_start,`
110	562	lampret	`binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,`
111	1206	lampret	`genpc_freeze, genpc_stop_prefetch, no_more_dslot`
112	504	lampret	`);`
113
114			`//`
115			`// I/O`
116			`//`
117
118			`//`
119			`// Clock and reset`
120			`//`
121			`input clk;`
122			`input rst;`
123
124			`//`
125			`// External i/f to IC`
126			`//`
127			`output [31:0] icpu_adr_o;`
128	660	lampret	`output icpu_cycstb_o;`
129	504	lampret	`output [3:0] icpu_sel_o;`
130			`output [3:0] icpu_tag_o;`
131			`input icpu_rty_i;`
132			`input [31:0] icpu_adr_i;`
133
134			`//`
135			`// Internal i/f`
136			`//`
137			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
138			input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
139	589	lampret	`input except_prefix;`
140	504	lampret	`input [31:2] branch_addrofs;`
141			`input [31:0] lr_restor;`
142			`input flag;`
143			`output taken;`
144			`input except_start;`
145			`input [31:2] binsn_addr;`
146			`input [31:0] epcr;`
147			`input [31:0] spr_dat_i;`
148			`input spr_pc_we;`
149			`input genpc_refetch;`
150	1206	lampret	`input genpc_stop_prefetch;`
151	562	lampret	`input genpc_freeze;`
152	617	lampret	`input no_more_dslot;`
153	504	lampret
154			`//`
155			`// Internal wires and regs`
156			`//`
157			`reg [31:2] pcreg;`
158			`reg [31:0] pc;`
159			`reg taken; /* Set to in case of jump or taken branch */`
160	1206	lampret	`reg genpc_refetch_r;`
161	504	lampret
162			`//`
163			`// Address of insn to be fecthed`
164			`//`
165	617	lampret	`assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i \| genpc_refetch) ? icpu_adr_i : pc;`
166			`// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i \| genpc_refetch) ? icpu_adr_i : pc;`
167	504	lampret
168			`//`
169			`// Control access to IC subsystem`
170			`//`
171	660	lampret	`// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;`
172	1206	lampret	`assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store`
173			`//assign icpu_cycstb_o = !(genpc_freeze \| genpc_refetch & genpc_refetch_r);`
174			`//assign icpu_cycstb_o = !(genpc_freeze \| genpc_stop_prefetch);`
175	504	lampret	`assign icpu_sel_o = 4'b1111;`
176			assign icpu_tag_o = `OR1200_ITAG_NI;
177
178			`//`
179	1206	lampret	`// genpc_freeze_r`
180			`//`
181			`always @(posedge clk or posedge rst)`
182			`if (rst)`
183			`genpc_refetch_r <= #1 1'b0;`
184			`else if (genpc_refetch)`
185			`genpc_refetch_r <= #1 1'b1;`
186			`else`
187			`genpc_refetch_r <= #1 1'b0;`
188
189			`//`
190	504	lampret	`// Async calculation of new PC value. This value is used for addressing the IC.`
191			`//`
192			`always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type`
193	589	lampret	`or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin`
194	504	lampret	`casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case`
195			{2'b00, `OR1200_BRANCHOP_NOP}: begin
196	1171	lampret	`pc = {pcreg + 1'd1, 2'b0};`
197	504	lampret	`taken = 1'b0;`
198			`end`
199			{2'b00, `OR1200_BRANCHOP_J}: begin
200			`ifdef OR1200_VERBOSE
201			`// synopsys translate_off`
202			`$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);`
203			`// synopsys translate_on`
204			`endif
205			`pc = {branch_addrofs, 2'b0};`
206			`taken = 1'b1;`
207			`end`
208			{2'b00, `OR1200_BRANCHOP_JR}: begin
209			`ifdef OR1200_VERBOSE
210			`// synopsys translate_off`
211			`$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);`
212			`// synopsys translate_on`
213			`endif
214			`pc = lr_restor;`
215			`taken = 1'b1;`
216			`end`
217			{2'b00, `OR1200_BRANCHOP_BAL}: begin
218			`ifdef OR1200_VERBOSE
219			`// synopsys translate_off`
220			`$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
221			`// synopsys translate_on`
222			`endif
223			`pc = {binsn_addr + branch_addrofs, 2'b0};`
224			`taken = 1'b1;`
225			`end`
226			{2'b00, `OR1200_BRANCHOP_BF}:
227			`if (flag) begin`
228			`ifdef OR1200_VERBOSE
229			`// synopsys translate_off`
230			`$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
231			`// synopsys translate_on`
232			`endif
233			`pc = {binsn_addr + branch_addrofs, 2'b0};`
234			`taken = 1'b1;`
235			`end`
236			`else begin`
237			`ifdef OR1200_VERBOSE
238			`// synopsys translate_off`
239			`$display("%t: BRANCHOP_BF: not taken", $time);`
240			`// synopsys translate_on`
241			`endif
242	1171	lampret	`pc = {pcreg + 1'd1, 2'b0};`
243	504	lampret	`taken = 1'b0;`
244			`end`
245			{2'b00, `OR1200_BRANCHOP_BNF}:
246			`if (flag) begin`
247	1171	lampret	`pc = {pcreg + 1'd1, 2'b0};`
248	504	lampret	`ifdef OR1200_VERBOSE
249			`// synopsys translate_off`
250			`$display("%t: BRANCHOP_BNF: not taken", $time);`
251			`// synopsys translate_on`
252			`endif
253			`taken = 1'b0;`
254			`end`
255			`else begin`
256			`ifdef OR1200_VERBOSE
257			`// synopsys translate_off`
258			`$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
259			`// synopsys translate_on`
260			`endif
261			`pc = {binsn_addr + branch_addrofs, 2'b0};`
262			`taken = 1'b1;`
263			`end`
264			{2'b00, `OR1200_BRANCHOP_RFE}: begin
265			`ifdef OR1200_VERBOSE
266			`// synopsys translate_off`
267			`$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);`
268			`// synopsys translate_on`
269			`endif
270			`pc = epcr;`
271			`taken = 1'b1;`
272			`end`
273			`{2'b01, 3'bxxx}: begin`
274			`ifdef OR1200_VERBOSE
275			`// synopsys translate_off`
276			`$display("Starting exception: %h.", except_type);`
277			`// synopsys translate_on`
278			`endif
279	1155	lampret	pc = { {4{except_prefix}}, `OR1200_EXCEPT_MMMM, except_type, `OR1200_EXCEPT_VV};
280	504	lampret	`taken = 1'b1;`
281			`end`
282			`default: begin`
283			`ifdef OR1200_VERBOSE
284			`// synopsys translate_off`
285			`$display("l.mtspr writing into PC: %h.", spr_dat_i);`
286			`// synopsys translate_on`
287			`endif
288			`pc = spr_dat_i;`
289			`taken = 1'b0;`
290			`end`
291			`endcase`
292			`end`
293
294			`//`
295			`// PC register`
296			`//`
297			`always @(posedge clk or posedge rst)`
298			`if (rst)`
299	1155	lampret	`// pcreg <= #1 30'd63;`
300	1206	lampret	pcreg <= #1 ({{4{except_prefix}}, `OR1200_EXCEPT_MMMM, `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_VV} - 1) >> 2;
301	504	lampret	`else if (spr_pc_we)`
302			`pcreg <= #1 spr_dat_i[31:2];`
303	617	lampret	`else if (no_more_dslot \| except_start \| !genpc_freeze & !icpu_rty_i & !genpc_refetch)`
304			`// else if (except_start \| !genpc_freeze & !icpu_rty_i & !genpc_refetch)`
305	504	lampret	`pcreg <= #1 pc[31:2];`
306
307			`endmodule`

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