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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Debug Unit                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Basic OR1200 debug unit.                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2002/03/14 00:30:24  lampret
// Added alternative for critical path in DU.
//
// Revision 1.5  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.3  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12  2001/11/30 18:58:00  simons
// Trap insn couses break after exits ex_insn.
//
// Revision 1.11  2001/11/23 08:38:51  lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.10  2001/11/20 21:25:44  lampret
// Fixed dbg_is_o assignment width.
//
// Revision 1.9  2001/11/20 18:46:14  simons
// Break point bug fixed
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 18:09:53  lampret
// Fixed sensitivity list.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Debug unit
//
 
module or1200_du(
        // RISC Internal Interface
        clk, rst,
        dcpu_cycstb_i, dcpu_we_i, icpu_cycstb_i,
        ex_freeze, branch_op, ex_insn,
        spr_dat_npc, rf_dataw,
        du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
        du_read, du_write, du_except,
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
        // External Debug Interface
        dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
        dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// RISC Internal Interface
//
input                           clk;            // Clock
input                           rst;            // Reset
input                           dcpu_cycstb_i;  // LSU status
input                           dcpu_we_i;      // LSU status
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cycstb_i;  // IFETCH unit status
input                           ex_freeze;      // EX stage freeze
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
input   [dw-1:0]         ex_insn;        // EX insn
input   [31:0]                   spr_dat_npc;    // Next PC (for trace)
input   [31:0]                   rf_dataw;       // ALU result (for trace)
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
output                          du_stall;       // Debug Unit Stall
output  [aw-1:0]         du_addr;        // Debug Unit Address
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
output                          du_read;        // Debug Unit Read Enable
output                          du_write;       // Debug Unit Write Enable
input   [12:0]                   du_except;      // Exception masked by DSR
input                           spr_cs;         // SPR Chip Select
input                           spr_write;      // SPR Read/Write
input   [aw-1:0]         spr_addr;       // SPR Address
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
 
//
// External Debug Interface
//
input                           dbg_stall_i;    // External Stall Input
input   [dw-1:0]         dbg_dat_i;      // External Data Input
input   [aw-1:0]         dbg_adr_i;      // External Address Input
input   [2:0]                    dbg_op_i;       // External Operation Select Input
input                           dbg_ewt_i;      // External Watchpoint Trigger Input
output  [3:0]                    dbg_lss_o;      // External Load/Store Unit Status
output  [1:0]                    dbg_is_o;       // External Insn Fetch Status
output  [10:0]                   dbg_wp_o;       // Watchpoints Outputs
output                          dbg_bp_o;       // Breakpoint Output
output  [dw-1:0]         dbg_dat_o;      // External Data Output
 
 
//
// Some connections go directly from the CPU through DU to Debug I/F
//
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
assign dbg_lss_o = 4'b0000;
 
reg     [1:0]                    dbg_is_o;
//
// Show insn activity (temp, must be removed)
//
always @(posedge clk or posedge rst)
        if (rst)
                dbg_is_o <= #1 2'b00;
        else if (!ex_freeze &
                ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
                dbg_is_o <= #1 ~dbg_is_o;
`ifdef UNUSED
assign dbg_is_o = 2'b00;
`endif
`else
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
assign dbg_is_o = {1'b0, icpu_cycstb_i};
`endif
assign dbg_wp_o = 11'b000_0000_0000;
assign dbg_dat_o = du_dat_i;
 
//
// Some connections go directly from Debug I/F through DU to the CPU
//
assign du_stall = dbg_stall_i;
assign du_addr = dbg_adr_i;
assign du_dat_o = dbg_dat_i;
assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
 
`ifdef OR1200_DU_IMPLEMENTED
 
//
// Debug Mode Register 1 (only ST and BT implemented)
//
`ifdef OR1200_DU_DMR1
reg     [23:22]                 dmr1;           // DMR1 implemented (ST & BT)
`else
wire    [23:22]                 dmr1;           // DMR1 not implemented
`endif
 
//
// Debug Mode Register 2 (not implemented)
//
`ifdef OR1200_DU_DMR2
wire    [31:0]                   dmr2;           // DMR not implemented
`endif
 
//
// Debug Stop Register
//
`ifdef OR1200_DU_DSR
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
`else
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
`endif
 
//
// Debug Reason Register
//
`ifdef OR1200_DU_DRR
reg     [13:0]                   drr;            // DRR implemented
`else
wire    [13:0]                   drr;            // DRR not implemented
`endif
 
//
// Internal wires
//
wire                            dmr1_sel;       // DMR1 select
wire                            dsr_sel;        // DSR select
wire                            drr_sel;        // DRR select
reg                             dbg_bp_r;
`ifdef OR1200_DU_READREGS
reg     [31:0]                   spr_dat_o;
`endif
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
`ifdef OR1200_DU_TB_IMPLEMENTED
wire                            tb_enw;
reg     [7:0]                    tb_wadr;
reg [31:0]                       tb_timstmp;
`endif
wire    [31:0]                   tbia_dat_o;
wire    [31:0]                   tbim_dat_o;
wire    [31:0]                   tbar_dat_o;
wire    [31:0]                   tbts_dat_o;
 
//
// DU registers address decoder
//
`ifdef OR1200_DU_DMR1
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DMR1));
`endif
`ifdef OR1200_DU_DSR
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DSR));
`endif
`ifdef OR1200_DU_DRR
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DRR));
`endif
 
//
// Decode started exception
//
always @(du_except) begin
        except_stop = 14'b0000_0000_0000;
        casex (du_except)
                13'b1_xxxx_xxxx_xxxx:
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
                13'b0_1xxx_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
                end
                13'b0_01xx_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
                end
                13'b0_001x_xxxx_xxxx:
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
                13'b0_0001_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
                end
                13'b0_0000_1xxx_xxxx:
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
                13'b0_0000_01xx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
                end
                13'b0_0000_001x_xxxx: begin
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
                end
                13'b0_0000_0001_xxxx:
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
                13'b0_0000_0000_1xxx:
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
                13'b0_0000_0000_01xx: begin
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
                end
                13'b0_0000_0000_001x: begin
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
                end
                13'b0_0000_0000_0001:
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
                default:
                        except_stop = 14'b0000_0000_0000;
        endcase
end
 
//
// dbg_bp_o is registered
//
assign dbg_bp_o = dbg_bp_r;
 
//
// Breakpoint activation register
//
always @(posedge clk or posedge rst)
        if (rst)
                dbg_bp_r <= #1 1'b0;
        else if (!ex_freeze)
                dbg_bp_r <= #1 |except_stop
`ifdef OR1200_DU_DMR1_ST
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
`endif
`ifdef OR1200_DU_DMR1_BT
                        | (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
`endif
                        ;
        else
                dbg_bp_r <= #1 |except_stop;
 
//
// Write to DMR1
//
`ifdef OR1200_DU_DMR1
always @(posedge clk or posedge rst)
        if (rst)
                dmr1 <= 2'b00;
        else if (dmr1_sel && spr_write)
                dmr1 <= #1 spr_dat_i[23:22];
`else
assign dmr1 = 2'b00;
`endif
 
//
// DMR2 bits tied to zero
//
`ifdef OR1200_DU_DMR2
assign dmr2 = 32'h0000_0000;
`endif
 
//
// Write to DSR
//
`ifdef OR1200_DU_DSR
always @(posedge clk or posedge rst)
        if (rst)
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
        else if (dsr_sel && spr_write)
                dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
`else
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
`endif
 
//
// Write to DRR
//
`ifdef OR1200_DU_DRR
always @(posedge clk or posedge rst)
        if (rst)
                drr <= 14'b0;
        else if (drr_sel && spr_write)
                drr <= #1 spr_dat_i[13:0];
        else
                drr <= #1 drr | except_stop;
`else
assign drr = 14'b0;
`endif
 
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
always @(spr_addr or dsr or drr or dmr1 or dmr2 or
        tbia_dat_o or tbim_dat_o or tbar_dat_o or tb_wadr)
        casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_DU_DMR1
                `OR1200_DU_OFS_DMR1:
                        spr_dat_o = {8'b0, dmr1, 22'b0};
`endif
`ifdef OR1200_DU_DMR2
                `OR1200_DU_OFS_DMR2:
                        spr_dat_o = dmr2;
`endif
`ifdef OR1200_DU_DSR
                `OR1200_DU_OFS_DSR:
                        spr_dat_o = {18'b0, dsr};
`endif
`ifdef OR1200_DU_DRR
                `OR1200_DU_OFS_DRR:
                        spr_dat_o = {18'b0, drr};
`endif
`ifdef OR1200_DU_TB_IMPLEMENTED
                `OR1200_DU_OFS_TBADR:
                        spr_dat_o = {24'h000000, tb_wadr};
                `OR1200_DU_OFS_TBIA:
                        spr_dat_o = tbia_dat_o;
                `OR1200_DU_OFS_TBIM:
                        spr_dat_o = tbim_dat_o;
                `OR1200_DU_OFS_TBAR:
                        spr_dat_o = tbar_dat_o;
                `OR1200_DU_OFS_TBTS:
                        spr_dat_o = tbts_dat_o;
`endif
                default:
                        spr_dat_o = 32'h0000_0000;
        endcase
`endif
 
//
// DSR alias
//
assign du_dsr = dsr;
 
`ifdef OR1200_DU_TB_IMPLEMENTED
//
// Simple trace buffer
// (right now hardcoded for Xilinx Virtex FPGAs)
//
// Stores last 256 instruction addresses, instruction
// machine words and ALU results
//
 
//
// Trace buffer write enable
//
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
 
//
// Trace buffer write address pointer
//
always @(posedge clk or posedge rst)
        if (rst)
                tb_wadr <= #1 8'h00;
        else if (tb_enw)
                tb_wadr <= #1 tb_wadr + 8'd1;
 
//
// Free running counter (time stamp)
//
always @(posedge clk or posedge rst)
        if (rst)
                tb_timstmp <= #1 32'h00000000;
        else if (!dbg_bp_r)
                tb_timstmp <= #1 tb_timstmp + 32'd1;
 
//
// Trace buffer RAMs
//
RAMB4_S16_S16 tbia_ramb4_s16_0(
        .CLKA(clk),
        .RSTA(rst),
        .ADDRA(tb_wadr),
        .DIA(spr_dat_npc[15:0]),
        .ENA(1'b1),
        .WEA(tb_enw),
        .DOA(),
 
        .CLKB(clk),
        .RSTB(rst),
        .ADDRB(spr_addr[7:0]),
        .DIB(16'h0000),
        .ENB(1'b1),
        .WEB(1'b0),
        .DOB(tbia_dat_o[15:0])
);
 
RAMB4_S16_S16 tbia_ramb4_s16_1(
        .CLKA(clk),
        .RSTA(rst),
        .ADDRA(tb_wadr),
        .DIA(spr_dat_npc[31:16]),
        .ENA(1'b1),
        .WEA(tb_enw),
        .DOA(),
 
        .CLKB(clk),
        .RSTB(rst),
        .ADDRB(spr_addr[7:0]),
        .DIB(16'h0000),
        .ENB(1'b1),
        .WEB(1'b0),
        .DOB(tbia_dat_o[31:16])
);
 
RAMB4_S16_S16 tbim_ramb4_s16_0(
        .CLKA(clk),
        .RSTA(rst),
        .ADDRA(tb_wadr),
        .DIA(ex_insn[15:0]),
        .ENA(1'b1),
        .WEA(tb_enw),
        .DOA(),
 
        .CLKB(clk),
        .RSTB(rst),
        .ADDRB(spr_addr[7:0]),
        .DIB(16'h0000),
        .ENB(1'b1),
        .WEB(1'b0),
        .DOB(tbim_dat_o[15:0])
);
 
RAMB4_S16_S16 tbim_ramb4_s16_1(
        .CLKA(clk),
        .RSTA(rst),
        .ADDRA(tb_wadr),
        .DIA(ex_insn[31:16]),
        .ENA(1'b1),
        .WEA(tb_enw),
        .DOA(),
 
        .CLKB(clk),
        .RSTB(rst),
        .ADDRB(spr_addr[7:0]),
        .DIB(16'h0000),
        .ENB(1'b1),
        .WEB(1'b0),
        .DOB(tbim_dat_o[31:16])
);
 
RAMB4_S16_S16 tbar_ramb4_s16_0(
        .CLKA(clk),
        .RSTA(rst),
        .ADDRA(tb_wadr),
        .DIA(rf_dataw[15:0]),
        .ENA(1'b1),
        .WEA(tb_enw),
        .DOA(),
 
        .CLKB(clk),
        .RSTB(rst),
        .ADDRB(spr_addr[7:0]),
        .DIB(16'h0000),
        .ENB(1'b1),
        .WEB(1'b0),
        .DOB(tbar_dat_o[15:0])
);
 
RAMB4_S16_S16 tbar_ramb4_s16_1(
        .CLKA(clk),
        .RSTA(rst),
        .ADDRA(tb_wadr),
        .DIA(rf_dataw[31:16]),
        .ENA(1'b1),
        .WEA(tb_enw),
        .DOA(),
 
        .CLKB(clk),
        .RSTB(rst),
        .ADDRB(spr_addr[7:0]),
        .DIB(16'h0000),
        .ENB(1'b1),
        .WEB(1'b0),
        .DOB(tbar_dat_o[31:16])
);
 
RAMB4_S16_S16 tbts_ramb4_s16_0(
        .CLKA(clk),
        .RSTA(rst),
        .ADDRA(tb_wadr),
        .DIA(tb_timstmp[15:0]),
        .ENA(1'b1),
        .WEA(tb_enw),
        .DOA(),
 
        .CLKB(clk),
        .RSTB(rst),
        .ADDRB(spr_addr[7:0]),
        .DIB(16'h0000),
        .ENB(1'b1),
        .WEB(1'b0),
        .DOB(tbts_dat_o[15:0])
);
 
RAMB4_S16_S16 tbts_ramb4_s16_1(
        .CLKA(clk),
        .RSTA(rst),
        .ADDRA(tb_wadr),
        .DIA(tb_timstmp[31:16]),
        .ENA(1'b1),
        .WEA(tb_enw),
        .DOA(),
 
        .CLKB(clk),
        .RSTB(rst),
        .ADDRB(spr_addr[7:0]),
        .DIB(16'h0000),
        .ENB(1'b1),
        .WEB(1'b0),
        .DOB(tbts_dat_o[31:16])
);
 
`else
assign tbia_dat_o = 32'h0000_0000;
assign tbim_dat_o = 32'h0000_0000;
assign tbar_dat_o = 32'h0000_0000;
assign tbts_dat_o = 32'h0000_0000;
 
`endif  // OR1200_DU_TB_IMPLEMENTED
 
`else   // OR1200_DU_IMPLEMENTED
 
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_bp_o = 1'b0;
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
 
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
assign spr_dat_o = 32'h0000_0000;
`ifdef OR1200_DU_UNUSED_ZERO
`endif
`endif
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Debug Unit ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Basic OR1200 debug unit. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	895	lampret	`// Revision 1.6 2002/03/14 00:30:24 lampret`
48			`// Added alternative for critical path in DU.`
49			`//`
50	737	lampret	`// Revision 1.5 2002/02/11 04:33:17 lampret`
51			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
52			`//`
53	660	lampret	`// Revision 1.4 2002/01/28 01:16:00 lampret`
54			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
55			`//`
56	617	lampret	`// Revision 1.3 2002/01/18 07:56:00 lampret`
57			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
58			`//`
59	589	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
60			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
61			`//`
62	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
63			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
64			`//`
65	504	lampret	`// Revision 1.12 2001/11/30 18:58:00 simons`
66			`// Trap insn couses break after exits ex_insn.`
67			`//`
68			`// Revision 1.11 2001/11/23 08:38:51 lampret`
69			`// Changed DSR/DRR behavior and exception detection.`
70			`//`
71			`// Revision 1.10 2001/11/20 21:25:44 lampret`
72			`// Fixed dbg_is_o assignment width.`
73			`//`
74			`// Revision 1.9 2001/11/20 18:46:14 simons`
75			`// Break point bug fixed`
76			`//`
77			`// Revision 1.8 2001/11/18 08:36:28 lampret`
78			`// For GDB changed single stepping and disabled trap exception.`
79			`//`
80			`// Revision 1.7 2001/10/21 18:09:53 lampret`
81			`// Fixed sensitivity list.`
82			`//`
83			`// Revision 1.6 2001/10/14 13:12:09 lampret`
84			`// MP3 version.`
85			`//`
86			`//`
87
88			`// synopsys translate_off`
89			`include "timescale.v"
90			`// synopsys translate_on`
91			`include "or1200_defines.v"
92
93			`//`
94			`// Debug unit`
95			`//`
96
97			`module or1200_du(`
98			`// RISC Internal Interface`
99			`clk, rst,`
100	895	lampret	`dcpu_cycstb_i, dcpu_we_i, icpu_cycstb_i,`
101			`ex_freeze, branch_op, ex_insn,`
102			`spr_dat_npc, rf_dataw,`
103			`du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,`
104			`du_read, du_write, du_except,`
105	504	lampret	`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
106
107			`// External Debug Interface`
108			`dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,`
109			`dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o`
110			`);`
111
112			parameter dw = `OR1200_OPERAND_WIDTH;
113			parameter aw = `OR1200_OPERAND_WIDTH;
114
115			`//`
116			`// I/O`
117			`//`
118
119			`//`
120			`// RISC Internal Interface`
121			`//`
122			`input clk; // Clock`
123			`input rst; // Reset`
124	660	lampret	`input dcpu_cycstb_i; // LSU status`
125	504	lampret	`input dcpu_we_i; // LSU status`
126	660	lampret	input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
127	504	lampret	`input ex_freeze; // EX stage freeze`
128			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
129			`input [dw-1:0] ex_insn; // EX insn`
130	895	lampret	`input [31:0] spr_dat_npc; // Next PC (for trace)`
131			`input [31:0] rf_dataw; // ALU result (for trace)`
132	504	lampret	output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
133			`output du_stall; // Debug Unit Stall`
134			`output [aw-1:0] du_addr; // Debug Unit Address`
135			`input [dw-1:0] du_dat_i; // Debug Unit Data In`
136			`output [dw-1:0] du_dat_o; // Debug Unit Data Out`
137			`output du_read; // Debug Unit Read Enable`
138			`output du_write; // Debug Unit Write Enable`
139			`input [12:0] du_except; // Exception masked by DSR`
140			`input spr_cs; // SPR Chip Select`
141			`input spr_write; // SPR Read/Write`
142			`input [aw-1:0] spr_addr; // SPR Address`
143			`input [dw-1:0] spr_dat_i; // SPR Data Input`
144			`output [dw-1:0] spr_dat_o; // SPR Data Output`
145
146			`//`
147			`// External Debug Interface`
148			`//`
149			`input dbg_stall_i; // External Stall Input`
150			`input [dw-1:0] dbg_dat_i; // External Data Input`
151			`input [aw-1:0] dbg_adr_i; // External Address Input`
152			`input [2:0] dbg_op_i; // External Operation Select Input`
153			`input dbg_ewt_i; // External Watchpoint Trigger Input`
154			`output [3:0] dbg_lss_o; // External Load/Store Unit Status`
155			`output [1:0] dbg_is_o; // External Insn Fetch Status`
156			`output [10:0] dbg_wp_o; // Watchpoints Outputs`
157			`output dbg_bp_o; // Breakpoint Output`
158			`output [dw-1:0] dbg_dat_o; // External Data Output`
159
160
161			`//`
162			`// Some connections go directly from the CPU through DU to Debug I/F`
163			`//`
164	737	lampret	`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
165			`assign dbg_lss_o = 4'b0000;`
166	895	lampret
167			`reg [1:0] dbg_is_o;`
168			`//`
169			`// Show insn activity (temp, must be removed)`
170			`//`
171			`always @(posedge clk or posedge rst)`
172			`if (rst)`
173			`dbg_is_o <= #1 2'b00;`
174			`else if (!ex_freeze &`
175			~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
176			`dbg_is_o <= #1 ~dbg_is_o;`
177			`ifdef UNUSED
178	737	lampret	`assign dbg_is_o = 2'b00;`
179	895	lampret	`endif
180	737	lampret	`else
181	660	lampret	`assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;`
182			`assign dbg_is_o = {1'b0, icpu_cycstb_i};`
183	737	lampret	`endif
184	504	lampret	`assign dbg_wp_o = 11'b000_0000_0000;`
185			`assign dbg_dat_o = du_dat_i;`
186
187			`//`
188			`// Some connections go directly from Debug I/F through DU to the CPU`
189			`//`
190			`assign du_stall = dbg_stall_i;`
191			`assign du_addr = dbg_adr_i;`
192			`assign du_dat_o = dbg_dat_i;`
193			assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
194			assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
195
196			`ifdef OR1200_DU_IMPLEMENTED
197
198			`//`
199			`// Debug Mode Register 1 (only ST and BT implemented)`
200			`//`
201			`ifdef OR1200_DU_DMR1
202			`reg [23:22] dmr1; // DMR1 implemented (ST & BT)`
203			`else
204			`wire [23:22] dmr1; // DMR1 not implemented`
205			`endif
206
207			`//`
208			`// Debug Mode Register 2 (not implemented)`
209			`//`
210			`ifdef OR1200_DU_DMR2
211			`wire [31:0] dmr2; // DMR not implemented`
212			`endif
213
214			`//`
215			`// Debug Stop Register`
216			`//`
217			`ifdef OR1200_DU_DSR
218			reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
219			`else
220			wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
221			`endif
222
223			`//`
224			`// Debug Reason Register`
225			`//`
226			`ifdef OR1200_DU_DRR
227			`reg [13:0] drr; // DRR implemented`
228			`else
229			`wire [13:0] drr; // DRR not implemented`
230			`endif
231
232			`//`
233			`// Internal wires`
234			`//`
235			`wire dmr1_sel; // DMR1 select`
236			`wire dsr_sel; // DSR select`
237			`wire drr_sel; // DRR select`
238			`reg dbg_bp_r;`
239			`ifdef OR1200_DU_READREGS
240			`reg [31:0] spr_dat_o;`
241			`endif
242			`reg [13:0] except_stop; // Exceptions that stop because of DSR`
243	895	lampret	`ifdef OR1200_DU_TB_IMPLEMENTED
244			`wire tb_enw;`
245			`reg [7:0] tb_wadr;`
246			`reg [31:0] tb_timstmp;`
247			`endif
248			`wire [31:0] tbia_dat_o;`
249			`wire [31:0] tbim_dat_o;`
250			`wire [31:0] tbar_dat_o;`
251			`wire [31:0] tbts_dat_o;`
252	504	lampret
253			`//`
254			`// DU registers address decoder`
255			`//`
256			`ifdef OR1200_DU_DMR1
257	895	lampret	assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DMR1));
258	504	lampret	`endif
259			`ifdef OR1200_DU_DSR
260	895	lampret	assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DSR));
261	504	lampret	`endif
262			`ifdef OR1200_DU_DRR
263	895	lampret	assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DRR));
264	504	lampret	`endif
265
266			`//`
267			`// Decode started exception`
268			`//`
269			`always @(du_except) begin`
270			`except_stop = 14'b0000_0000_0000;`
271			`casex (du_except)`
272	617	lampret	`13'b1_xxxx_xxxx_xxxx:`
273			except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
274			`13'b0_1xxx_xxxx_xxxx: begin`
275	589	lampret	except_stop[`OR1200_DU_DRR_IE] = 1'b1;
276	504	lampret	`end`
277	617	lampret	`13'b0_01xx_xxxx_xxxx: begin`
278	504	lampret	except_stop[`OR1200_DU_DRR_IME] = 1'b1;
279			`end`
280	617	lampret	`13'b0_001x_xxxx_xxxx:`
281	504	lampret	except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
282	617	lampret	`13'b0_0001_xxxx_xxxx: begin`
283	504	lampret	except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
284			`end`
285	617	lampret	`13'b0_0000_1xxx_xxxx:`
286	504	lampret	except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
287	617	lampret	`13'b0_0000_01xx_xxxx: begin`
288	504	lampret	except_stop[`OR1200_DU_DRR_AE] = 1'b1;
289			`end`
290	617	lampret	`13'b0_0000_001x_xxxx: begin`
291	504	lampret	except_stop[`OR1200_DU_DRR_DME] = 1'b1;
292			`end`
293	617	lampret	`13'b0_0000_0001_xxxx:`
294	504	lampret	except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
295	617	lampret	`13'b0_0000_0000_1xxx:`
296	504	lampret	except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
297			`13'b0_0000_0000_01xx: begin`
298			except_stop[`OR1200_DU_DRR_RE] = 1'b1;
299			`end`
300			`13'b0_0000_0000_001x: begin`
301			except_stop[`OR1200_DU_DRR_TE] = 1'b1;
302			`end`
303			`13'b0_0000_0000_0001:`
304			except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
305			`default:`
306			`except_stop = 14'b0000_0000_0000;`
307			`endcase`
308			`end`
309
310			`//`
311			`// dbg_bp_o is registered`
312			`//`
313			`assign dbg_bp_o = dbg_bp_r;`
314
315			`//`
316			`// Breakpoint activation register`
317			`//`
318			`always @(posedge clk or posedge rst)`
319			`if (rst)`
320			`dbg_bp_r <= #1 1'b0;`
321			`else if (!ex_freeze)`
322			`dbg_bp_r <= #1 \|except_stop`
323			`ifdef OR1200_DU_DMR1_ST
324	617	lampret	\| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
325	504	lampret	`endif
326			`ifdef OR1200_DU_DMR1_BT
327			\| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
328			`endif
329			`;`
330			`else`
331	562	lampret	`dbg_bp_r <= #1 \|except_stop;`
332	504	lampret
333			`//`
334			`// Write to DMR1`
335			`//`
336			`ifdef OR1200_DU_DMR1
337			`always @(posedge clk or posedge rst)`
338			`if (rst)`
339			`dmr1 <= 2'b00;`
340			`else if (dmr1_sel && spr_write)`
341			`dmr1 <= #1 spr_dat_i[23:22];`
342			`else
343			`assign dmr1 = 2'b00;`
344			`endif
345
346			`//`
347			`// DMR2 bits tied to zero`
348			`//`
349			`ifdef OR1200_DU_DMR2
350			`assign dmr2 = 32'h0000_0000;`
351			`endif
352
353			`//`
354			`// Write to DSR`
355			`//`
356			`ifdef OR1200_DU_DSR
357			`always @(posedge clk or posedge rst)`
358			`if (rst)`
359			dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
360			`else if (dsr_sel && spr_write)`
361			dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
362			`else
363			assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
364			`endif
365
366			`//`
367			`// Write to DRR`
368			`//`
369			`ifdef OR1200_DU_DRR
370			`always @(posedge clk or posedge rst)`
371			`if (rst)`
372			`drr <= 14'b0;`
373			`else if (drr_sel && spr_write)`
374			`drr <= #1 spr_dat_i[13:0];`
375			`else`
376			`drr <= #1 drr \| except_stop;`
377			`else
378			`assign drr = 14'b0;`
379			`endif
380
381			`//`
382			`// Read DU registers`
383			`//`
384			`ifdef OR1200_DU_READREGS
385	895	lampret	`always @(spr_addr or dsr or drr or dmr1 or dmr2 or`
386			`tbia_dat_o or tbim_dat_o or tbar_dat_o or tb_wadr)`
387			casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
388	504	lampret	`ifdef OR1200_DU_DMR1
389			`OR1200_DU_OFS_DMR1:
390			`spr_dat_o = {8'b0, dmr1, 22'b0};`
391			`endif
392			`ifdef OR1200_DU_DMR2
393			`OR1200_DU_OFS_DMR2:
394			`spr_dat_o = dmr2;`
395			`endif
396			`ifdef OR1200_DU_DSR
397			`OR1200_DU_OFS_DSR:
398			`spr_dat_o = {18'b0, dsr};`
399			`endif
400			`ifdef OR1200_DU_DRR
401			`OR1200_DU_OFS_DRR:
402			`spr_dat_o = {18'b0, drr};`
403			`endif
404	895	lampret	`ifdef OR1200_DU_TB_IMPLEMENTED
405			`OR1200_DU_OFS_TBADR:
406			`spr_dat_o = {24'h000000, tb_wadr};`
407			`OR1200_DU_OFS_TBIA:
408			`spr_dat_o = tbia_dat_o;`
409			`OR1200_DU_OFS_TBIM:
410			`spr_dat_o = tbim_dat_o;`
411			`OR1200_DU_OFS_TBAR:
412			`spr_dat_o = tbar_dat_o;`
413			`OR1200_DU_OFS_TBTS:
414			`spr_dat_o = tbts_dat_o;`
415			`endif
416	504	lampret	`default:`
417			`spr_dat_o = 32'h0000_0000;`
418			`endcase`
419			`endif
420
421			`//`
422			`// DSR alias`
423			`//`
424			`assign du_dsr = dsr;`
425
426	895	lampret	`ifdef OR1200_DU_TB_IMPLEMENTED
427			`//`
428			`// Simple trace buffer`
429			`// (right now hardcoded for Xilinx Virtex FPGAs)`
430			`//`
431			`// Stores last 256 instruction addresses, instruction`
432			`// machine words and ALU results`
433			`//`
434
435			`//`
436			`// Trace buffer write enable`
437			`//`
438			assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
439
440			`//`
441			`// Trace buffer write address pointer`
442			`//`
443			`always @(posedge clk or posedge rst)`
444			`if (rst)`
445			`tb_wadr <= #1 8'h00;`
446			`else if (tb_enw)`
447			`tb_wadr <= #1 tb_wadr + 8'd1;`
448
449			`//`
450			`// Free running counter (time stamp)`
451			`//`
452			`always @(posedge clk or posedge rst)`
453			`if (rst)`
454			`tb_timstmp <= #1 32'h00000000;`
455			`else if (!dbg_bp_r)`
456			`tb_timstmp <= #1 tb_timstmp + 32'd1;`
457
458			`//`
459			`// Trace buffer RAMs`
460			`//`
461			`RAMB4_S16_S16 tbia_ramb4_s16_0(`
462			`.CLKA(clk),`
463			`.RSTA(rst),`
464			`.ADDRA(tb_wadr),`
465			`.DIA(spr_dat_npc[15:0]),`
466			`.ENA(1'b1),`
467			`.WEA(tb_enw),`
468			`.DOA(),`
469
470			`.CLKB(clk),`
471			`.RSTB(rst),`
472			`.ADDRB(spr_addr[7:0]),`
473			`.DIB(16'h0000),`
474			`.ENB(1'b1),`
475			`.WEB(1'b0),`
476			`.DOB(tbia_dat_o[15:0])`
477			`);`
478
479			`RAMB4_S16_S16 tbia_ramb4_s16_1(`
480			`.CLKA(clk),`
481			`.RSTA(rst),`
482			`.ADDRA(tb_wadr),`
483			`.DIA(spr_dat_npc[31:16]),`
484			`.ENA(1'b1),`
485			`.WEA(tb_enw),`
486			`.DOA(),`
487
488			`.CLKB(clk),`
489			`.RSTB(rst),`
490			`.ADDRB(spr_addr[7:0]),`
491			`.DIB(16'h0000),`
492			`.ENB(1'b1),`
493			`.WEB(1'b0),`
494			`.DOB(tbia_dat_o[31:16])`
495			`);`
496
497			`RAMB4_S16_S16 tbim_ramb4_s16_0(`
498			`.CLKA(clk),`
499			`.RSTA(rst),`
500			`.ADDRA(tb_wadr),`

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