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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_DCFSM_IDLE       3'd0
`define OR1200_DCFSM_CLOAD      3'd1
`define OR1200_DCFSM_LREFILL3   3'd2
`define OR1200_DCFSM_CSTORE     3'd3
`define OR1200_DCFSM_SREFILL4   3'd4
`define OR1200_DCFSM_ILOAD      3'd5
`define OR1200_DCFSM_ISTORE     3'd6
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module or1200_dc_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level DC
        dc_en, dcdmmu_cyc_i, dcdmmu_stb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
        burst
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           dc_en;
input                           dcdmmu_cyc_i;
input                           dcdmmu_stb_i;
input                           dcdmmu_ci_i;
input                           dcpu_we_i;
input   [3:0]                    dcpu_sel_i;
input                           tagcomp_miss;
input                           biudata_valid;
input                           biudata_error;
input   [31:0]                   start_addr;
output  [31:0]                   saved_addr;
output  [3:0]                    dcram_we;
output                          biu_read;
output                          biu_write;
output                          first_hit_ack;
output                          first_miss_ack;
output                          first_miss_err;
output                          burst;
 
//
// Internal wires and regs
//
reg     [31:0]                   saved_addr;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             hitmiss_eval;
reg                             store;
reg                             load;
wire                            first_store_hit_ack;
 
//
// Generate of DCRAM write enables
//
assign dcram_we = {4{load & biudata_valid & (state != `OR1200_DCFSM_ILOAD)}} | {4{first_store_hit_ack}} & dcpu_sel_i;
 
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
assign biu_write = store;
 
//
// Assert for cache hit first word ready
// Assert for store cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss | first_store_hit_ack;
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid;
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE) | (state == `OR1200_DCFSM_ILOAD) | (state == `OR1200_DCFSM_ISTORE)) & biudata_valid;
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE) | (state == `OR1200_DCFSM_ILOAD) | (state == `OR1200_DCFSM_ISTORE)) & biudata_error;
 
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss
                | (state == `OR1200_DCFSM_LREFILL3)
`ifdef OR1200_DC_STORE_REFILL
                | (state == `OR1200_DCFSM_SREFILL4)
`endif
                ;
 
//
// Main DC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_DCFSM_IDLE;
                saved_addr <= #1 32'b0;
                hitmiss_eval <= #1 1'b0;
                store <= #1 1'b0;
                load <= #1 1'b0;
                cnt <= #1 3'b000;
        end
        else
        case (state)    // synopsys parallel_case
                `OR1200_DCFSM_IDLE :
                        if (dc_en & dcdmmu_ci_i & dcdmmu_cyc_i & dcdmmu_stb_i & dcpu_we_i) begin        // store to cache-inhibited area
                                state <= #1 `OR1200_DCFSM_ISTORE;
                                saved_addr <= #1 start_addr;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b1;
                                load <= #1 1'b0;
                        end
                        else if (dc_en & dcdmmu_ci_i & dcdmmu_cyc_i & dcdmmu_stb_i) begin       // load from cache-inhibited area
                                state <= #1 `OR1200_DCFSM_ILOAD;
                                saved_addr <= #1 start_addr;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                        end
                        else if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i & dcpu_we_i) begin // store to cached area
                                state <= #1 `OR1200_DCFSM_CSTORE;
                                saved_addr <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                store <= #1 1'b1;
                                load <= #1 1'b0;
                        end
                        else if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i) begin             // load from cached area
                                state <= #1 `OR1200_DCFSM_CLOAD;
                                saved_addr <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                        end
                        else begin                                                      // idle
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                `OR1200_DCFSM_CLOAD:            // load from cached area
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin   // load aborted (usually caused by DMMU)
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // load terminated with an error
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else if (tagcomp_miss & biudata_valid) begin    // load missed, finish current external load and refill
                                state <= #1 `OR1200_DCFSM_LREFILL3;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                hitmiss_eval <= #1 1'b0;
                                cnt <= #1 `OR1200_DCLS-2;
                        end
                        else if (!tagcomp_miss) begin                   // load hit, finish immediately
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else                                            // load in-progress
                                hitmiss_eval <= #1 1'b0;
                `OR1200_DCFSM_LREFILL3 : begin
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (biudata_valid && (|cnt)) begin         // refill ack, more loads to come
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                        end
                end
                `OR1200_DCFSM_CSTORE:           // store to cached area
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin   // store aborted (usually caused by DMMU)
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // store terminated with an error
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                        end
`ifdef OR1200_DC_STORE_REFILL
                        else if (tagcomp_miss & biudata_valid) begin    // store missed, finish write-through and do load refill
                                state <= #1 `OR1200_DCFSM_SREFILL4;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                                cnt <= #1 `OR1200_DCLS-1;
                        end
`endif
                        else if (biudata_valid) begin                   // store hit, finish write-through
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                        end
                        else                                            // store write-through in-progress
                                hitmiss_eval <= #1 1'b0;
`ifdef OR1200_DC_STORE_REFILL
                `OR1200_DCFSM_SREFILL4 : begin
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (biudata_valid && (|cnt)) begin         // refill ack, more loads to come
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                        end
                end
`endif
                `OR1200_DCFSM_ILOAD:            // load from cache-inhibited area
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (!(dcdmmu_cyc_i & dcdmmu_stb_i)) begin  // load aborted (usually caused by DMMU)
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // load terminated with an error
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else if (biudata_valid) begin                   // load from cache inhibit page
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else                                            // load in-progress
                                hitmiss_eval <= #1 1'b0;
                `OR1200_DCFSM_ISTORE:           // store to cache-inhibited area
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (!(dcdmmu_cyc_i & dcdmmu_stb_i)) begin  // store aborted (usually caused by DMMU)
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // store terminated with an error
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                        end
                        else if (biudata_valid) begin                   // store to cache inhibit page
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                        end
                        else                                            // store write-through in-progress
                                hitmiss_eval <= #1 1'b0;
                default:
                        state <= #1 `OR1200_DCFSM_IDLE;
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	636	lampret	`// Revision 1.3 2002/01/28 01:15:59 lampret`
48			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
49			`//`
50	617	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
51			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
52			`//`
53	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
54			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
55			`//`
56	504	lampret	`// Revision 1.9 2001/10/21 17:57:16 lampret`
57			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
58			`//`
59			`// Revision 1.8 2001/10/19 23:28:46 lampret`
60			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
61			`//`
62			`// Revision 1.7 2001/10/14 13:12:09 lampret`
63			`// MP3 version.`
64			`//`
65			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
66			`// no message`
67			`//`
68			`// Revision 1.2 2001/08/09 13:39:33 lampret`
69			`// Major clean-up.`
70			`//`
71			`// Revision 1.1 2001/07/20 00:46:03 lampret`
72			`// Development version of RTL. Libraries are missing.`
73			`//`
74			`//`
75
76			`// synopsys translate_off`
77			`include "timescale.v"
78			`// synopsys translate_on`
79			`include "or1200_defines.v"
80
81			`define OR1200_DCFSM_IDLE 3'd0
82	636	lampret	`define OR1200_DCFSM_CLOAD 3'd1
83	504	lampret	`define OR1200_DCFSM_LREFILL3 3'd2
84	636	lampret	`define OR1200_DCFSM_CSTORE 3'd3
85	504	lampret	`define OR1200_DCFSM_SREFILL4 3'd4
86	636	lampret	`define OR1200_DCFSM_ILOAD 3'd5
87			`define OR1200_DCFSM_ISTORE 3'd6
88	504	lampret
89			`//`
90			`// Data cache FSM for cache line of 16 bytes (4x singleword)`
91			`//`
92
93			`module or1200_dc_fsm(`
94			`// Clock and reset`
95			`clk, rst,`
96
97			`// Internal i/f to top level DC`
98			`dc_en, dcdmmu_cyc_i, dcdmmu_stb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,`
99			`tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,`
100			`dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,`
101			`burst`
102			`);`
103
104			`//`
105			`// I/O`
106			`//`
107			`input clk;`
108			`input rst;`
109			`input dc_en;`
110			`input dcdmmu_cyc_i;`
111			`input dcdmmu_stb_i;`
112			`input dcdmmu_ci_i;`
113			`input dcpu_we_i;`
114			`input [3:0] dcpu_sel_i;`
115			`input tagcomp_miss;`
116			`input biudata_valid;`
117			`input biudata_error;`
118			`input [31:0] start_addr;`
119			`output [31:0] saved_addr;`
120			`output [3:0] dcram_we;`
121			`output biu_read;`
122			`output biu_write;`
123			`output first_hit_ack;`
124			`output first_miss_ack;`
125			`output first_miss_err;`
126			`output burst;`
127
128			`//`
129			`// Internal wires and regs`
130			`//`
131			`reg [31:0] saved_addr;`
132			`reg [2:0] state;`
133			`reg [2:0] cnt;`
134			`reg hitmiss_eval;`
135			`reg store;`
136			`reg load;`
137	636	lampret	`wire first_store_hit_ack;`
138	504	lampret
139			`//`
140			`// Generate of DCRAM write enables`
141			`//`
142	636	lampret	assign dcram_we = {4{load & biudata_valid & (state != `OR1200_DCFSM_ILOAD)}} \| {4{first_store_hit_ack}} & dcpu_sel_i;
143	504	lampret
144			`//`
145			`// BIU read and write`
146			`//`
147			`assign biu_read = (hitmiss_eval & tagcomp_miss) \| (!hitmiss_eval & load);`
148			`assign biu_write = store;`
149
150			`//`
151			`// Assert for cache hit first word ready`
152	636	lampret	`// Assert for store cache hit first word ready`
153	504	lampret	`// Assert for cache miss first word stored/loaded OK`
154			`// Assert for cache miss first word stored/loaded with an error`
155			`//`
156	636	lampret	assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss \| first_store_hit_ack;
157			assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid;
158			assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) \| (state == `OR1200_DCFSM_CSTORE) \| (state == `OR1200_DCFSM_ILOAD) \| (state == `OR1200_DCFSM_ISTORE)) & biudata_valid;
159			assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) \| (state == `OR1200_DCFSM_CSTORE) \| (state == `OR1200_DCFSM_ILOAD) \| (state == `OR1200_DCFSM_ISTORE)) & biudata_error;
160	504	lampret
161			`//`
162			`// Assert burst when doing reload of complete cache line`
163			`//`
164	636	lampret	assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss
165			\| (state == `OR1200_DCFSM_LREFILL3)
166			`ifdef OR1200_DC_STORE_REFILL
167			\| (state == `OR1200_DCFSM_SREFILL4)
168			`endif
169			`;`
170	504	lampret
171			`//`
172			`// Main DC FSM`
173			`//`
174			`always @(posedge clk or posedge rst) begin`
175			`if (rst) begin`
176			state <= #1 `OR1200_DCFSM_IDLE;
177			`saved_addr <= #1 32'b0;`
178			`hitmiss_eval <= #1 1'b0;`
179			`store <= #1 1'b0;`
180			`load <= #1 1'b0;`
181			`cnt <= #1 3'b000;`
182			`end`
183			`else`
184			`case (state) // synopsys parallel_case`
185			`OR1200_DCFSM_IDLE :
186	636	lampret	`if (dc_en & dcdmmu_ci_i & dcdmmu_cyc_i & dcdmmu_stb_i & dcpu_we_i) begin // store to cache-inhibited area`
187			state <= #1 `OR1200_DCFSM_ISTORE;
188	504	lampret	`saved_addr <= #1 start_addr;`
189	636	lampret	`hitmiss_eval <= #1 1'b0;`
190			`store <= #1 1'b1;`
191			`load <= #1 1'b0;`
192			`end`
193			`else if (dc_en & dcdmmu_ci_i & dcdmmu_cyc_i & dcdmmu_stb_i) begin // load from cache-inhibited area`
194			state <= #1 `OR1200_DCFSM_ILOAD;
195			`saved_addr <= #1 start_addr;`
196			`hitmiss_eval <= #1 1'b0;`
197			`store <= #1 1'b0;`
198			`load <= #1 1'b1;`
199			`end`
200			`else if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i & dcpu_we_i) begin // store to cached area`
201			state <= #1 `OR1200_DCFSM_CSTORE;
202			`saved_addr <= #1 start_addr;`
203	504	lampret	`hitmiss_eval <= #1 1'b1;`
204			`store <= #1 1'b1;`
205			`load <= #1 1'b0;`
206			`end`
207	636	lampret	`else if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i) begin // load from cached area`
208			state <= #1 `OR1200_DCFSM_CLOAD;
209	504	lampret	`saved_addr <= #1 start_addr;`
210			`hitmiss_eval <= #1 1'b1;`
211			`store <= #1 1'b0;`
212			`load <= #1 1'b1;`
213			`end`
214			`else begin // idle`
215			state <= #1 `OR1200_DCFSM_IDLE;
216			`hitmiss_eval <= #1 1'b0;`
217			`store <= #1 1'b0;`
218			`load <= #1 1'b0;`
219			`end`
220	636	lampret	`OR1200_DCFSM_CLOAD: // load from cached area
221	617	lampret	`if (!dc_en)`
222	504	lampret	state <= #1 `OR1200_DCFSM_IDLE;
223	617	lampret	`else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)`
224			state <= #1 `OR1200_DCFSM_IDLE;
225	504	lampret	`hitmiss_eval <= #1 1'b0;`
226			`load <= #1 1'b0;`
227			`end`
228	562	lampret	`else if (biudata_error) begin // load terminated with an error`
229			state <= #1 `OR1200_DCFSM_IDLE;
230			`hitmiss_eval <= #1 1'b0;`
231			`load <= #1 1'b0;`
232			`end`
233	504	lampret	`else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill`
234			state <= #1 `OR1200_DCFSM_LREFILL3;
235			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
236			`hitmiss_eval <= #1 1'b0;`
237			cnt <= #1 `OR1200_DCLS-2;
238			`end`
239	636	lampret	`else if (!tagcomp_miss) begin // load hit, finish immediately`
240	504	lampret	state <= #1 `OR1200_DCFSM_IDLE;
241			`hitmiss_eval <= #1 1'b0;`
242			`load <= #1 1'b0;`
243			`end`
244			`else // load in-progress`
245			`hitmiss_eval <= #1 1'b0;`
246			`OR1200_DCFSM_LREFILL3 : begin
247	617	lampret	`if (!dc_en)`
248			state <= #1 `OR1200_DCFSM_IDLE;
249			`else if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
250	504	lampret	`cnt <= #1 cnt - 'd1;`
251			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
252			`end`
253			`else if (biudata_valid) begin // last load of line refill`
254			state <= #1 `OR1200_DCFSM_IDLE;
255			`load <= #1 1'b0;`
256			`end`
257			`end`
258	636	lampret	`OR1200_DCFSM_CSTORE: // store to cached area
259	617	lampret	`if (!dc_en)`
260	504	lampret	state <= #1 `OR1200_DCFSM_IDLE;
261	617	lampret	`else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)`
262			state <= #1 `OR1200_DCFSM_IDLE;
263	504	lampret	`hitmiss_eval <= #1 1'b0;`
264			`store <= #1 1'b0;`
265			`end`
266	562	lampret	`else if (biudata_error) begin // store terminated with an error`
267			state <= #1 `OR1200_DCFSM_IDLE;
268			`hitmiss_eval <= #1 1'b0;`
269			`store <= #1 1'b0;`
270			`end`
271	636	lampret	`ifdef OR1200_DC_STORE_REFILL
272	504	lampret	`else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill`
273			state <= #1 `OR1200_DCFSM_SREFILL4;
274			`hitmiss_eval <= #1 1'b0;`
275			`store <= #1 1'b0;`
276			`load <= #1 1'b1;`
277			cnt <= #1 `OR1200_DCLS-1;
278			`end`
279	636	lampret	`endif
280	504	lampret	`else if (biudata_valid) begin // store hit, finish write-through`
281			state <= #1 `OR1200_DCFSM_IDLE;
282			`hitmiss_eval <= #1 1'b0;`
283			`store <= #1 1'b0;`
284			`end`
285			`else // store write-through in-progress`
286			`hitmiss_eval <= #1 1'b0;`
287	636	lampret	`ifdef OR1200_DC_STORE_REFILL
288	504	lampret	`OR1200_DCFSM_SREFILL4 : begin
289	617	lampret	`if (!dc_en)`
290			state <= #1 `OR1200_DCFSM_IDLE;
291			`else if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
292	504	lampret	`cnt <= #1 cnt - 'd1;`
293			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
294			`end`
295			`else if (biudata_valid) begin // last load of line refill`
296			state <= #1 `OR1200_DCFSM_IDLE;
297			`load <= #1 1'b0;`
298			`end`
299			`end`
300	636	lampret	`endif
301			`OR1200_DCFSM_ILOAD: // load from cache-inhibited area
302			`if (!dc_en)`
303			state <= #1 `OR1200_DCFSM_IDLE;
304			`else if (!(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)`
305			state <= #1 `OR1200_DCFSM_IDLE;
306			`hitmiss_eval <= #1 1'b0;`
307			`load <= #1 1'b0;`
308			`end`
309			`else if (biudata_error) begin // load terminated with an error`
310			state <= #1 `OR1200_DCFSM_IDLE;
311			`hitmiss_eval <= #1 1'b0;`
312			`load <= #1 1'b0;`
313			`end`
314			`else if (biudata_valid) begin // load from cache inhibit page`
315			state <= #1 `OR1200_DCFSM_IDLE;
316			`hitmiss_eval <= #1 1'b0;`
317			`load <= #1 1'b0;`
318			`end`
319			`else // load in-progress`
320			`hitmiss_eval <= #1 1'b0;`
321			`OR1200_DCFSM_ISTORE: // store to cache-inhibited area
322			`if (!dc_en)`
323			state <= #1 `OR1200_DCFSM_IDLE;
324			`else if (!(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)`
325			state <= #1 `OR1200_DCFSM_IDLE;
326			`hitmiss_eval <= #1 1'b0;`
327			`store <= #1 1'b0;`
328			`end`
329			`else if (biudata_error) begin // store terminated with an error`
330			state <= #1 `OR1200_DCFSM_IDLE;
331			`hitmiss_eval <= #1 1'b0;`
332			`store <= #1 1'b0;`
333			`end`
334			`else if (biudata_valid) begin // store to cache inhibit page`
335			state <= #1 `OR1200_DCFSM_IDLE;
336			`hitmiss_eval <= #1 1'b0;`
337			`store <= #1 1'b0;`
338			`end`
339			`else // store write-through in-progress`
340			`hitmiss_eval <= #1 1'b0;`
341	504	lampret	`default:`
342			state <= #1 `OR1200_DCFSM_IDLE;
343			`endcase`
344			`end`
345
346			`endmodule`

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