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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's IC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.3  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_ICFSM_IDLE       3'd0
`define OR1200_ICFSM_CFETCH     3'd1
`define OR1200_ICFSM_LREFILL3   3'd2
`define OR1200_ICFSM_IFETCH     3'd3
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module or1200_ic_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level IC
        ic_en, icimmu_cycstb_i, icimmu_ci_i, icpu_sel_i,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
        burst, tag_we
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           ic_en;
input                           icimmu_cycstb_i;
input                           icimmu_ci_i;
input   [3:0]                    icpu_sel_i;
input                           tagcomp_miss;
input                           biudata_valid;
input                           biudata_error;
input   [31:0]                   start_addr;
output  [31:0]                   saved_addr;
output  [3:0]                    icram_we;
output                          biu_read;
output                          first_hit_ack;
output                          first_miss_ack;
output                          first_miss_err;
output                          burst;
output                          tag_we;
 
//
// Internal wires and regs
//
reg     [31:0]                   saved_addr_r;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             hitmiss_eval;
reg                             load;
reg                             cache_inhibit;
 
//
// Generate of ICRAM write enables
//
assign icram_we = {4{load & biudata_valid & !cache_inhibit}};
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
 
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
 
//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
assign saved_addr = saved_addr_r;
 
//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icimmu_ci_i;
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
 
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit
                | (state == `OR1200_ICFSM_LREFILL3);
 
//
// Main IC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_ICFSM_IDLE;
                saved_addr_r <= #1 32'b0;
                hitmiss_eval <= #1 1'b0;
                load <= #1 1'b0;
                cnt <= #1 3'b000;
                cache_inhibit <= #1 1'b0;
        end
        else
        case (state)    // synopsys parallel_case
                `OR1200_ICFSM_IDLE :
                        if (ic_en & icimmu_cycstb_i) begin              // fetch
                                state <= #1 `OR1200_ICFSM_CFETCH;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                load <= #1 1'b1;
                                cache_inhibit <= #1 1'b0;
                        end
                        else begin                                                      // idle
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                `OR1200_ICFSM_CFETCH: begin     // fetch
                        if (icimmu_cycstb_i & icimmu_ci_i)
                                cache_inhibit <= #1 1'b1;
                        if (hitmiss_eval)
                                saved_addr_r[31:13] <= #1 start_addr[31:13];
                        if (!ic_en)
                                state <= #1 `OR1200_ICFSM_IDLE;
                        else if (hitmiss_eval & !icimmu_cycstb_i) begin // fetch aborted (usually caused by IMMU)
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // fetch terminated with an error
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (cache_inhibit & biudata_valid) begin   // fetch from cache-inhibited page
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (tagcomp_miss & biudata_valid) begin    // fetch missed, finish current external fetch and refill
                                state <= #1 `OR1200_ICFSM_LREFILL3;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
                                hitmiss_eval <= #1 1'b0;
                                cnt <= #1 `OR1200_ICLS-2;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (!tagcomp_miss & !icimmu_ci_i) begin    // fetch hit, finish immediately
                                state <= #1 `OR1200_ICFSM_CFETCH;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                load <= #1 1'b1;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (!icimmu_cycstb_i) begin        // fetch aborted (usually caused by exception)
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else                                            // fetch in-progress
                                hitmiss_eval <= #1 1'b0;
                end
                `OR1200_ICFSM_LREFILL3 : begin
                        if (!ic_en)
                                state <= #1 `OR1200_ICFSM_IDLE;
                        else if (biudata_valid && (|cnt)) begin         // refill ack, more fetchs to come
                                cnt <= #1 cnt - 'd1;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
                        end
                        else if (biudata_valid) begin                   // last fetch of line refill
                                state <= #1 `OR1200_ICFSM_IDLE;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                end
                default:
                        state <= #1 `OR1200_ICFSM_IDLE;
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's IC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	660	lampret	`// Revision 1.4 2002/02/01 19:56:54 lampret`
48			`// Fixed combinational loops.`
49			`//`
50	636	lampret	`// Revision 1.3 2002/01/28 01:16:00 lampret`
51			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
52			`//`
53	617	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
54			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
55			`//`
56	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
57			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
58			`//`
59	504	lampret	`// Revision 1.9 2001/10/21 17:57:16 lampret`
60			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.`
61			`//`
62			`// Revision 1.8 2001/10/19 23:28:46 lampret`
63			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
64			`//`
65			`// Revision 1.7 2001/10/14 13:12:09 lampret`
66			`// MP3 version.`
67			`//`
68			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
69			`// no message`
70			`//`
71			`// Revision 1.2 2001/08/09 13:39:33 lampret`
72			`// Major clean-up.`
73			`//`
74			`// Revision 1.1 2001/07/20 00:46:03 lampret`
75			`// Development version of RTL. Libraries are missing.`
76			`//`
77			`//`
78
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82			`include "or1200_defines.v"
83
84			`define OR1200_ICFSM_IDLE 3'd0
85	636	lampret	`define OR1200_ICFSM_CFETCH 3'd1
86	504	lampret	`define OR1200_ICFSM_LREFILL3 3'd2
87	636	lampret	`define OR1200_ICFSM_IFETCH 3'd3
88	504	lampret
89			`//`
90			`// Data cache FSM for cache line of 16 bytes (4x singleword)`
91			`//`
92
93			`module or1200_ic_fsm(`
94			`// Clock and reset`
95			`clk, rst,`
96
97			`// Internal i/f to top level IC`
98	660	lampret	`ic_en, icimmu_cycstb_i, icimmu_ci_i, icpu_sel_i,`
99	504	lampret	`tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,`
100			`icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,`
101	660	lampret	`burst, tag_we`
102	504	lampret	`);`
103
104			`//`
105			`// I/O`
106			`//`
107			`input clk;`
108			`input rst;`
109			`input ic_en;`
110	660	lampret	`input icimmu_cycstb_i;`
111	504	lampret	`input icimmu_ci_i;`
112			`input [3:0] icpu_sel_i;`
113			`input tagcomp_miss;`
114			`input biudata_valid;`
115			`input biudata_error;`
116			`input [31:0] start_addr;`
117			`output [31:0] saved_addr;`
118			`output [3:0] icram_we;`
119			`output biu_read;`
120			`output first_hit_ack;`
121			`output first_miss_ack;`
122			`output first_miss_err;`
123			`output burst;`
124	660	lampret	`output tag_we;`
125	504	lampret
126			`//`
127			`// Internal wires and regs`
128			`//`
129	660	lampret	`reg [31:0] saved_addr_r;`
130	504	lampret	`reg [2:0] state;`
131			`reg [2:0] cnt;`
132			`reg hitmiss_eval;`
133			`reg load;`
134	660	lampret	`reg cache_inhibit;`
135	504	lampret
136			`//`
137			`// Generate of ICRAM write enables`
138			`//`
139	660	lampret	`assign icram_we = {4{load & biudata_valid & !cache_inhibit}};`
140			`assign tag_we = biu_read & biudata_valid & !cache_inhibit;`
141	504	lampret
142			`//`
143			`// BIU read and write`
144			`//`
145			`assign biu_read = (hitmiss_eval & tagcomp_miss) \| (!hitmiss_eval & load);`
146
147	660	lampret	`//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;`
148			`assign saved_addr = saved_addr_r;`
149
150	504	lampret	`//`
151			`// Assert for cache hit first word ready`
152			`// Assert for cache miss first word stored/loaded OK`
153			`// Assert for cache miss first word stored/loaded with an error`
154			`//`
155	660	lampret	assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icimmu_ci_i;
156			assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
157			assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
158	504	lampret
159			`//`
160			`// Assert burst when doing reload of complete cache line`
161			`//`
162	660	lampret	assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit
163	504	lampret	\| (state == `OR1200_ICFSM_LREFILL3);
164
165			`//`
166			`// Main IC FSM`
167			`//`
168			`always @(posedge clk or posedge rst) begin`
169			`if (rst) begin`
170			state <= #1 `OR1200_ICFSM_IDLE;
171	660	lampret	`saved_addr_r <= #1 32'b0;`
172	504	lampret	`hitmiss_eval <= #1 1'b0;`
173			`load <= #1 1'b0;`
174			`cnt <= #1 3'b000;`
175	660	lampret	`cache_inhibit <= #1 1'b0;`
176	504	lampret	`end`
177			`else`
178			`case (state) // synopsys parallel_case`
179			`OR1200_ICFSM_IDLE :
180	660	lampret	`if (ic_en & icimmu_cycstb_i) begin // fetch`
181	636	lampret	state <= #1 `OR1200_ICFSM_CFETCH;
182	660	lampret	`saved_addr_r <= #1 start_addr;`
183	504	lampret	`hitmiss_eval <= #1 1'b1;`
184			`load <= #1 1'b1;`
185	660	lampret	`cache_inhibit <= #1 1'b0;`
186	504	lampret	`end`
187			`else begin // idle`
188			state <= #1 `OR1200_ICFSM_IDLE;
189			`hitmiss_eval <= #1 1'b0;`
190			`load <= #1 1'b0;`
191	660	lampret	`cache_inhibit <= #1 1'b0;`
192	504	lampret	`end`
193	660	lampret	`OR1200_ICFSM_CFETCH: begin // fetch
194			`if (icimmu_cycstb_i & icimmu_ci_i)`
195			`cache_inhibit <= #1 1'b1;`
196			`if (hitmiss_eval)`
197			`saved_addr_r[31:13] <= #1 start_addr[31:13];`
198	617	lampret	`if (!ic_en)`
199	504	lampret	state <= #1 `OR1200_ICFSM_IDLE;
200	660	lampret	`else if (hitmiss_eval & !icimmu_cycstb_i) begin // fetch aborted (usually caused by IMMU)`
201	617	lampret	state <= #1 `OR1200_ICFSM_IDLE;
202	504	lampret	`hitmiss_eval <= #1 1'b0;`
203			`load <= #1 1'b0;`
204	660	lampret	`cache_inhibit <= #1 1'b0;`
205	504	lampret	`end`
206	636	lampret	`else if (biudata_error) begin // fetch terminated with an error`
207	504	lampret	state <= #1 `OR1200_ICFSM_IDLE;
208			`hitmiss_eval <= #1 1'b0;`
209			`load <= #1 1'b0;`
210	660	lampret	`cache_inhibit <= #1 1'b0;`
211	504	lampret	`end`
212	660	lampret	`else if (cache_inhibit & biudata_valid) begin // fetch from cache-inhibited page`
213			state <= #1 `OR1200_ICFSM_IDLE;
214			`hitmiss_eval <= #1 1'b0;`
215			`load <= #1 1'b0;`
216			`cache_inhibit <= #1 1'b0;`
217			`end`
218	636	lampret	`else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill`
219	504	lampret	state <= #1 `OR1200_ICFSM_LREFILL3;
220	660	lampret	`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;`
221	504	lampret	`hitmiss_eval <= #1 1'b0;`
222			cnt <= #1 `OR1200_ICLS-2;
223	660	lampret	`cache_inhibit <= #1 1'b0;`
224	504	lampret	`end`
225	660	lampret	`else if (!tagcomp_miss & !icimmu_ci_i) begin // fetch hit, finish immediately`
226	636	lampret	state <= #1 `OR1200_ICFSM_CFETCH;
227	660	lampret	`saved_addr_r <= #1 start_addr;`
228	504	lampret	`hitmiss_eval <= #1 1'b1;`
229			`load <= #1 1'b1;`
230	660	lampret	`cache_inhibit <= #1 1'b0;`
231	504	lampret	`end`
232	660	lampret	`else if (!icimmu_cycstb_i) begin // fetch aborted (usually caused by exception)`
233	562	lampret	state <= #1 `OR1200_ICFSM_IDLE;
234			`hitmiss_eval <= #1 1'b0;`
235			`load <= #1 1'b0;`
236	660	lampret	`cache_inhibit <= #1 1'b0;`
237	562	lampret	`end`
238	636	lampret	`else // fetch in-progress`
239	504	lampret	`hitmiss_eval <= #1 1'b0;`
240	660	lampret	`end`
241	504	lampret	`OR1200_ICFSM_LREFILL3 : begin
242	617	lampret	`if (!ic_en)`
243			state <= #1 `OR1200_ICFSM_IDLE;
244	636	lampret	`else if (biudata_valid && (\|cnt)) begin // refill ack, more fetchs to come`
245	504	lampret	`cnt <= #1 cnt - 'd1;`
246	660	lampret	`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;`
247	504	lampret	`end`
248	636	lampret	`else if (biudata_valid) begin // last fetch of line refill`
249	504	lampret	state <= #1 `OR1200_ICFSM_IDLE;
250	660	lampret	`saved_addr_r <= #1 start_addr;`
251	504	lampret	`hitmiss_eval <= #1 1'b0;`
252			`load <= #1 1'b0;`
253			`end`
254			`end`
255			`default:`
256			state <= #1 `OR1200_ICFSM_IDLE;
257			`endcase`
258			`end`
259
260			`endmodule`

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