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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_DCFSM_IDLE       3'd0
`define OR1200_DCFSM_DOLOAD     3'd1
`define OR1200_DCFSM_LREFILL3   3'd2
`define OR1200_DCFSM_DOSTORE    3'd3
`define OR1200_DCFSM_SREFILL4   3'd4
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module or1200_dc_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level DC
        dc_en, dcdmmu_cyc_i, dcdmmu_stb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
        burst
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           dc_en;
input                           dcdmmu_cyc_i;
input                           dcdmmu_stb_i;
input                           dcdmmu_ci_i;
input                           dcpu_we_i;
input   [3:0]                    dcpu_sel_i;
input                           tagcomp_miss;
input                           biudata_valid;
input                           biudata_error;
input   [31:0]                   start_addr;
output  [31:0]                   saved_addr;
output  [3:0]                    dcram_we;
output                          biu_read;
output                          biu_write;
output                          first_hit_ack;
output                          first_miss_ack;
output                          first_miss_err;
output                          burst;
 
//
// Internal wires and regs
//
reg     [31:0]                   saved_addr;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             hitmiss_eval;
reg                             store;
reg                             load;
 
//
// Generate of DCRAM write enables
//
assign dcram_we = {4{load & biudata_valid}} | {4{store & biudata_valid}} & dcpu_sel_i;
 
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
assign biu_write = store;
 
//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_DCFSM_DOLOAD) & !tagcomp_miss & !dcdmmu_ci_i | (state == `OR1200_DCFSM_DOSTORE) & !tagcomp_miss & biudata_valid;
assign first_miss_ack = ((state == `OR1200_DCFSM_DOLOAD) | (state == `OR1200_DCFSM_DOSTORE)) & (tagcomp_miss | dcdmmu_ci_i) & biudata_valid;
assign first_miss_err = ((state == `OR1200_DCFSM_DOLOAD) | (state == `OR1200_DCFSM_DOSTORE)) & (tagcomp_miss | dcdmmu_ci_i) & biudata_error;
 
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_DCFSM_DOLOAD) & tagcomp_miss
                | (state == `OR1200_DCFSM_LREFILL3) | (state == `OR1200_DCFSM_SREFILL4);
 
//
// Main DC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_DCFSM_IDLE;
                saved_addr <= #1 32'b0;
                hitmiss_eval <= #1 1'b0;
                store <= #1 1'b0;
                load <= #1 1'b0;
                cnt <= #1 3'b000;
        end
        else
        case (state)    // synopsys parallel_case
                `OR1200_DCFSM_IDLE :
                        if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i & dcpu_we_i) begin      // store
                                state <= #1 `OR1200_DCFSM_DOSTORE;
                                saved_addr <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                store <= #1 1'b1;
                                load <= #1 1'b0;
                        end
                        else if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i) begin             // load
                                state <= #1 `OR1200_DCFSM_DOLOAD;
                                saved_addr <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                        end
                        else begin                                                      // idle
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                `OR1200_DCFSM_DOLOAD:
                        if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin        // load aborted (usually caused by DMMU)
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // load terminated with an error
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else if (dcdmmu_ci_i & biudata_valid) begin     // load from cache inhibit page
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else if (tagcomp_miss & biudata_valid) begin    // load missed, finish current external load and refill
                                state <= #1 `OR1200_DCFSM_LREFILL3;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                hitmiss_eval <= #1 1'b0;
                                cnt <= #1 `OR1200_DCLS-2;
                        end
                        else if (!tagcomp_miss & !dcdmmu_ci_i) begin    // load hit and not cache inhibit, finish immediately
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else                                            // load in-progress
                                hitmiss_eval <= #1 1'b0;
                `OR1200_DCFSM_LREFILL3 : begin
                        if (biudata_valid && (|cnt)) begin              // refill ack, more loads to come
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                        end
                end
                `OR1200_DCFSM_DOSTORE:
                        if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin        // store aborted (usually caused by DMMU)
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // store terminated with an error
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                        end
                        else if (dcdmmu_ci_i & biudata_valid) begin     // store to cache inhibit page
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                        end
                        else if (tagcomp_miss & biudata_valid) begin    // store missed, finish write-through and do load refill
                                state <= #1 `OR1200_DCFSM_SREFILL4;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                                cnt <= #1 `OR1200_DCLS-1;
                        end
                        else if (biudata_valid) begin                   // store hit, finish write-through
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                        end
                        else                                            // store write-through in-progress
                                hitmiss_eval <= #1 1'b0;
                `OR1200_DCFSM_SREFILL4 : begin
                        if (biudata_valid && (|cnt)) begin              // refill ack, more loads to come
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                        end
                end
                default:
                        state <= #1 `OR1200_DCFSM_IDLE;
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50	504	lampret	`// Revision 1.9 2001/10/21 17:57:16 lampret`
51			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
52			`//`
53			`// Revision 1.8 2001/10/19 23:28:46 lampret`
54			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
55			`//`
56			`// Revision 1.7 2001/10/14 13:12:09 lampret`
57			`// MP3 version.`
58			`//`
59			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
60			`// no message`
61			`//`
62			`// Revision 1.2 2001/08/09 13:39:33 lampret`
63			`// Major clean-up.`
64			`//`
65			`// Revision 1.1 2001/07/20 00:46:03 lampret`
66			`// Development version of RTL. Libraries are missing.`
67			`//`
68			`//`
69
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "or1200_defines.v"
74
75			`define OR1200_DCFSM_IDLE 3'd0
76			`define OR1200_DCFSM_DOLOAD 3'd1
77			`define OR1200_DCFSM_LREFILL3 3'd2
78			`define OR1200_DCFSM_DOSTORE 3'd3
79			`define OR1200_DCFSM_SREFILL4 3'd4
80
81			`//`
82			`// Data cache FSM for cache line of 16 bytes (4x singleword)`
83			`//`
84
85			`module or1200_dc_fsm(`
86			`// Clock and reset`
87			`clk, rst,`
88
89			`// Internal i/f to top level DC`
90			`dc_en, dcdmmu_cyc_i, dcdmmu_stb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,`
91			`tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,`
92			`dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,`
93			`burst`
94			`);`
95
96			`//`
97			`// I/O`
98			`//`
99			`input clk;`
100			`input rst;`
101			`input dc_en;`
102			`input dcdmmu_cyc_i;`
103			`input dcdmmu_stb_i;`
104			`input dcdmmu_ci_i;`
105			`input dcpu_we_i;`
106			`input [3:0] dcpu_sel_i;`
107			`input tagcomp_miss;`
108			`input biudata_valid;`
109			`input biudata_error;`
110			`input [31:0] start_addr;`
111			`output [31:0] saved_addr;`
112			`output [3:0] dcram_we;`
113			`output biu_read;`
114			`output biu_write;`
115			`output first_hit_ack;`
116			`output first_miss_ack;`
117			`output first_miss_err;`
118			`output burst;`
119
120			`//`
121			`// Internal wires and regs`
122			`//`
123			`reg [31:0] saved_addr;`
124			`reg [2:0] state;`
125			`reg [2:0] cnt;`
126			`reg hitmiss_eval;`
127			`reg store;`
128			`reg load;`
129
130			`//`
131			`// Generate of DCRAM write enables`
132			`//`
133			`assign dcram_we = {4{load & biudata_valid}} \| {4{store & biudata_valid}} & dcpu_sel_i;`
134
135			`//`
136			`// BIU read and write`
137			`//`
138			`assign biu_read = (hitmiss_eval & tagcomp_miss) \| (!hitmiss_eval & load);`
139			`assign biu_write = store;`
140
141			`//`
142			`// Assert for cache hit first word ready`
143			`// Assert for cache miss first word stored/loaded OK`
144			`// Assert for cache miss first word stored/loaded with an error`
145			`//`
146			assign first_hit_ack = (state == `OR1200_DCFSM_DOLOAD) & !tagcomp_miss & !dcdmmu_ci_i \| (state == `OR1200_DCFSM_DOSTORE) & !tagcomp_miss & biudata_valid;
147			assign first_miss_ack = ((state == `OR1200_DCFSM_DOLOAD) \| (state == `OR1200_DCFSM_DOSTORE)) & (tagcomp_miss \| dcdmmu_ci_i) & biudata_valid;
148			assign first_miss_err = ((state == `OR1200_DCFSM_DOLOAD) \| (state == `OR1200_DCFSM_DOSTORE)) & (tagcomp_miss \| dcdmmu_ci_i) & biudata_error;
149
150			`//`
151			`// Assert burst when doing reload of complete cache line`
152			`//`
153			assign burst = (state == `OR1200_DCFSM_DOLOAD) & tagcomp_miss
154			\| (state == `OR1200_DCFSM_LREFILL3) \| (state == `OR1200_DCFSM_SREFILL4);
155
156			`//`
157			`// Main DC FSM`
158			`//`
159			`always @(posedge clk or posedge rst) begin`
160			`if (rst) begin`
161			state <= #1 `OR1200_DCFSM_IDLE;
162			`saved_addr <= #1 32'b0;`
163			`hitmiss_eval <= #1 1'b0;`
164			`store <= #1 1'b0;`
165			`load <= #1 1'b0;`
166			`cnt <= #1 3'b000;`
167			`end`
168			`else`
169			`case (state) // synopsys parallel_case`
170			`OR1200_DCFSM_IDLE :
171			`if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i & dcpu_we_i) begin // store`
172			state <= #1 `OR1200_DCFSM_DOSTORE;
173			`saved_addr <= #1 start_addr;`
174			`hitmiss_eval <= #1 1'b1;`
175			`store <= #1 1'b1;`
176			`load <= #1 1'b0;`
177			`end`
178			`else if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i) begin // load`
179			state <= #1 `OR1200_DCFSM_DOLOAD;
180			`saved_addr <= #1 start_addr;`
181			`hitmiss_eval <= #1 1'b1;`
182			`store <= #1 1'b0;`
183			`load <= #1 1'b1;`
184			`end`
185			`else begin // idle`
186			state <= #1 `OR1200_DCFSM_IDLE;
187			`hitmiss_eval <= #1 1'b0;`
188			`store <= #1 1'b0;`
189			`load <= #1 1'b0;`
190			`end`
191			`OR1200_DCFSM_DOLOAD:
192			`if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)`
193			state <= #1 `OR1200_DCFSM_IDLE;
194			`hitmiss_eval <= #1 1'b0;`
195			`load <= #1 1'b0;`
196			`end`
197	562	lampret	`else if (biudata_error) begin // load terminated with an error`
198			state <= #1 `OR1200_DCFSM_IDLE;
199			`hitmiss_eval <= #1 1'b0;`
200			`load <= #1 1'b0;`
201			`end`
202	504	lampret	`else if (dcdmmu_ci_i & biudata_valid) begin // load from cache inhibit page`
203			state <= #1 `OR1200_DCFSM_IDLE;
204			`hitmiss_eval <= #1 1'b0;`
205			`load <= #1 1'b0;`
206			`end`
207			`else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill`
208			state <= #1 `OR1200_DCFSM_LREFILL3;
209			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
210			`hitmiss_eval <= #1 1'b0;`
211			cnt <= #1 `OR1200_DCLS-2;
212			`end`
213			`else if (!tagcomp_miss & !dcdmmu_ci_i) begin // load hit and not cache inhibit, finish immediately`
214			state <= #1 `OR1200_DCFSM_IDLE;
215			`hitmiss_eval <= #1 1'b0;`
216			`load <= #1 1'b0;`
217			`end`
218			`else // load in-progress`
219			`hitmiss_eval <= #1 1'b0;`
220			`OR1200_DCFSM_LREFILL3 : begin
221			`if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
222			`cnt <= #1 cnt - 'd1;`
223			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
224			`end`
225			`else if (biudata_valid) begin // last load of line refill`
226			state <= #1 `OR1200_DCFSM_IDLE;
227			`load <= #1 1'b0;`
228			`end`
229			`end`
230			`OR1200_DCFSM_DOSTORE:
231			`if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)`
232			state <= #1 `OR1200_DCFSM_IDLE;
233			`hitmiss_eval <= #1 1'b0;`
234			`store <= #1 1'b0;`
235			`end`
236	562	lampret	`else if (biudata_error) begin // store terminated with an error`
237			state <= #1 `OR1200_DCFSM_IDLE;
238			`hitmiss_eval <= #1 1'b0;`
239			`store <= #1 1'b0;`
240			`end`
241	504	lampret	`else if (dcdmmu_ci_i & biudata_valid) begin // store to cache inhibit page`
242			state <= #1 `OR1200_DCFSM_IDLE;
243			`hitmiss_eval <= #1 1'b0;`
244			`store <= #1 1'b0;`
245			`end`
246			`else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill`
247			state <= #1 `OR1200_DCFSM_SREFILL4;
248			`hitmiss_eval <= #1 1'b0;`
249			`store <= #1 1'b0;`
250			`load <= #1 1'b1;`
251			cnt <= #1 `OR1200_DCLS-1;
252			`end`
253			`else if (biudata_valid) begin // store hit, finish write-through`
254			state <= #1 `OR1200_DCFSM_IDLE;
255			`hitmiss_eval <= #1 1'b0;`
256			`store <= #1 1'b0;`
257			`end`
258			`else // store write-through in-progress`
259			`hitmiss_eval <= #1 1'b0;`
260			`OR1200_DCFSM_SREFILL4 : begin
261			`if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
262			`cnt <= #1 cnt - 'd1;`
263			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
264			`end`
265			`else if (biudata_valid) begin // last load of line refill`
266			state <= #1 `OR1200_DCFSM_IDLE;
267			`load <= #1 1'b0;`
268			`end`
269			`end`
270			`default:`
271			state <= #1 `OR1200_DCFSM_IDLE;
272			`endcase`
273			`end`
274
275			`endmodule`

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