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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instatiation of DC RAM blocks.                              ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dc_ram(
        // Reset and clock
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // Internal i/f
        addr, en, we, datain, dataout
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
`ifdef OR1200_NO_DC
 
//
// Data cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`else
 
`ifdef OR1200_BIST
//
// RAM BIST
//
wire                            mbist_ram0_so;
wire                            mbist_ram1_so;
wire                            mbist_ram2_so;
wire                            mbist_ram3_so;
wire                            mbist_ram0_si = mbist_si_i;
wire                            mbist_ram1_si = mbist_ram0_so;
wire                            mbist_ram2_si = mbist_ram1_so;
wire                            mbist_ram3_si = mbist_ram2_so;
assign                          mbist_so_o = mbist_ram3_so;
`endif
 
//
// Instantiation of RAM block 0
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram0(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram0(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_ram0_si),
        .mbist_so_o(mbist_ram0_so),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[0]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[7:0]),
        .do(dataout[7:0])
);
 
//
// Instantiation of RAM block 1
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram1(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram1(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_ram1_si),
        .mbist_so_o(mbist_ram1_so),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[1]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[15:8]),
        .do(dataout[15:8])
);
 
//
// Instantiation of RAM block 2
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram2(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram2(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_ram2_si),
        .mbist_so_o(mbist_ram2_so),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[2]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[23:16]),
        .do(dataout[23:16])
);
 
//
// Instantiation of RAM block 3
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram3(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram3(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_ram3_si),
        .mbist_so_o(mbist_ram3_so),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[3]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[31:24]),
        .do(dataout[31:24])
);
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	1063	lampret
2	504	lampret	`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// OR1200's DC RAMs ////`
5			`//// ////`
6			`//// This file is part of the OpenRISC 1200 project ////`
7			`//// http://www.opencores.org/cores/or1k/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// Instatiation of DC RAM blocks. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	1214	simons	`// Revision 1.2 2002/10/17 20:04:40 lampret`
49			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
50			`//`
51	1063	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
52			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
53			`//`
54	504	lampret	`// Revision 1.8 2001/10/21 17:57:16 lampret`
55			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
56			`//`
57			`// Revision 1.7 2001/10/14 13:12:09 lampret`
58			`// MP3 version.`
59			`//`
60			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
61			`// no message`
62			`//`
63			`// Revision 1.2 2001/08/09 13:39:33 lampret`
64			`// Major clean-up.`
65			`//`
66			`// Revision 1.1 2001/07/20 00:46:03 lampret`
67			`// Development version of RTL. Libraries are missing.`
68			`//`
69			`//`
70
71			`// synopsys translate_off`
72			`include "timescale.v"
73			`// synopsys translate_on`
74			`include "or1200_defines.v"
75
76			`module or1200_dc_ram(`
77			`// Reset and clock`
78			`clk, rst,`
79
80	1063	lampret	`ifdef OR1200_BIST
81			`// RAM BIST`
82	1214	simons	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
83	1063	lampret	`endif
84
85	504	lampret	`// Internal i/f`
86			`addr, en, we, datain, dataout`
87			`);`
88
89			parameter dw = `OR1200_OPERAND_WIDTH;
90			parameter aw = `OR1200_DCINDX;
91
92			`//`
93			`// I/O`
94			`//`
95			`input clk;`
96			`input rst;`
97			`input [aw-1:0] addr;`
98			`input en;`
99			`input [3:0] we;`
100			`input [dw-1:0] datain;`
101			`output [dw-1:0] dataout;`
102
103	1063	lampret	`ifdef OR1200_BIST
104			`//`
105			`// RAM BIST`
106			`//`
107	1214	simons	`input mbist_si_i;`
108			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
109			`output mbist_so_o;`
110	1063	lampret	`endif
111
112	504	lampret	`ifdef OR1200_NO_DC
113
114			`//`
115			`// Data cache not implemented`
116			`//`
117			`assign dataout = {dw{1'b0}};`
118	1063	lampret	`ifdef OR1200_BIST
119	1214	simons	`assign mbist_so_o = mbist_si_i;`
120	1063	lampret	`endif
121	504	lampret
122			`else
123
124	1063	lampret	`ifdef OR1200_BIST
125	504	lampret	`//`
126	1063	lampret	`// RAM BIST`
127			`//`
128	1214	simons	`wire mbist_ram0_so;`
129			`wire mbist_ram1_so;`
130			`wire mbist_ram2_so;`
131			`wire mbist_ram3_so;`
132			`wire mbist_ram0_si = mbist_si_i;`
133			`wire mbist_ram1_si = mbist_ram0_so;`
134			`wire mbist_ram2_si = mbist_ram1_so;`
135			`wire mbist_ram3_si = mbist_ram2_so;`
136			`assign mbist_so_o = mbist_ram3_so;`
137	1063	lampret	`endif
138
139			`//`
140	504	lampret	`// Instantiation of RAM block 0`
141			`//`
142			`ifdef OR1200_DC_1W_4KB
143			`or1200_spram_1024x8 dc_ram0(`
144			`endif
145			`ifdef OR1200_DC_1W_8KB
146			`or1200_spram_2048x8 dc_ram0(`
147			`endif
148	1063	lampret	`ifdef OR1200_BIST
149			`// RAM BIST`
150	1214	simons	`.mbist_si_i(mbist_ram0_si),`
151			`.mbist_so_o(mbist_ram0_so),`
152			`.mbist_ctrl_i(mbist_ctrl_i),`
153	1063	lampret	`endif
154	504	lampret	`.clk(clk),`
155			`.rst(rst),`
156			`.ce(en),`
157			`.we(we[0]),`
158			`.oe(1'b1),`
159			`.addr(addr),`
160			`.di(datain[7:0]),`
161			`.do(dataout[7:0])`
162			`);`
163
164			`//`
165			`// Instantiation of RAM block 1`
166			`//`
167			`ifdef OR1200_DC_1W_4KB
168			`or1200_spram_1024x8 dc_ram1(`
169			`endif
170			`ifdef OR1200_DC_1W_8KB
171			`or1200_spram_2048x8 dc_ram1(`
172			`endif
173	1063	lampret	`ifdef OR1200_BIST
174			`// RAM BIST`
175	1214	simons	`.mbist_si_i(mbist_ram1_si),`
176			`.mbist_so_o(mbist_ram1_so),`
177			`.mbist_ctrl_i(mbist_ctrl_i),`
178	1063	lampret	`endif
179	504	lampret	`.clk(clk),`
180			`.rst(rst),`
181			`.ce(en),`
182			`.we(we[1]),`
183			`.oe(1'b1),`
184			`.addr(addr),`
185			`.di(datain[15:8]),`
186			`.do(dataout[15:8])`
187			`);`
188
189			`//`
190			`// Instantiation of RAM block 2`
191			`//`
192			`ifdef OR1200_DC_1W_4KB
193			`or1200_spram_1024x8 dc_ram2(`
194			`endif
195			`ifdef OR1200_DC_1W_8KB
196			`or1200_spram_2048x8 dc_ram2(`
197			`endif
198	1063	lampret	`ifdef OR1200_BIST
199			`// RAM BIST`
200	1214	simons	`.mbist_si_i(mbist_ram2_si),`
201			`.mbist_so_o(mbist_ram2_so),`
202			`.mbist_ctrl_i(mbist_ctrl_i),`
203	1063	lampret	`endif
204	504	lampret	`.clk(clk),`
205			`.rst(rst),`
206			`.ce(en),`
207			`.we(we[2]),`
208			`.oe(1'b1),`
209			`.addr(addr),`
210			`.di(datain[23:16]),`
211			`.do(dataout[23:16])`
212			`);`
213
214			`//`
215			`// Instantiation of RAM block 3`
216			`//`
217			`ifdef OR1200_DC_1W_4KB
218			`or1200_spram_1024x8 dc_ram3(`
219			`endif
220			`ifdef OR1200_DC_1W_8KB
221			`or1200_spram_2048x8 dc_ram3(`
222			`endif
223	1063	lampret	`ifdef OR1200_BIST
224			`// RAM BIST`
225	1214	simons	`.mbist_si_i(mbist_ram3_si),`
226			`.mbist_so_o(mbist_ram3_so),`
227			`.mbist_ctrl_i(mbist_ctrl_i),`
228	1063	lampret	`endif
229	504	lampret	`.clk(clk),`
230			`.rst(rst),`
231			`.ce(en),`
232			`.we(we[3]),`
233			`.oe(1'b1),`
234			`.addr(addr),`
235			`.di(datain[31:24]),`
236			`.do(dataout[31:24])`
237			`);`
238
239			`endif
240
241			`endmodule`

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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Blame information for rev 1214