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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Double-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common double-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  double-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (Altera, VS etc)                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2001/11/05 14:48:00  lampret
// Added missing endif
//
// Revision 1.9  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.8  2001/10/22 19:39:56  lampret
// Fixed parameters in generic sprams.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dpram_32x32(
        // Generic synchronous double-port RAM interface
        clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
        clk_b, rst_b, ce_b, we_b, addr_b, di_b
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
 
//
// Generic synchronous double-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SDP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef UNUSED
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
`else
art_hsdp_32x32 artisan_sdp(
`endif
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(1'b1),
        .aa(addr_a),
        .da(32'h00000000),
        .oena(~oe_a),
        .qb(),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(1'b1)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_STP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
        .QA(do_a),
        .QB(),
 
        .ADRA(addr_a),
        .DA(32'h00000000),
        .WEA(1'b0),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(addr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(1'b1),
        .MEB(ce_b),
        .CLKB(clk_b)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_STP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Two-port R/W SRAM
//
`ifdef UNUSED
vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
vs_hdtp_32x32 vs_ssp(
`endif
        .RCK(clk_a),
        .REN(~ce_a),
        .OEN(~oe_a),
        .RADR(addr_a),
        .DI(di_b),
        .WCK(clk_b),
        .WEN(~ce_b),
        .WADR(addr_b),
        .DOUT(do_a)
);
 
`else
 
`ifdef OR1200_XILINX_RAM32X1D
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
xcv_ram32x8d xcv_ram32x8d_0 (
        .DPO(do_a[7:0]),
        .SPO(),
        .A(addr_b),
        .D(di_b[7:0]),
        .DPRA(addr_a),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 1
//
xcv_ram32x8d xcv_ram32x8d_1 (
        .DPO(do_a[15:8]),
        .SPO(),
        .A(addr_b),
        .D(di_b[15:8]),
        .DPRA(addr_a),
        .WCLK(clk_b),
        .WE(we_b)
);
 
 
//
// Block 2
//
xcv_ram32x8d xcv_ram32x8d_2 (
        .DPO(do_a[23:16]),
        .SPO(),
        .A(addr_b),
        .D(di_b[23:16]),
        .DPRA(addr_a),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 3
//
xcv_ram32x8d xcv_ram32x8d_3 (
        .DPO(do_a[31:24]),
        .SPO(),
        .A(addr_b),
        .D(di_b[31:24]),
        .DPRA(addr_a),
        .WCLK(clk_b),
        .WE(we_b)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
`else
 
//
// Generic double-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do_a = (oe_a) ? do_reg : {dw{1'bz}};
 
//
// RAM read
//
always @(posedge clk_a)
        if (ce_a)
                do_reg <= #1 mem[addr_a];
 
//
// RAM write
//
always @(posedge clk_b)
        if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
 
`endif  // !OR1200_XILINX_RAMB4_S16_S16
`endif  // !OR1200_XILINX_RAM32X1D
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_STP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SDP
 
endmodule

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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Blame information for rev 504

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Double-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common double-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// double-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25			`//// ////`
26			`//// To Do: ////`
27			`//// - fix Avant! ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - add additional RAMs (Altera, VS etc) ////`
30			`//// ////`
31			`//// Author(s): ////`
32			`//// - Damjan Lampret, lampret@opencores.org ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35			`//// ////`
36			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
37			`//// ////`
38			`//// This source file may be used and distributed without ////`
39			`//// restriction provided that this copyright statement is not ////`
40			`//// removed from the file and that any derivative work contains ////`
41			`//// the original copyright notice and the associated disclaimer. ////`
42			`//// ////`
43			`//// This source file is free software; you can redistribute it ////`
44			`//// and/or modify it under the terms of the GNU Lesser General ////`
45			`//// Public License as published by the Free Software Foundation; ////`
46			`//// either version 2.1 of the License, or (at your option) any ////`
47			`//// later version. ////`
48			`//// ////`
49			`//// This source is distributed in the hope that it will be ////`
50			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
51			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
52			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
53			`//// details. ////`
54			`//// ////`
55			`//// You should have received a copy of the GNU Lesser General ////`
56			`//// Public License along with this source; if not, download it ////`
57			`//// from http://www.opencores.org/lgpl.shtml ////`
58			`//// ////`
59			`//////////////////////////////////////////////////////////////////////`
60			`//`
61			`// CVS Revision History`
62			`//`
63			`// $Log: not supported by cvs2svn $`
64			`// Revision 1.10 2001/11/05 14:48:00 lampret`
65			`// Added missing endif`
66			`//`
67			`// Revision 1.9 2001/11/02 18:57:14 lampret`
68			`// Modified virtual silicon instantiations.`
69			`//`
70			`// Revision 1.8 2001/10/22 19:39:56 lampret`
71			`// Fixed parameters in generic sprams.`
72			`//`
73			`// Revision 1.7 2001/10/21 17:57:16 lampret`
74			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
75			`//`
76			`// Revision 1.6 2001/10/14 13:12:09 lampret`
77			`// MP3 version.`
78			`//`
79			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
80			`// no message`
81			`//`
82			`// Revision 1.1 2001/08/09 13:39:33 lampret`
83			`// Major clean-up.`
84			`//`
85			`// Revision 1.2 2001/07/30 05:38:02 lampret`
86			`// Adding empty directories required by HDL coding guidelines`
87			`//`
88			`//`
89
90			`// synopsys translate_off`
91			`include "timescale.v"
92			`// synopsys translate_on`
93			`include "or1200_defines.v"
94
95			`module or1200_dpram_32x32(`
96			`// Generic synchronous double-port RAM interface`
97			`clk_a, rst_a, ce_a, oe_a, addr_a, do_a,`
98			`clk_b, rst_b, ce_b, we_b, addr_b, di_b`
99			`);`
100
101			`//`
102			`// Default address and data buses width`
103			`//`
104			`parameter aw = 5;`
105			`parameter dw = 32;`
106
107			`//`
108			`// Generic synchronous double-port RAM interface`
109			`//`
110			`input clk_a; // Clock`
111			`input rst_a; // Reset`
112			`input ce_a; // Chip enable input`
113			`input oe_a; // Output enable input`
114			`input [aw-1:0] addr_a; // address bus inputs`
115			`output [dw-1:0] do_a; // output data bus`
116			`input clk_b; // Clock`
117			`input rst_b; // Reset`
118			`input ce_b; // Chip enable input`
119			`input we_b; // Write enable input`
120			`input [aw-1:0] addr_b; // address bus inputs`
121			`input [dw-1:0] di_b; // input data bus`
122
123			`//`
124			`// Internal wires and registers`
125			`//`
126
127			`ifdef OR1200_ARTISAN_SDP
128
129			`//`
130			`// Instantiation of ASIC memory:`
131			`//`
132			`// Artisan Synchronous Double-Port RAM (ra2sh)`
133			`//`
134			`ifdef UNUSED
135			`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`
136			`else
137			`art_hsdp_32x32 artisan_sdp(`
138			`endif
139			`.qa(do_a),`
140			`.clka(clk_a),`
141			`.cena(~ce_a),`
142			`.wena(1'b1),`
143			`.aa(addr_a),`
144			`.da(32'h00000000),`
145			`.oena(~oe_a),`
146			`.qb(),`
147			`.clkb(clk_b),`
148			`.cenb(~ce_b),`
149			`.wenb(~we_b),`
150			`.ab(addr_b),`
151			`.db(di_b),`
152			`.oenb(1'b1)`
153			`);`
154
155			`else
156
157			`ifdef OR1200_AVANT_ATP
158
159			`//`
160			`// Instantiation of ASIC memory:`
161			`//`
162			`// Avant! Asynchronous Two-Port RAM`
163			`//`
164			`avant_atp avant_atp(`
165			`.web(~we),`
166			`.reb(),`
167			`.oeb(~oe),`
168			`.rcsb(),`
169			`.wcsb(),`
170			`.ra(addr),`
171			`.wa(addr),`
172			`.di(di),`
173			`.do(do)`
174			`);`
175
176			`else
177
178			`ifdef OR1200_VIRAGE_STP
179
180			`//`
181			`// Instantiation of ASIC memory:`
182			`//`
183			`// Virage Synchronous 2-port R/W RAM`
184			`//`
185			`virage_stp virage_stp(`
186			`.QA(do_a),`
187			`.QB(),`
188
189			`.ADRA(addr_a),`
190			`.DA(32'h00000000),`
191			`.WEA(1'b0),`
192			`.OEA(oe_a),`
193			`.MEA(ce_a),`
194			`.CLKA(clk_a),`
195
196			`.ADRB(addr_b),`
197			`.DB(di_b),`
198			`.WEB(we_b),`
199			`.OEB(1'b1),`
200			`.MEB(ce_b),`
201			`.CLKB(clk_b)`
202			`);`
203
204			`else
205
206			`ifdef OR1200_VIRTUALSILICON_STP
207
208			`//`
209			`// Instantiation of ASIC memory:`
210			`//`
211			`// Virtual Silicon Two-port R/W SRAM`
212			`//`
213			`ifdef UNUSED
214			`vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
215			`else
216			`vs_hdtp_32x32 vs_ssp(`
217			`endif
218			`.RCK(clk_a),`
219			`.REN(~ce_a),`
220			`.OEN(~oe_a),`
221			`.RADR(addr_a),`
222			`.DI(di_b),`
223			`.WCK(clk_b),`
224			`.WEN(~ce_b),`
225			`.WADR(addr_b),`
226			`.DOUT(do_a)`
227			`);`
228
229			`else
230
231			`ifdef OR1200_XILINX_RAM32X1D
232
233			`//`
234			`// Instantiation of FPGA memory:`
235			`//`
236			`// Virtex/Spartan2`
237			`//`
238
239			`//`
240			`// Block 0`
241			`//`
242			`xcv_ram32x8d xcv_ram32x8d_0 (`
243			`.DPO(do_a[7:0]),`
244			`.SPO(),`
245			`.A(addr_b),`
246			`.D(di_b[7:0]),`
247			`.DPRA(addr_a),`
248			`.WCLK(clk_b),`
249			`.WE(we_b)`
250			`);`
251
252			`//`
253			`// Block 1`
254			`//`
255			`xcv_ram32x8d xcv_ram32x8d_1 (`
256			`.DPO(do_a[15:8]),`
257			`.SPO(),`
258			`.A(addr_b),`
259			`.D(di_b[15:8]),`
260			`.DPRA(addr_a),`
261			`.WCLK(clk_b),`
262			`.WE(we_b)`
263			`);`
264
265
266			`//`
267			`// Block 2`
268			`//`
269			`xcv_ram32x8d xcv_ram32x8d_2 (`
270			`.DPO(do_a[23:16]),`
271			`.SPO(),`
272			`.A(addr_b),`
273			`.D(di_b[23:16]),`
274			`.DPRA(addr_a),`
275			`.WCLK(clk_b),`
276			`.WE(we_b)`
277			`);`
278
279			`//`
280			`// Block 3`
281			`//`
282			`xcv_ram32x8d xcv_ram32x8d_3 (`
283			`.DPO(do_a[31:24]),`
284			`.SPO(),`
285			`.A(addr_b),`
286			`.D(di_b[31:24]),`
287			`.DPRA(addr_a),`
288			`.WCLK(clk_b),`
289			`.WE(we_b)`
290			`);`
291
292			`else
293
294			`ifdef OR1200_XILINX_RAMB4
295
296			`//`
297			`// Instantiation of FPGA memory:`
298			`//`
299			`// Virtex/Spartan2`
300			`//`
301
302			`//`
303			`// Block 0`
304			`//`
305			`RAMB4_S16_S16 ramb4_s16_0(`
306			`.CLKA(clk_a),`
307			`.RSTA(rst_a),`
308			`.ADDRA({3'b000, addr_a}),`
309			`.DIA(16'h0000),`
310			`.ENA(ce_a),`
311			`.WEA(1'b0),`
312			`.DOA(do_a[15:0]),`
313
314			`.CLKB(clk_b),`
315			`.RSTB(rst_b),`
316			`.ADDRB({3'b000, addr_b}),`
317			`.DIB(di_b[15:0]),`
318			`.ENB(ce_b),`
319			`.WEB(we_b),`
320			`.DOB()`
321			`);`
322
323			`//`
324			`// Block 1`
325			`//`
326			`RAMB4_S16_S16 ramb4_s16_1(`
327			`.CLKA(clk_a),`
328			`.RSTA(rst_a),`
329			`.ADDRA({3'b000, addr_a}),`
330			`.DIA(16'h0000),`
331			`.ENA(ce_a),`
332			`.WEA(1'b0),`
333			`.DOA(do_a[31:16]),`
334
335			`.CLKB(clk_b),`
336			`.RSTB(rst_b),`
337			`.ADDRB({3'b000, addr_b}),`
338			`.DIB(di_b[31:16]),`
339			`.ENB(ce_b),`
340			`.WEB(we_b),`
341			`.DOB()`
342			`);`
343
344			`else
345
346			`//`
347			`// Generic double-port synchronous RAM model`
348			`//`
349
350			`//`
351			`// Generic RAM's registers and wires`
352			`//`
353			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
354			`reg [dw-1:0] do_reg; // RAM data output register`
355
356			`//`
357			`// Data output drivers`
358			`//`
359			`assign do_a = (oe_a) ? do_reg : {dw{1'bz}};`
360
361			`//`
362			`// RAM read`
363			`//`
364			`always @(posedge clk_a)`
365			`if (ce_a)`
366			`do_reg <= #1 mem[addr_a];`
367
368			`//`
369			`// RAM write`
370			`//`
371			`always @(posedge clk_b)`
372			`if (ce_b && we_b)`
373			`mem[addr_b] <= #1 di_b;`
374
375			`endif // !OR1200_XILINX_RAMB4_S16_S16
376			`endif // !OR1200_XILINX_RAM32X1D
377			`endif // !OR1200_VIRTUALSILICON_SSP
378			`endif // !OR1200_VIRAGE_STP
379			`endif // !OR1200_AVANT_ATP
380			`endif // !OR1200_ARTISAN_SDP
381
382			`endmodule`