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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_mem2reg(addr, lsu_op, memdata, regdata);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
input   [width-1:0]              memdata;
output  [width-1:0]              regdata;
 
 
//
// Faster implementation of mem2reg
//
`ifdef OR1200_MEM2REG_FAST
 
`define OR1200_SEL_00 2'b00
`define OR1200_SEL_01 2'b01
`define OR1200_SEL_10 2'b10
`define OR1200_SEL_11 2'b11
 
reg     [7:0]                    regdata_hh;
reg     [7:0]                    regdata_hl;
reg     [7:0]                    regdata_lh;
reg     [7:0]                    regdata_ll;
reg     [width-1:0]              aligned;
reg     [1:0]                    sel_byte0, sel_byte1,
                                sel_byte2, sel_byte3;
 
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b01x, 2'b00}:
                        sel_byte0 = `OR1200_SEL_11;
                {3'b01x, 2'b01}:
                        sel_byte0 = `OR1200_SEL_10;
                {3'b01x, 2'b10}:
                        sel_byte0 = `OR1200_SEL_01;
                {3'b01x, 2'b11}:
                        sel_byte0 = `OR1200_SEL_00;
                {3'b10x, 2'b00}:
                        sel_byte0 = `OR1200_SEL_10;
                {3'b10x, 2'b10}:
                        sel_byte0 = `OR1200_SEL_00;
                default:
                        sel_byte0 = `OR1200_SEL_00;
        endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx}:
                        sel_byte1 = `OR1200_SEL_00;     // zero extend
                {3'b011, 2'bxx}:
                        sel_byte1 = `OR1200_SEL_10;     // sign extend byte
                {3'b10x, 2'b00}:
                        sel_byte1 = `OR1200_SEL_11;
                default:
                        sel_byte1 = `OR1200_SEL_01;
        endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx},
                {3'b100, 2'bxx}:
                        sel_byte2 = `OR1200_SEL_00;     // zero extend
                {3'b011, 2'bxx}:
                        sel_byte2 = `OR1200_SEL_01;     // sign extend byte
                {3'b101, 2'bxx}:
                        sel_byte2 = `OR1200_SEL_11;     // sign extend halfword
                default:
                        sel_byte2 = `OR1200_SEL_10;
        endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx},
                {3'b100, 2'bxx}:
                        sel_byte3 = `OR1200_SEL_00;     // zero extend
                {3'b011, 2'bxx}:
                        sel_byte3 = `OR1200_SEL_01;     // sign extend byte
                {3'b101, 2'bxx}:
                        sel_byte3 = `OR1200_SEL_10;     // sign extend halfword
                default:
                        sel_byte3 = `OR1200_SEL_11;
        endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
                `OR1200_SEL_00: begin
                                regdata_ll = memdata[7:0];
                        end
                `OR1200_SEL_01: begin
                                regdata_ll = memdata[15:8];
                        end
                `OR1200_SEL_10: begin
                                regdata_ll = memdata[23:16];
                        end
                `OR1200_SEL_11: begin
                                regdata_ll = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
                `OR1200_SEL_00: begin
                                regdata_lh = 8'b0;
                        end
                `OR1200_SEL_01: begin
                                regdata_lh = memdata[15:8];
                        end
                `OR1200_SEL_10: begin
                                regdata_lh = {8{memdata[7]}};
                        end
                `OR1200_SEL_11: begin
                                regdata_lh = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
                `OR1200_SEL_00: begin
                                regdata_hl = 8'b0;
                        end
                `OR1200_SEL_01: begin
                                regdata_hl = {8{memdata[7]}};
                        end
                `OR1200_SEL_10: begin
                                regdata_hl = memdata[23:16];
                        end
                `OR1200_SEL_11: begin
                                regdata_hl = {8{memdata[15]}};
                        end
        endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
                `OR1200_SEL_00: begin
                                regdata_hh = 8'b0;
                        end
                `OR1200_SEL_01: begin
                                regdata_hh = {8{memdata[7]}};
                        end
                `OR1200_SEL_10: begin
                                regdata_hh = {8{memdata[15]}};
                        end
                `OR1200_SEL_11: begin
                                regdata_hh = memdata[31:24];
                        end
        endcase
end
 
`else
 
//
// Slow implementation of mem2reg
//
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
        case(addr) // synopsys infer_mux
                2'b00:
                        aligned = memdata;
                2'b01:
                        aligned = {memdata[23:0], 8'b0};
                2'b10:
                        aligned = {memdata[15:0], 16'b0};
                2'b11:
                        aligned = {memdata[7:0], 24'b0};
        endcase
end
 
//
// Bytes
//
always @(lsu_op or aligned) begin
        case(lsu_op) // synopsys infer_mux
                `OR1200_LSUOP_LBZ: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = 24'b0;
                        end
                `OR1200_LSUOP_LBS: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = {24{aligned[31]}};
                        end
                `OR1200_LSUOP_LHZ: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = 16'b0;
                        end
                `OR1200_LSUOP_LHS: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = {16{aligned[31]}};
                        end
                default:
                                regdata = aligned;
        endcase
end
 
`endif
 
endmodule

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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Blame information for rev 504

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's mem2reg alignment ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Two versions of Memory to register data alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.9 2001/10/21 17:57:16 lampret`
48			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
49			`//`
50			`// Revision 1.8 2001/10/19 23:28:46 lampret`
51			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
52			`//`
53			`// Revision 1.7 2001/10/14 13:12:09 lampret`
54			`// MP3 version.`
55			`//`
56			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
57			`// no message`
58			`//`
59			`// Revision 1.2 2001/08/09 13:39:33 lampret`
60			`// Major clean-up.`
61			`//`
62			`// Revision 1.1 2001/07/20 00:46:03 lampret`
63			`// Development version of RTL. Libraries are missing.`
64			`//`
65			`//`
66
67			`// synopsys translate_off`
68			`include "timescale.v"
69			`// synopsys translate_on`
70			`include "or1200_defines.v"
71
72			`module or1200_mem2reg(addr, lsu_op, memdata, regdata);`
73
74			parameter width = `OR1200_OPERAND_WIDTH;
75
76			`//`
77			`// I/O`
78			`//`
79			`input [1:0] addr;`
80			input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
81			`input [width-1:0] memdata;`
82			`output [width-1:0] regdata;`
83
84
85			`//`
86			`// Faster implementation of mem2reg`
87			`//`
88			`ifdef OR1200_MEM2REG_FAST
89
90			`define OR1200_SEL_00 2'b00
91			`define OR1200_SEL_01 2'b01
92			`define OR1200_SEL_10 2'b10
93			`define OR1200_SEL_11 2'b11
94
95			`reg [7:0] regdata_hh;`
96			`reg [7:0] regdata_hl;`
97			`reg [7:0] regdata_lh;`
98			`reg [7:0] regdata_ll;`
99			`reg [width-1:0] aligned;`
100			`reg [1:0] sel_byte0, sel_byte1,`
101			`sel_byte2, sel_byte3;`
102
103			`assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};`
104
105			`//`
106			`// Byte select 0`
107			`//`
108			`always @(addr or lsu_op) begin`
109			`casex({lsu_op[2:0], addr})`
110			`{3'b01x, 2'b00}:`
111			sel_byte0 = `OR1200_SEL_11;
112			`{3'b01x, 2'b01}:`
113			sel_byte0 = `OR1200_SEL_10;
114			`{3'b01x, 2'b10}:`
115			sel_byte0 = `OR1200_SEL_01;
116			`{3'b01x, 2'b11}:`
117			sel_byte0 = `OR1200_SEL_00;
118			`{3'b10x, 2'b00}:`
119			sel_byte0 = `OR1200_SEL_10;
120			`{3'b10x, 2'b10}:`
121			sel_byte0 = `OR1200_SEL_00;
122			`default:`
123			sel_byte0 = `OR1200_SEL_00;
124			`endcase`
125			`end`
126
127			`//`
128			`// Byte select 1`
129			`//`
130			`always @(addr or lsu_op) begin`
131			`casex({lsu_op[2:0], addr})`
132			`{3'b010, 2'bxx}:`
133			sel_byte1 = `OR1200_SEL_00; // zero extend
134			`{3'b011, 2'bxx}:`
135			sel_byte1 = `OR1200_SEL_10; // sign extend byte
136			`{3'b10x, 2'b00}:`
137			sel_byte1 = `OR1200_SEL_11;
138			`default:`
139			sel_byte1 = `OR1200_SEL_01;
140			`endcase`
141			`end`
142
143			`//`
144			`// Byte select 2`
145			`//`
146			`always @(addr or lsu_op) begin`
147			`casex({lsu_op[2:0], addr})`
148			`{3'b010, 2'bxx},`
149			`{3'b100, 2'bxx}:`
150			sel_byte2 = `OR1200_SEL_00; // zero extend
151			`{3'b011, 2'bxx}:`
152			sel_byte2 = `OR1200_SEL_01; // sign extend byte
153			`{3'b101, 2'bxx}:`
154			sel_byte2 = `OR1200_SEL_11; // sign extend halfword
155			`default:`
156			sel_byte2 = `OR1200_SEL_10;
157			`endcase`
158			`end`
159
160			`//`
161			`// Byte select 3`
162			`//`
163			`always @(addr or lsu_op) begin`
164			`casex({lsu_op[2:0], addr})`
165			`{3'b010, 2'bxx},`
166			`{3'b100, 2'bxx}:`
167			sel_byte3 = `OR1200_SEL_00; // zero extend
168			`{3'b011, 2'bxx}:`
169			sel_byte3 = `OR1200_SEL_01; // sign extend byte
170			`{3'b101, 2'bxx}:`
171			sel_byte3 = `OR1200_SEL_10; // sign extend halfword
172			`default:`
173			sel_byte3 = `OR1200_SEL_11;
174			`endcase`
175			`end`
176
177			`//`
178			`// Byte 0`
179			`//`
180			`always @(sel_byte0 or memdata) begin`
181			`case(sel_byte0) // synopsys full_case parallel_case infer_mux`
182			`OR1200_SEL_00: begin
183			`regdata_ll = memdata[7:0];`
184			`end`
185			`OR1200_SEL_01: begin
186			`regdata_ll = memdata[15:8];`
187			`end`
188			`OR1200_SEL_10: begin
189			`regdata_ll = memdata[23:16];`
190			`end`
191			`OR1200_SEL_11: begin
192			`regdata_ll = memdata[31:24];`
193			`end`
194			`endcase`
195			`end`
196
197			`//`
198			`// Byte 1`
199			`//`
200			`always @(sel_byte1 or memdata) begin`
201			`case(sel_byte1) // synopsys full_case parallel_case infer_mux`
202			`OR1200_SEL_00: begin
203			`regdata_lh = 8'b0;`
204			`end`
205			`OR1200_SEL_01: begin
206			`regdata_lh = memdata[15:8];`
207			`end`
208			`OR1200_SEL_10: begin
209			`regdata_lh = {8{memdata[7]}};`
210			`end`
211			`OR1200_SEL_11: begin
212			`regdata_lh = memdata[31:24];`
213			`end`
214			`endcase`
215			`end`
216
217			`//`
218			`// Byte 2`
219			`//`
220			`always @(sel_byte2 or memdata) begin`
221			`case(sel_byte2) // synopsys full_case parallel_case infer_mux`
222			`OR1200_SEL_00: begin
223			`regdata_hl = 8'b0;`
224			`end`
225			`OR1200_SEL_01: begin
226			`regdata_hl = {8{memdata[7]}};`
227			`end`
228			`OR1200_SEL_10: begin
229			`regdata_hl = memdata[23:16];`
230			`end`
231			`OR1200_SEL_11: begin
232			`regdata_hl = {8{memdata[15]}};`
233			`end`
234			`endcase`
235			`end`
236
237			`//`
238			`// Byte 3`
239			`//`
240			`always @(sel_byte3 or memdata) begin`
241			`case(sel_byte3) // synopsys full_case parallel_case infer_mux`
242			`OR1200_SEL_00: begin
243			`regdata_hh = 8'b0;`
244			`end`
245			`OR1200_SEL_01: begin
246			`regdata_hh = {8{memdata[7]}};`
247			`end`
248			`OR1200_SEL_10: begin
249			`regdata_hh = {8{memdata[15]}};`
250			`end`
251			`OR1200_SEL_11: begin
252			`regdata_hh = memdata[31:24];`
253			`end`
254			`endcase`
255			`end`
256
257			`else
258
259			`//`
260			`// Slow implementation of mem2reg`
261			`//`
262
263			`reg [width-1:0] regdata;`
264			`reg [width-1:0] aligned;`
265
266			`//`
267			`// Alignment`
268			`//`
269			`always @(addr or memdata) begin`
270			`case(addr) // synopsys infer_mux`
271			`2'b00:`
272			`aligned = memdata;`
273			`2'b01:`
274			`aligned = {memdata[23:0], 8'b0};`
275			`2'b10:`
276			`aligned = {memdata[15:0], 16'b0};`
277			`2'b11:`
278			`aligned = {memdata[7:0], 24'b0};`
279			`endcase`
280			`end`
281
282			`//`
283			`// Bytes`
284			`//`
285			`always @(lsu_op or aligned) begin`
286			`case(lsu_op) // synopsys infer_mux`
287			`OR1200_LSUOP_LBZ: begin
288			`regdata[7:0] = aligned[31:24];`
289			`regdata[31:8] = 24'b0;`
290			`end`
291			`OR1200_LSUOP_LBS: begin
292			`regdata[7:0] = aligned[31:24];`
293			`regdata[31:8] = {24{aligned[31]}};`
294			`end`
295			`OR1200_LSUOP_LHZ: begin
296			`regdata[15:0] = aligned[31:16];`
297			`regdata[31:16] = 16'b0;`
298			`end`
299			`OR1200_LSUOP_LHS: begin
300			`regdata[15:0] = aligned[31:16];`
301			`regdata[31:16] = {16{aligned[31]}};`
302			`end`
303			`default:`
304			`regdata = aligned;`
305			`endcase`
306			`end`
307
308			`endif
309
310			`endmodule`