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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Blame information for rev 1778

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Programmable Interrupt Controller                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PIC according to OR1K architectural specification.          ////
////                                                              ////
////  To Do:                                                      ////
////   None                                                       ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_pic(
        // RISC Internal Interface
        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        pic_wakeup, int,
 
        // PIC Interface
        pic_int
);
 
//
// RISC Internal Interface
//
input           clk;            // Clock
input           rst;            // Reset
input           spr_cs;         // SPR CS
input           spr_write;      // SPR Write
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_dat_i;      // SPR Write Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output          pic_wakeup;     // Wakeup to the PM
output          int;            // interrupt
                                // exception request
 
//
// PIC Interface
//
input   [`OR1200_PIC_INTS-1:0]   pic_int;// Interrupt inputs
 
`ifdef OR1200_PIC_IMPLEMENTED
 
//
// PIC Mask Register bits (or no register)
//
`ifdef OR1200_PIC_PICMR
reg     [`OR1200_PIC_INTS-1:2]  picmr;  // PICMR bits
`else
wire    [`OR1200_PIC_INTS-1:2]  picmr;  // No PICMR register
`endif
 
//
// PIC Status Register bits (or no register)
//
`ifdef OR1200_PIC_PICSR
reg     [`OR1200_PIC_INTS-1:0]   picsr;  // PICSR bits
`else
wire    [`OR1200_PIC_INTS-1:0]   picsr;  // No PICSR register
`endif
 
//
// Internal wires & regs
//
wire            picmr_sel;      // PICMR select
wire            picsr_sel;      // PICSR select
wire    [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
reg     [31:0]   spr_dat_o;      // SPR data out
 
//
// PIC registers address decoder
//
assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
 
//
// Write to PICMR
//
`ifdef OR1200_PIC_PICMR
always @(posedge clk or posedge rst)
        if (rst)
                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
        else if (picmr_sel && spr_write) begin
                picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
        end
`else
assign picmr = (`OR1200_PIC_INTS)'b1;
`endif
 
//
// Write to PICSR, both CPU and external ints
//
`ifdef OR1200_PIC_PICSR
always @(posedge clk or posedge rst)
        if (rst)
                picsr <= {`OR1200_PIC_INTS-2{1'b0}};
        else if (picsr_sel && spr_write) begin
                picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
        end else
                picsr <= #1 picsr | um_ints;
`else
assign picsr = pic_int;
`endif
 
//
// Read PIC registers
//
always @(spr_addr or picmr or picsr)
        case (spr_addr[`OR1200_PICOFS_BITS])    // synopsys parallel_case
`ifdef OR1200_PIC_READREGS
                `OR1200_PIC_OFS_PICMR: begin
                                        spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
`ifdef OR1200_PIC_UNUSED_ZERO
                                        spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
                                end
`endif
                default: begin
                                spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
`ifdef OR1200_PIC_UNUSED_ZERO
                                spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
                        end
        endcase
 
//
// Unmasked interrupts
//
assign um_ints = pic_int & {picmr, 2'b11};
 
//
// Generate int
//
assign int = |um_ints;
 
//
// Assert pic_wakeup when int is asserted
//
assign pic_wakeup = int;
 
`else
 
//
// When PIC is not implemented, drive all outputs as would when PIC is disabled
//
assign int = pic_int[1] | pic_int[0];
assign pic_wakeup= int;
 
//
// Read PIC registers
//
`ifdef OR1200_PIC_READREGS
assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
`ifdef OR1200_PIC_UNUSED_ZERO
assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
`endif
`endif
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Programmable Interrupt Controller ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PIC according to OR1K architectural specification. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// None ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	788	lampret	`// Revision 1.2 2002/01/18 07:56:00 lampret`
48			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
49			`//`
50	589	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
51			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
52			`//`
53	504	lampret	`// Revision 1.8 2001/10/21 17:57:16 lampret`
54			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
55			`//`
56			`// Revision 1.7 2001/10/14 13:12:10 lampret`
57			`// MP3 version.`
58			`//`
59			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
60			`// no message`
61			`//`
62			`// Revision 1.2 2001/08/09 13:39:33 lampret`
63			`// Major clean-up.`
64			`//`
65			`// Revision 1.1 2001/07/20 00:46:21 lampret`
66			`// Development version of RTL. Libraries are missing.`
67			`//`
68			`//`
69
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "or1200_defines.v"
74
75			`module or1200_pic(`
76			`// RISC Internal Interface`
77			`clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
78	589	lampret	`pic_wakeup, int,`
79	504	lampret
80			`// PIC Interface`
81			`pic_int`
82			`);`
83
84			`//`
85			`// RISC Internal Interface`
86			`//`
87			`input clk; // Clock`
88			`input rst; // Reset`
89			`input spr_cs; // SPR CS`
90			`input spr_write; // SPR Write`
91			`input [31:0] spr_addr; // SPR Address`
92			`input [31:0] spr_dat_i; // SPR Write Data`
93			`output [31:0] spr_dat_o; // SPR Read Data`
94			`output pic_wakeup; // Wakeup to the PM`
95	589	lampret	`output int; // interrupt`
96	504	lampret	`// exception request`
97
98			`//`
99			`// PIC Interface`
100			`//`
101			input [`OR1200_PIC_INTS-1:0] pic_int;// Interrupt inputs
102
103			`ifdef OR1200_PIC_IMPLEMENTED
104
105			`//`
106			`// PIC Mask Register bits (or no register)`
107			`//`
108			`ifdef OR1200_PIC_PICMR
109			reg [`OR1200_PIC_INTS-1:2] picmr; // PICMR bits
110			`else
111			wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register
112			`endif
113
114			`//`
115			`// PIC Status Register bits (or no register)`
116			`//`
117			`ifdef OR1200_PIC_PICSR
118			reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits
119			`else
120			wire [`OR1200_PIC_INTS-1:0] picsr; // No PICSR register
121			`endif
122
123			`//`
124			`// Internal wires & regs`
125			`//`
126			`wire picmr_sel; // PICMR select`
127			`wire picsr_sel; // PICSR select`
128			wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
129			`reg [31:0] spr_dat_o; // SPR data out`
130
131			`//`
132			`// PIC registers address decoder`
133			`//`
134			assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
135			assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
136
137			`//`
138			`// Write to PICMR`
139			`//`
140			`ifdef OR1200_PIC_PICMR
141			`always @(posedge clk or posedge rst)`
142			`if (rst)`
143			picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
144			`else if (picmr_sel && spr_write) begin`
145			picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
146			`end`
147			`else
148	589	lampret	assign picmr = (`OR1200_PIC_INTS)'b1;
149	504	lampret	`endif
150
151			`//`
152			`// Write to PICSR, both CPU and external ints`
153			`//`
154			`ifdef OR1200_PIC_PICSR
155			`always @(posedge clk or posedge rst)`
156			`if (rst)`
157			picsr <= {`OR1200_PIC_INTS-2{1'b0}};
158			`else if (picsr_sel && spr_write) begin`
159			picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] \| um_ints;
160			`end else`
161			`picsr <= #1 picsr \| um_ints;`
162			`else
163			`assign picsr = pic_int;`
164			`endif
165
166			`//`
167			`// Read PIC registers`
168			`//`
169	589	lampret	`always @(spr_addr or picmr or picsr)`
170	788	lampret	case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys parallel_case
171	504	lampret	`ifdef OR1200_PIC_READREGS
172			`OR1200_PIC_OFS_PICMR: begin
173			spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
174			`ifdef OR1200_PIC_UNUSED_ZERO
175			spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
176			`endif
177			`end`
178			`endif
179			`default: begin`
180			spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
181			`ifdef OR1200_PIC_UNUSED_ZERO
182			spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
183			`endif
184			`end`
185			`endcase`
186
187			`//`
188			`// Unmasked interrupts`
189			`//`
190			`assign um_ints = pic_int & {picmr, 2'b11};`
191
192			`//`
193	589	lampret	`// Generate int`
194	504	lampret	`//`
195	589	lampret	`assign int = \|um_ints;`
196	504	lampret
197			`//`
198	589	lampret	`// Assert pic_wakeup when int is asserted`
199	504	lampret	`//`
200	589	lampret	`assign pic_wakeup = int;`
201	504	lampret
202			`else
203
204			`//`
205			`// When PIC is not implemented, drive all outputs as would when PIC is disabled`
206			`//`
207	589	lampret	`assign int = pic_int[1] \| pic_int[0];`
208			`assign pic_wakeup= int;`
209	504	lampret
210			`//`
211			`// Read PIC registers`
212			`//`
213			`ifdef OR1200_PIC_READREGS
214			assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
215			`ifdef OR1200_PIC_UNUSED_ZERO
216			assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
217			`endif
218			`endif
219
220			`endif
221
222			`endmodule`

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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Blame information for rev 1778