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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Blame information for rev 1129

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Two-Port Synchronous RAM                            ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common two-port                ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  two-port synchronous RAM.                                   ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (VS etc)                             ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_tpram_32x32(
        // Generic synchronous two-port RAM interface
        clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,
        clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
 
//
// Generic synchronous two-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   we_a;   // Write enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
input   [dw-1:0] di_a;   // input data bus
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input                   oe_b;   // Output enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
output  [dw-1:0] do_b;   // output data bus
 
//
// Internal wires and registers
//
 
 
`ifdef OR1200_ARTISAN_SDP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef UNUSED
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
`else
art_hsdp_32x32 artisan_sdp(
`endif
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(~we_a),
        .aa(addr_a),
        .da(di_a),
        .oena(~oe_a),
        .qb(do_b),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(~oe_b)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_STP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
        .QA(do_a),
        .QB(do_b),
 
        .ADRA(addr_a),
        .DA(di_a),
        .WEA(we_a),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(adr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(oe_b),
        .MEB(ce_b),
        .CLKB(clk_b)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[15:0]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[15:0])
);
 
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[31:16]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[31:16])
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
altqpram altqpram_component (
        .wraddress_a (addr_a),
        .inclocken_a (ce_a),
        .wraddress_b (addr_b),
        .wren_a (we_a),
        .inclocken_b (ce_b),
        .wren_b (we_b),
        .inaclr_a (rst_a),
        .inaclr_b (rst_b),
        .inclock_a (clk_a),
        .inclock_b (clk_b),
        .data_a (di_a),
        .data_b (di_b),
        .q_a (do_a),
        .q_b (do_b)
);
 
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
        altqpram_component.width_write_a = dw,
        altqpram_component.widthad_write_a = aw,
        altqpram_component.numwords_write_a = dw,
        altqpram_component.width_read_a = dw,
        altqpram_component.widthad_read_a = aw,
        altqpram_component.numwords_read_a = dw,
        altqpram_component.width_write_b = dw,
        altqpram_component.widthad_write_b = aw,
        altqpram_component.numwords_write_b = dw,
        altqpram_component.width_read_b = dw,
        altqpram_component.widthad_read_b = aw,
        altqpram_component.numwords_read_b = dw,
        altqpram_component.indata_reg_a = "INCLOCK_A",
        altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
        altqpram_component.outdata_reg_a = "INCLOCK_A",
        altqpram_component.indata_reg_b = "INCLOCK_B",
        altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
        altqpram_component.outdata_reg_b = "INCLOCK_B",
        altqpram_component.indata_aclr_a = "INACLR_A",
        altqpram_component.wraddress_aclr_a = "INACLR_A",
        altqpram_component.wrcontrol_aclr_a = "INACLR_A",
        altqpram_component.outdata_aclr_a = "INACLR_A",
        altqpram_component.indata_aclr_b = "NONE",
        altqpram_component.wraddress_aclr_b = "NONE",
        altqpram_component.wrcontrol_aclr_b = "NONE",
        altqpram_component.outdata_aclr_b = "INACLR_B",
        altqpram_component.lpm_hint = "USE_ESB=ON";
        //examplar attribute altqpram_component NOOPT TRUE
 
`else
 
//
// Generic two-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg_a;               // RAM data output register
reg     [dw-1:0] do_reg_b;               // RAM data output register
 
//
// Data output drivers
//
assign do_a = (oe_a) ? do_reg_a : {dw{1'b0}};
assign do_b = (oe_b) ? do_reg_b : {dw{1'b0}};
 
//
// RAM read and write
//
always @(posedge clk_a)
        if (ce_a && !we_a)
                do_reg_a <= #1 mem[addr_a];
        else if (ce_a && we_a)
                mem[addr_a] <= #1 di_a;
 
//
// RAM read and write
//
always @(posedge clk_b)
        if (ce_b && !we_b)
                do_reg_b <= #1 mem[addr_b];
        else if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16_S16
`endif  // !OR1200_VIRAGE_STP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SDP
 
endmodule

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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Blame information for rev 1129

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Two-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common two-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// two-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25	1129	lampret	`//// - Altera LPM ////`
26	504	lampret	`//// ////`
27			`//// To Do: ////`
28			`//// - fix Avant! ////`
29			`//// - xilinx rams need external tri-state logic ////`
30	1129	lampret	`//// - add additional RAMs (VS etc) ////`
31	504	lampret	`//// ////`
32			`//// Author(s): ////`
33			`//// - Damjan Lampret, lampret@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65	1129	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
66			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
67			`//`
68	504	lampret	`// Revision 1.7 2001/10/21 17:57:16 lampret`
69			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
70			`//`
71			`// Revision 1.6 2001/10/14 13:12:09 lampret`
72			`// MP3 version.`
73			`//`
74			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
75			`// no message`
76			`//`
77			`// Revision 1.1 2001/08/09 13:39:33 lampret`
78			`// Major clean-up.`
79			`//`
80			`// Revision 1.2 2001/07/30 05:38:02 lampret`
81			`// Adding empty directories required by HDL coding guidelines`
82			`//`
83			`//`
84
85			`// synopsys translate_off`
86			`include "timescale.v"
87			`// synopsys translate_on`
88			`include "or1200_defines.v"
89
90			`module or1200_tpram_32x32(`
91			`// Generic synchronous two-port RAM interface`
92			`clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,`
93			`clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b`
94			`);`
95
96			`//`
97			`// Default address and data buses width`
98			`//`
99			`parameter aw = 5;`
100			`parameter dw = 32;`
101
102			`//`
103			`// Generic synchronous two-port RAM interface`
104			`//`
105			`input clk_a; // Clock`
106			`input rst_a; // Reset`
107			`input ce_a; // Chip enable input`
108			`input we_a; // Write enable input`
109			`input oe_a; // Output enable input`
110			`input [aw-1:0] addr_a; // address bus inputs`
111			`input [dw-1:0] di_a; // input data bus`
112			`output [dw-1:0] do_a; // output data bus`
113			`input clk_b; // Clock`
114			`input rst_b; // Reset`
115			`input ce_b; // Chip enable input`
116			`input we_b; // Write enable input`
117			`input oe_b; // Output enable input`
118			`input [aw-1:0] addr_b; // address bus inputs`
119			`input [dw-1:0] di_b; // input data bus`
120			`output [dw-1:0] do_b; // output data bus`
121
122			`//`
123			`// Internal wires and registers`
124			`//`
125
126
127			`ifdef OR1200_ARTISAN_SDP
128
129			`//`
130			`// Instantiation of ASIC memory:`
131			`//`
132			`// Artisan Synchronous Double-Port RAM (ra2sh)`
133			`//`
134			`ifdef UNUSED
135			`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`
136			`else
137			`art_hsdp_32x32 artisan_sdp(`
138			`endif
139			`.qa(do_a),`
140			`.clka(clk_a),`
141			`.cena(~ce_a),`
142			`.wena(~we_a),`
143			`.aa(addr_a),`
144			`.da(di_a),`
145			`.oena(~oe_a),`
146			`.qb(do_b),`
147			`.clkb(clk_b),`
148			`.cenb(~ce_b),`
149			`.wenb(~we_b),`
150			`.ab(addr_b),`
151			`.db(di_b),`
152			`.oenb(~oe_b)`
153			`);`
154
155			`else
156
157			`ifdef OR1200_AVANT_ATP
158
159			`//`
160			`// Instantiation of ASIC memory:`
161			`//`
162			`// Avant! Asynchronous Two-Port RAM`
163			`//`
164			`avant_atp avant_atp(`
165			`.web(~we),`
166			`.reb(),`
167			`.oeb(~oe),`
168			`.rcsb(),`
169			`.wcsb(),`
170			`.ra(addr),`
171			`.wa(addr),`
172			`.di(di),`
173			`.do(do)`
174			`);`
175
176			`else
177
178			`ifdef OR1200_VIRAGE_STP
179
180			`//`
181			`// Instantiation of ASIC memory:`
182			`//`
183			`// Virage Synchronous 2-port R/W RAM`
184			`//`
185			`virage_stp virage_stp(`
186			`.QA(do_a),`
187			`.QB(do_b),`
188
189			`.ADRA(addr_a),`
190			`.DA(di_a),`
191			`.WEA(we_a),`
192			`.OEA(oe_a),`
193			`.MEA(ce_a),`
194			`.CLKA(clk_a),`
195
196			`.ADRB(adr_b),`
197			`.DB(di_b),`
198			`.WEB(we_b),`
199			`.OEB(oe_b),`
200			`.MEB(ce_b),`
201			`.CLKB(clk_b)`
202			`);`
203
204			`else
205
206			`ifdef OR1200_XILINX_RAMB4
207
208			`//`
209			`// Instantiation of FPGA memory:`
210			`//`
211			`// Virtex/Spartan2`
212			`//`
213
214			`//`
215			`// Block 0`
216			`//`
217			`RAMB4_S16_S16 ramb4_s16_s16_0(`
218			`.CLKA(clk_a),`
219			`.RSTA(rst_a),`
220			`.ADDRA(addr_a),`
221			`.DIA(di_a[15:0]),`
222			`.ENA(ce_a),`
223			`.WEA(we_a),`
224			`.DOA(do_a[15:0]),`
225
226			`.CLKB(clk_b),`
227			`.RSTB(rst_b),`
228			`.ADDRB(addr_b),`
229			`.DIB(di_b[15:0]),`
230			`.ENB(ce_b),`
231			`.WEB(we_b),`
232			`.DOB(do_b[15:0])`
233			`);`
234
235			`//`
236			`// Block 1`
237			`//`
238			`RAMB4_S16_S16 ramb4_s16_s16_1(`
239			`.CLKA(clk_a),`
240			`.RSTA(rst_a),`
241			`.ADDRA(addr_a),`
242			`.DIA(di_a[31:16]),`
243			`.ENA(ce_a),`
244			`.WEA(we_a),`
245			`.DOA(do_a[31:16]),`
246
247			`.CLKB(clk_b),`
248			`.RSTB(rst_b),`
249			`.ADDRB(addr_b),`
250			`.DIB(di_b[31:16]),`
251			`.ENB(ce_b),`
252			`.WEB(we_b),`
253			`.DOB(do_b[31:16])`
254			`);`
255
256			`else
257
258	1129	lampret	`ifdef OR1200_ALTERA_LPM
259
260	504	lampret	`//`
261	1129	lampret	`// Instantiation of FPGA memory:`
262			`//`
263			`// Altera LPM`
264			`//`
265			`// Added By Jamil Khatib`
266			`//`
267			`altqpram altqpram_component (`
268			`.wraddress_a (addr_a),`
269			`.inclocken_a (ce_a),`
270			`.wraddress_b (addr_b),`
271			`.wren_a (we_a),`
272			`.inclocken_b (ce_b),`
273			`.wren_b (we_b),`
274			`.inaclr_a (rst_a),`
275			`.inaclr_b (rst_b),`
276			`.inclock_a (clk_a),`
277			`.inclock_b (clk_b),`
278			`.data_a (di_a),`
279			`.data_b (di_b),`
280			`.q_a (do_a),`
281			`.q_b (do_b)`
282			`);`
283
284			`defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",`
285			`altqpram_component.width_write_a = dw,`
286			`altqpram_component.widthad_write_a = aw,`
287			`altqpram_component.numwords_write_a = dw,`
288			`altqpram_component.width_read_a = dw,`
289			`altqpram_component.widthad_read_a = aw,`
290			`altqpram_component.numwords_read_a = dw,`
291			`altqpram_component.width_write_b = dw,`
292			`altqpram_component.widthad_write_b = aw,`
293			`altqpram_component.numwords_write_b = dw,`
294			`altqpram_component.width_read_b = dw,`
295			`altqpram_component.widthad_read_b = aw,`
296			`altqpram_component.numwords_read_b = dw,`
297			`altqpram_component.indata_reg_a = "INCLOCK_A",`
298			`altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",`
299			`altqpram_component.outdata_reg_a = "INCLOCK_A",`
300			`altqpram_component.indata_reg_b = "INCLOCK_B",`
301			`altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",`
302			`altqpram_component.outdata_reg_b = "INCLOCK_B",`
303			`altqpram_component.indata_aclr_a = "INACLR_A",`
304			`altqpram_component.wraddress_aclr_a = "INACLR_A",`
305			`altqpram_component.wrcontrol_aclr_a = "INACLR_A",`
306			`altqpram_component.outdata_aclr_a = "INACLR_A",`
307			`altqpram_component.indata_aclr_b = "NONE",`
308			`altqpram_component.wraddress_aclr_b = "NONE",`
309			`altqpram_component.wrcontrol_aclr_b = "NONE",`
310			`altqpram_component.outdata_aclr_b = "INACLR_B",`
311			`altqpram_component.lpm_hint = "USE_ESB=ON";`
312			`//examplar attribute altqpram_component NOOPT TRUE`
313
314			`else
315
316			`//`
317	504	lampret	`// Generic two-port synchronous RAM model`
318			`//`
319
320			`//`
321			`// Generic RAM's registers and wires`
322			`//`
323			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
324			`reg [dw-1:0] do_reg_a; // RAM data output register`
325			`reg [dw-1:0] do_reg_b; // RAM data output register`
326
327			`//`
328			`// Data output drivers`
329			`//`
330	1129	lampret	`assign do_a = (oe_a) ? do_reg_a : {dw{1'b0}};`
331			`assign do_b = (oe_b) ? do_reg_b : {dw{1'b0}};`
332	504	lampret
333			`//`
334			`// RAM read and write`
335			`//`
336			`always @(posedge clk_a)`
337			`if (ce_a && !we_a)`
338			`do_reg_a <= #1 mem[addr_a];`
339			`else if (ce_a && we_a)`
340			`mem[addr_a] <= #1 di_a;`
341
342			`//`
343			`// RAM read and write`
344			`//`
345			`always @(posedge clk_b)`
346			`if (ce_b && !we_b)`
347			`do_reg_b <= #1 mem[addr_b];`
348			`else if (ce_b && we_b)`
349			`mem[addr_b] <= #1 di_b;`
350
351	1129	lampret	`endif // !OR1200_ALTERA_LPM
352	504	lampret	`endif // !OR1200_XILINX_RAMB4_S16_S16
353			`endif // !OR1200_VIRAGE_STP
354			`endif // !OR1200_AVANT_ATP
355			`endif // !OR1200_ARTISAN_SDP
356
357			`endmodule`