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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Xilinx Virtex RAM 32x8D                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Virtex dual-port memory                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`ifdef OR1200_XILINX_RAM32X1D
 
module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
 
//
// I/O
//
output [7:0]     DPO;
output [7:0]     SPO;
input [4:0]      A;
input [4:0]      DPRA;
input [7:0]      D;
input           WCLK;
input           WE;
 
//
// Instantiation of block 0
//
RAM32X1D ram32x1d_0(
        .DPO(DPO[0]),
        .SPO(SPO[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 1
//
RAM32X1D ram32x1d_1(
        .DPO(DPO[1]),
        .SPO(SPO[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 2
//
RAM32X1D ram32x1d_2(
        .DPO(DPO[2]),
        .SPO(SPO[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 3
//
RAM32X1D ram32x1d_3(
        .DPO(DPO[3]),
        .SPO(SPO[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 4
//
RAM32X1D ram32x1d_4(
        .DPO(DPO[4]),
        .SPO(SPO[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 5
//
RAM32X1D ram32x1d_5(
        .DPO(DPO[5]),
        .SPO(SPO[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 6
//
RAM32X1D ram32x1d_6(
        .DPO(DPO[6]),
        .SPO(SPO[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 7
//
RAM32X1D ram32x1d_7(
        .DPO(DPO[7]),
        .SPO(SPO[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
endmodule
 
`endif

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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Blame information for rev 504

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Xilinx Virtex RAM 32x8D ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Virtex dual-port memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.7 2001/10/21 17:57:16 lampret`
48			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
49			`//`
50			`// Revision 1.6 2001/10/14 13:12:10 lampret`
51			`// MP3 version.`
52			`//`
53			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
54			`// no message`
55			`//`
56			`// Revision 1.1 2001/08/09 13:39:33 lampret`
57			`// Major clean-up.`
58			`//`
59			`//`
60
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "or1200_defines.v"
65
66			`ifdef OR1200_XILINX_RAM32X1D
67
68			`module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);`
69
70			`//`
71			`// I/O`
72			`//`
73			`output [7:0] DPO;`
74			`output [7:0] SPO;`
75			`input [4:0] A;`
76			`input [4:0] DPRA;`
77			`input [7:0] D;`
78			`input WCLK;`
79			`input WE;`
80
81			`//`
82			`// Instantiation of block 0`
83			`//`
84			`RAM32X1D ram32x1d_0(`
85			`.DPO(DPO[0]),`
86			`.SPO(SPO[0]),`
87			`.A0(A[0]),`
88			`.A1(A[1]),`
89			`.A2(A[2]),`
90			`.A3(A[3]),`
91			`.A4(A[4]),`
92			`.D(D[0]),`
93			`.DPRA0(DPRA[0]),`
94			`.DPRA1(DPRA[1]),`
95			`.DPRA2(DPRA[2]),`
96			`.DPRA3(DPRA[3]),`
97			`.DPRA4(DPRA[4]),`
98			`.WCLK(WCLK),`
99			`.WE(WE)`
100			`);`
101
102			`//`
103			`// Instantiation of block 1`
104			`//`
105			`RAM32X1D ram32x1d_1(`
106			`.DPO(DPO[1]),`
107			`.SPO(SPO[1]),`
108			`.A0(A[0]),`
109			`.A1(A[1]),`
110			`.A2(A[2]),`
111			`.A3(A[3]),`
112			`.A4(A[4]),`
113			`.D(D[1]),`
114			`.DPRA0(DPRA[0]),`
115			`.DPRA1(DPRA[1]),`
116			`.DPRA2(DPRA[2]),`
117			`.DPRA3(DPRA[3]),`
118			`.DPRA4(DPRA[4]),`
119			`.WCLK(WCLK),`
120			`.WE(WE)`
121			`);`
122
123			`//`
124			`// Instantiation of block 2`
125			`//`
126			`RAM32X1D ram32x1d_2(`
127			`.DPO(DPO[2]),`
128			`.SPO(SPO[2]),`
129			`.A0(A[0]),`
130			`.A1(A[1]),`
131			`.A2(A[2]),`
132			`.A3(A[3]),`
133			`.A4(A[4]),`
134			`.D(D[2]),`
135			`.DPRA0(DPRA[0]),`
136			`.DPRA1(DPRA[1]),`
137			`.DPRA2(DPRA[2]),`
138			`.DPRA3(DPRA[3]),`
139			`.DPRA4(DPRA[4]),`
140			`.WCLK(WCLK),`
141			`.WE(WE)`
142			`);`
143
144			`//`
145			`// Instantiation of block 3`
146			`//`
147			`RAM32X1D ram32x1d_3(`
148			`.DPO(DPO[3]),`
149			`.SPO(SPO[3]),`
150			`.A0(A[0]),`
151			`.A1(A[1]),`
152			`.A2(A[2]),`
153			`.A3(A[3]),`
154			`.A4(A[4]),`
155			`.D(D[3]),`
156			`.DPRA0(DPRA[0]),`
157			`.DPRA1(DPRA[1]),`
158			`.DPRA2(DPRA[2]),`
159			`.DPRA3(DPRA[3]),`
160			`.DPRA4(DPRA[4]),`
161			`.WCLK(WCLK),`
162			`.WE(WE)`
163			`);`
164
165			`//`
166			`// Instantiation of block 4`
167			`//`
168			`RAM32X1D ram32x1d_4(`
169			`.DPO(DPO[4]),`
170			`.SPO(SPO[4]),`
171			`.A0(A[0]),`
172			`.A1(A[1]),`
173			`.A2(A[2]),`
174			`.A3(A[3]),`
175			`.A4(A[4]),`
176			`.D(D[4]),`
177			`.DPRA0(DPRA[0]),`
178			`.DPRA1(DPRA[1]),`
179			`.DPRA2(DPRA[2]),`
180			`.DPRA3(DPRA[3]),`
181			`.DPRA4(DPRA[4]),`
182			`.WCLK(WCLK),`
183			`.WE(WE)`
184			`);`
185
186			`//`
187			`// Instantiation of block 5`
188			`//`
189			`RAM32X1D ram32x1d_5(`
190			`.DPO(DPO[5]),`
191			`.SPO(SPO[5]),`
192			`.A0(A[0]),`
193			`.A1(A[1]),`
194			`.A2(A[2]),`
195			`.A3(A[3]),`
196			`.A4(A[4]),`
197			`.D(D[5]),`
198			`.DPRA0(DPRA[0]),`
199			`.DPRA1(DPRA[1]),`
200			`.DPRA2(DPRA[2]),`
201			`.DPRA3(DPRA[3]),`
202			`.DPRA4(DPRA[4]),`
203			`.WCLK(WCLK),`
204			`.WE(WE)`
205			`);`
206
207			`//`
208			`// Instantiation of block 6`
209			`//`
210			`RAM32X1D ram32x1d_6(`
211			`.DPO(DPO[6]),`
212			`.SPO(SPO[6]),`
213			`.A0(A[0]),`
214			`.A1(A[1]),`
215			`.A2(A[2]),`
216			`.A3(A[3]),`
217			`.A4(A[4]),`
218			`.D(D[6]),`
219			`.DPRA0(DPRA[0]),`
220			`.DPRA1(DPRA[1]),`
221			`.DPRA2(DPRA[2]),`
222			`.DPRA3(DPRA[3]),`
223			`.DPRA4(DPRA[4]),`
224			`.WCLK(WCLK),`
225			`.WE(WE)`
226			`);`
227
228			`//`
229			`// Instantiation of block 7`
230			`//`
231			`RAM32X1D ram32x1d_7(`
232			`.DPO(DPO[7]),`
233			`.SPO(SPO[7]),`
234			`.A0(A[0]),`
235			`.A1(A[1]),`
236			`.A2(A[2]),`
237			`.A3(A[3]),`
238			`.A4(A[4]),`
239			`.D(D[7]),`
240			`.DPRA0(DPRA[0]),`
241			`.DPRA1(DPRA[1]),`
242			`.DPRA2(DPRA[2]),`
243			`.DPRA3(DPRA[3]),`
244			`.DPRA4(DPRA[4]),`
245			`.WCLK(WCLK),`
246			`.WE(WE)`
247			`);`
248
249			`endmodule`
250
251			`endif