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[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Blame information for rev 1163

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instatiation of DC RAM blocks.                              ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dc_ram(
        // Reset and clock
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
        // Internal i/f
        addr, en, we, datain, dataout
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                           scanb_rst,
                                scanb_si,
                                scanb_en,
                                scanb_clk;
output                          scanb_so;
`endif
 
`ifdef OR1200_NO_DC
 
//
// Data cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
 
`else
 
`ifdef OR1200_BIST
//
// RAM BIST
//
wire                            scanb_ram0_so;
wire                            scanb_ram1_so;
wire                            scanb_ram2_so;
wire                            scanb_ram3_so;
wire                            scanb_ram0_si = scanb_si;
wire                            scanb_ram1_si = scanb_ram0_so;
wire                            scanb_ram2_si = scanb_ram1_so;
wire                            scanb_ram3_si = scanb_ram2_so;
assign                          scanb_so = scanb_ram3_so;
`endif
 
//
// Instantiation of RAM block 0
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram0(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram0(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_ram0_si),
        .scanb_so(scanb_ram0_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[0]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[7:0]),
        .do(dataout[7:0])
);
 
//
// Instantiation of RAM block 1
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram1(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram1(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_ram1_si),
        .scanb_so(scanb_ram1_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[1]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[15:8]),
        .do(dataout[15:8])
);
 
//
// Instantiation of RAM block 2
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram2(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram2(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_ram2_si),
        .scanb_so(scanb_ram2_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[2]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[23:16]),
        .do(dataout[23:16])
);
 
//
// Instantiation of RAM block 3
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram3(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram3(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_ram3_si),
        .scanb_so(scanb_ram3_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[3]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[31:24]),
        .do(dataout[31:24])
);
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	1063	lampret
2	504	lampret	`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// OR1200's DC RAMs ////`
5			`//// ////`
6			`//// This file is part of the OpenRISC 1200 project ////`
7			`//// http://www.opencores.org/cores/or1k/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// Instatiation of DC RAM blocks. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	1063	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
49			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
50			`//`
51	504	lampret	`// Revision 1.8 2001/10/21 17:57:16 lampret`
52			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
53			`//`
54			`// Revision 1.7 2001/10/14 13:12:09 lampret`
55			`// MP3 version.`
56			`//`
57			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
58			`// no message`
59			`//`
60			`// Revision 1.2 2001/08/09 13:39:33 lampret`
61			`// Major clean-up.`
62			`//`
63			`// Revision 1.1 2001/07/20 00:46:03 lampret`
64			`// Development version of RTL. Libraries are missing.`
65			`//`
66			`//`
67
68			`// synopsys translate_off`
69			`include "timescale.v"
70			`// synopsys translate_on`
71			`include "or1200_defines.v"
72
73			`module or1200_dc_ram(`
74			`// Reset and clock`
75			`clk, rst,`
76
77	1063	lampret	`ifdef OR1200_BIST
78			`// RAM BIST`
79			`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`
80			`endif
81
82	504	lampret	`// Internal i/f`
83			`addr, en, we, datain, dataout`
84			`);`
85
86			parameter dw = `OR1200_OPERAND_WIDTH;
87			parameter aw = `OR1200_DCINDX;
88
89			`//`
90			`// I/O`
91			`//`
92			`input clk;`
93			`input rst;`
94			`input [aw-1:0] addr;`
95			`input en;`
96			`input [3:0] we;`
97			`input [dw-1:0] datain;`
98			`output [dw-1:0] dataout;`
99
100	1063	lampret	`ifdef OR1200_BIST
101			`//`
102			`// RAM BIST`
103			`//`
104			`input scanb_rst,`
105			`scanb_si,`
106			`scanb_en,`
107			`scanb_clk;`
108			`output scanb_so;`
109			`endif
110
111	504	lampret	`ifdef OR1200_NO_DC
112
113			`//`
114			`// Data cache not implemented`
115			`//`
116			`assign dataout = {dw{1'b0}};`
117	1063	lampret	`ifdef OR1200_BIST
118			`assign scanb_so = scanb_si;`
119			`endif
120	504	lampret
121			`else
122
123	1063	lampret	`ifdef OR1200_BIST
124	504	lampret	`//`
125	1063	lampret	`// RAM BIST`
126			`//`
127			`wire scanb_ram0_so;`
128			`wire scanb_ram1_so;`
129			`wire scanb_ram2_so;`
130			`wire scanb_ram3_so;`
131			`wire scanb_ram0_si = scanb_si;`
132			`wire scanb_ram1_si = scanb_ram0_so;`
133			`wire scanb_ram2_si = scanb_ram1_so;`
134			`wire scanb_ram3_si = scanb_ram2_so;`
135			`assign scanb_so = scanb_ram3_so;`
136			`endif
137
138			`//`
139	504	lampret	`// Instantiation of RAM block 0`
140			`//`
141			`ifdef OR1200_DC_1W_4KB
142			`or1200_spram_1024x8 dc_ram0(`
143			`endif
144			`ifdef OR1200_DC_1W_8KB
145			`or1200_spram_2048x8 dc_ram0(`
146			`endif
147	1063	lampret	`ifdef OR1200_BIST
148			`// RAM BIST`
149			`.scanb_rst(scanb_rst),`
150			`.scanb_si(scanb_ram0_si),`
151			`.scanb_so(scanb_ram0_so),`
152			`.scanb_en(scanb_en),`
153			`.scanb_clk(scanb_clk),`
154			`endif
155	504	lampret	`.clk(clk),`
156			`.rst(rst),`
157			`.ce(en),`
158			`.we(we[0]),`
159			`.oe(1'b1),`
160			`.addr(addr),`
161			`.di(datain[7:0]),`
162			`.do(dataout[7:0])`
163			`);`
164
165			`//`
166			`// Instantiation of RAM block 1`
167			`//`
168			`ifdef OR1200_DC_1W_4KB
169			`or1200_spram_1024x8 dc_ram1(`
170			`endif
171			`ifdef OR1200_DC_1W_8KB
172			`or1200_spram_2048x8 dc_ram1(`
173			`endif
174	1063	lampret	`ifdef OR1200_BIST
175			`// RAM BIST`
176			`.scanb_rst(scanb_rst),`
177			`.scanb_si(scanb_ram1_si),`
178			`.scanb_so(scanb_ram1_so),`
179			`.scanb_en(scanb_en),`
180			`.scanb_clk(scanb_clk),`
181			`endif
182	504	lampret	`.clk(clk),`
183			`.rst(rst),`
184			`.ce(en),`
185			`.we(we[1]),`
186			`.oe(1'b1),`
187			`.addr(addr),`
188			`.di(datain[15:8]),`
189			`.do(dataout[15:8])`
190			`);`
191
192			`//`
193			`// Instantiation of RAM block 2`
194			`//`
195			`ifdef OR1200_DC_1W_4KB
196			`or1200_spram_1024x8 dc_ram2(`
197			`endif
198			`ifdef OR1200_DC_1W_8KB
199			`or1200_spram_2048x8 dc_ram2(`
200			`endif
201	1063	lampret	`ifdef OR1200_BIST
202			`// RAM BIST`
203			`.scanb_rst(scanb_rst),`
204			`.scanb_si(scanb_ram2_si),`
205			`.scanb_so(scanb_ram2_so),`
206			`.scanb_en(scanb_en),`
207			`.scanb_clk(scanb_clk),`
208			`endif
209	504	lampret	`.clk(clk),`
210			`.rst(rst),`
211			`.ce(en),`
212			`.we(we[2]),`
213			`.oe(1'b1),`
214			`.addr(addr),`
215			`.di(datain[23:16]),`
216			`.do(dataout[23:16])`
217			`);`
218
219			`//`
220			`// Instantiation of RAM block 3`
221			`//`
222			`ifdef OR1200_DC_1W_4KB
223			`or1200_spram_1024x8 dc_ram3(`
224			`endif
225			`ifdef OR1200_DC_1W_8KB
226			`or1200_spram_2048x8 dc_ram3(`
227			`endif
228	1063	lampret	`ifdef OR1200_BIST
229			`// RAM BIST`
230			`.scanb_rst(scanb_rst),`
231			`.scanb_si(scanb_ram3_si),`
232			`.scanb_so(scanb_ram3_so),`
233			`.scanb_en(scanb_en),`
234			`.scanb_clk(scanb_clk),`
235			`endif
236	504	lampret	`.clk(clk),`
237			`.rst(rst),`
238			`.ce(en),`
239			`.we(we[3]),`
240			`.oe(1'b1),`
241			`.addr(addr),`
242			`.di(datain[31:24]),`
243			`.do(dataout[31:24])`
244			`);`
245
246			`endif
247
248			`endmodule`

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[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Blame information for rev 1163