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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Top level multiplier and MAC                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Multiplier is 32x32 however multiply instructions only      ////
////  use lower 32 bits of the result. MAC is 32x32=64+64.        ////
////                                                              ////
////  To Do:                                                      ////
////   - make signed division better, w/o negating the operands   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.3  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.2  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:38  igorm
// no message
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_mult_mac(
        // Clock and reset
        clk, rst,
 
        // Multiplier/MAC interface
        ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
 
        // SPR interface
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Multiplier/MAC interface
//
input                           ex_freeze;
input                           id_macrc_op;
input                           macrc_op;
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [`OR1200_MACOP_WIDTH-1:0]        mac_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
output  [width-1:0]              result;
output                          mac_stall_r;
 
//
// SPR interface
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [2*width-1:0]            mul_prod_r;
reg     [2*width-1:0]            mac_r;
wire    [2*width-1:0]            mul_prod;
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r1;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r2;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r3;
reg                             mac_stall_r;
wire    [width-1:0]              x;
wire    [width-1:0]              y;
wire                            spr_maclo_we;
wire                            spr_machi_we;
wire                            alu_op_div_divu;
wire                            alu_op_div;
reg                             div_free;
`ifdef OR1200_IMPL_DIV
wire    [width-1:0]              div_tmp;
reg     [5:0]                    div_cntr;
`endif
 
//
// Combinatorial logic
//
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
`ifdef OR1200_LOWPWR_MULT
assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
`else
assign x = alu_op_div & a[31] ? ~a + 1'b1 : a;
assign y = alu_op_div & b[31] ? ~b + 1'b1 : b;
`endif
`ifdef OR1200_IMPL_DIV
assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU);
assign div_tmp = mul_prod_r[63:32] - y;
`else
assign alu_op_div = 1'b0;
assign alu_op_div_divu = 1'b0;
`endif
 
//
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
//
always @(alu_op or mul_prod_r or mac_r or a or b)
        casex(alu_op)   // synopsys parallel_case
`ifdef OR1200_IMPL_DIV
                `OR1200_ALUOP_DIV:
                        result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL: begin
                        result = mul_prod_r[31:0];
                end
                default:
                        result = mac_r[59:28];
        endcase
 
//
// Instantiation of the multiplier
//
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
        .X(x),
        .Y(y),
        .RST(rst),
        .CLK(clk),
        .P(mul_prod)
);
`else
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
        .X(x),
        .Y(y),
        .RST(rst),
        .CLK(clk),
        .P(mul_prod)
);
`endif
 
//
// Registered output from the multiplier and
// an optional divider
//
always @(posedge rst or posedge clk)
        if (rst) begin
                mul_prod_r <= #1 64'h0000_0000_0000_0000;
                div_free <= #1 1'b1;
`ifdef OR1200_IMPL_DIV
                div_cntr <= #1 6'b00_0000;
`endif
        end
`ifdef OR1200_IMPL_DIV
        else if (|div_cntr) begin
                if (div_tmp[31])
                        mul_prod_r <= #1 {mul_prod_r[62:0], 1'b0};
                else
                        mul_prod_r <= #1 {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
                div_cntr <= #1 div_cntr - 1'b1;
        end
        else if (alu_op_div_divu && div_free) begin
                mul_prod_r <= #1 {31'b0, x[31:0], 1'b0};
                div_cntr <= #1 6'b10_0000;
                div_free <= #1 1'b0;
        end
`endif
        else if (div_free | !ex_freeze) begin
                mul_prod_r <= #1 mul_prod[63:0];
                div_free <= #1 1'b1;
        end
 
//
 // Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r1 <= #1 mac_op;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r2 <= #1 mac_op_r1;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r3 <= #1 mac_op_r2;
 
//
// Implementation of MAC
//
always @(posedge rst or posedge clk)
        if (rst)
                mac_r <= #1 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
        else if (spr_maclo_we)
                mac_r[31:0] <= #1 spr_dat_i;
        else if (spr_machi_we)
                mac_r[63:32] <= #1 spr_dat_i;
`endif
        else if (mac_op_r3 == `OR1200_MACOP_MAC)
                mac_r <= #1 mac_r + mul_prod_r;
        else if (mac_op_r3 == `OR1200_MACOP_MSB)
                mac_r <= #1 mac_r - mul_prod_r;
        else if (macrc_op & !ex_freeze)
                mac_r <= #1 64'h0000_0000_0000_0000;
 
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
// This stall signal is also used by the divider.
//
always @(posedge rst or posedge clk)
        if (rst)
                mac_stall_r <= #1 1'b0;
        else
                mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op
`ifdef OR1200_IMPL_DIV
                                | (|div_cntr)
`endif
                                ;
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Top level multiplier and MAC ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Multiplier is 32x32 however multiply instructions only ////`
10			`//// use lower 32 bits of the result. MAC is 32x32=64+64. ////`
11			`//// ////`
12			`//// To Do: ////`
13	1035	lampret	`//// - make signed division better, w/o negating the operands ////`
14	504	lampret	`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	1035	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
49			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
50			`//`
51	504	lampret	`// Revision 1.3 2001/10/21 17:57:16 lampret`
52			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
53			`//`
54			`// Revision 1.2 2001/10/14 13:12:09 lampret`
55			`// MP3 version.`
56			`//`
57			`// Revision 1.1.1.1 2001/10/06 10:18:38 igorm`
58			`// no message`
59			`//`
60			`//`
61
62			`// synopsys translate_off`
63			`include "timescale.v"
64			`// synopsys translate_on`
65			`include "or1200_defines.v"
66
67			`module or1200_mult_mac(`
68			`// Clock and reset`
69			`clk, rst,`
70
71			`// Multiplier/MAC interface`
72			`ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,`
73
74			`// SPR interface`
75			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
76			`);`
77
78			parameter width = `OR1200_OPERAND_WIDTH;
79
80			`//`
81			`// I/O`
82			`//`
83
84			`//`
85			`// Clock and reset`
86			`//`
87			`input clk;`
88			`input rst;`
89
90			`//`
91			`// Multiplier/MAC interface`
92			`//`
93			`input ex_freeze;`
94			`input id_macrc_op;`
95			`input macrc_op;`
96			`input [width-1:0] a;`
97			`input [width-1:0] b;`
98			input [`OR1200_MACOP_WIDTH-1:0] mac_op;
99			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
100			`output [width-1:0] result;`
101			`output mac_stall_r;`
102
103			`//`
104			`// SPR interface`
105			`//`
106			`input spr_cs;`
107			`input spr_write;`
108			`input [31:0] spr_addr;`
109			`input [31:0] spr_dat_i;`
110			`output [31:0] spr_dat_o;`
111
112			`//`
113			`// Internal wires and regs`
114			`//`
115	1035	lampret	`reg [width-1:0] result;`
116	504	lampret	`reg [2*width-1:0] mul_prod_r;`
117			`reg [2*width-1:0] mac_r;`
118			`wire [2*width-1:0] mul_prod;`
119			wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
120			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
121			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
122			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
123			`reg mac_stall_r;`
124			`wire [width-1:0] x;`
125			`wire [width-1:0] y;`
126			`wire spr_maclo_we;`
127			`wire spr_machi_we;`
128	1035	lampret	`wire alu_op_div_divu;`
129			`wire alu_op_div;`
130			`reg div_free;`
131			`ifdef OR1200_IMPL_DIV
132			`wire [width-1:0] div_tmp;`
133			`reg [5:0] div_cntr;`
134			`endif
135	504	lampret
136			`//`
137			`// Combinatorial logic`
138			`//`
139			assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
140			assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
141			assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
142			`ifdef OR1200_LOWPWR_MULT
143	1035	lampret	assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu \| (alu_op == `OR1200_ALUOP_MUL) \| (\|mac_op) ? a : 32'h0000_0000;
144			assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu \| (alu_op == `OR1200_ALUOP_MUL) \| (\|mac_op) ? b : 32'h0000_0000;
145	504	lampret	`else
146	1035	lampret	`assign x = alu_op_div & a[31] ? ~a + 1'b1 : a;`
147			`assign y = alu_op_div & b[31] ? ~b + 1'b1 : b;`
148	504	lampret	`endif
149	1035	lampret	`ifdef OR1200_IMPL_DIV
150			assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
151			assign alu_op_div_divu = alu_op_div \| (alu_op == `OR1200_ALUOP_DIVU);
152			`assign div_tmp = mul_prod_r[63:32] - y;`
153			`else
154			`assign alu_op_div = 1'b0;`
155			`assign alu_op_div_divu = 1'b0;`
156			`endif
157	504	lampret
158			`//`
159	1035	lampret	`// Select result of current ALU operation to be forwarded`
160			`// to next instruction and to WB stage`
161			`//`
162			`always @(alu_op or mul_prod_r or mac_r or a or b)`
163			`casex(alu_op) // synopsys parallel_case`
164			`ifdef OR1200_IMPL_DIV
165			`OR1200_ALUOP_DIV:
166			`result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];`
167			`OR1200_ALUOP_DIVU,
168			`endif
169			`OR1200_ALUOP_MUL: begin
170			`result = mul_prod_r[31:0];`
171			`end`
172			`default:`
173			`result = mac_r[59:28];`
174			`endcase`
175
176			`//`
177	504	lampret	`// Instantiation of the multiplier`
178			`//`
179			`ifdef OR1200_ASIC_MULTP2_32X32
180			`or1200_amultp2_32x32 or1200_amultp2_32x32(`
181			`.X(x),`
182			`.Y(y),`
183			`.RST(rst),`
184			`.CLK(clk),`
185			`.P(mul_prod)`
186			`);`
187			`else
188			`or1200_gmultp2_32x32 or1200_gmultp2_32x32(`
189			`.X(x),`
190			`.Y(y),`
191			`.RST(rst),`
192			`.CLK(clk),`
193			`.P(mul_prod)`
194			`);`
195			`endif
196
197			`//`
198	1035	lampret	`// Registered output from the multiplier and`
199			`// an optional divider`
200	504	lampret	`//`
201			`always @(posedge rst or posedge clk)`
202	1035	lampret	`if (rst) begin`
203	504	lampret	`mul_prod_r <= #1 64'h0000_0000_0000_0000;`
204	1035	lampret	`div_free <= #1 1'b1;`
205			`ifdef OR1200_IMPL_DIV
206			`div_cntr <= #1 6'b00_0000;`
207			`endif
208			`end`
209			`ifdef OR1200_IMPL_DIV
210			`else if (\|div_cntr) begin`
211			`if (div_tmp[31])`
212			`mul_prod_r <= #1 {mul_prod_r[62:0], 1'b0};`
213			`else`
214			`mul_prod_r <= #1 {div_tmp[30:0], mul_prod_r[31:0], 1'b1};`
215			`div_cntr <= #1 div_cntr - 1'b1;`
216			`end`
217			`else if (alu_op_div_divu && div_free) begin`
218			`mul_prod_r <= #1 {31'b0, x[31:0], 1'b0};`
219			`div_cntr <= #1 6'b10_0000;`
220			`div_free <= #1 1'b0;`
221			`end`
222			`endif
223			`else if (div_free \| !ex_freeze) begin`
224	504	lampret	`mul_prod_r <= #1 mul_prod[63:0];`
225	1035	lampret	`div_free <= #1 1'b1;`
226			`end`
227	504	lampret
228			`//`
229	1035	lampret	`// Propagation of l.mac opcode`
230	504	lampret	`//`
231			`always @(posedge clk or posedge rst)`
232			`if (rst)`
233			mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
234			`else`
235			`mac_op_r1 <= #1 mac_op;`
236
237			`//`
238			`// Propagation of l.mac opcode`
239			`//`
240			`always @(posedge clk or posedge rst)`
241			`if (rst)`
242			mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
243			`else`
244			`mac_op_r2 <= #1 mac_op_r1;`
245
246			`//`
247			`// Propagation of l.mac opcode`
248			`//`
249			`always @(posedge clk or posedge rst)`
250			`if (rst)`
251			mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
252			`else`
253			`mac_op_r3 <= #1 mac_op_r2;`
254
255			`//`
256			`// Implementation of MAC`
257			`//`
258			`always @(posedge rst or posedge clk)`
259			`if (rst)`
260			`mac_r <= #1 64'h0000_0000_0000_0000;`
261			`ifdef OR1200_MAC_SPR_WE
262			`else if (spr_maclo_we)`
263			`mac_r[31:0] <= #1 spr_dat_i;`
264			`else if (spr_machi_we)`
265			`mac_r[63:32] <= #1 spr_dat_i;`
266			`endif
267			else if (mac_op_r3 == `OR1200_MACOP_MAC)
268			`mac_r <= #1 mac_r + mul_prod_r;`
269			else if (mac_op_r3 == `OR1200_MACOP_MSB)
270			`mac_r <= #1 mac_r - mul_prod_r;`
271			`else if (macrc_op & !ex_freeze)`
272			`mac_r <= #1 64'h0000_0000_0000_0000;`
273
274			`//`
275			`// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions`
276			`// in EX stage (e.g. inside multiplier)`
277	1035	lampret	`// This stall signal is also used by the divider.`
278	504	lampret	`//`
279			`always @(posedge rst or posedge clk)`
280			`if (rst)`
281			`mac_stall_r <= #1 1'b0;`
282			`else`
283	1035	lampret	`mac_stall_r <= #1 (\|mac_op \| (\|mac_op_r1) \| (\|mac_op_r2)) & id_macrc_op`
284			`ifdef OR1200_IMPL_DIV
285			`\| (\|div_cntr)`
286			`endif
287			`;`
288	504	lampret	`endmodule`

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