URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Blame information for rev 504

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Programmable Interrupt Controller                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PIC according to OR1K architectural specification.          ////
////                                                              ////
////  To Do:                                                      ////
////   None                                                       ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_pic(
        // RISC Internal Interface
        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        pic_wakeup, int_low, int_high,
 
        // PIC Interface
        pic_int
);
 
//
// RISC Internal Interface
//
input           clk;            // Clock
input           rst;            // Reset
input           spr_cs;         // SPR CS
input           spr_write;      // SPR Write
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_dat_i;      // SPR Write Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output          pic_wakeup;     // Wakeup to the PM
output          int_low;        // Low priority interrupt
                                // exception request
output          int_high;       // High priority interrupt
                                // exception request
 
//
// PIC Interface
//
input   [`OR1200_PIC_INTS-1:0]   pic_int;// Interrupt inputs
 
`ifdef OR1200_PIC_IMPLEMENTED
 
//
// PIC Mask Register bits (or no register)
//
`ifdef OR1200_PIC_PICMR
reg     [`OR1200_PIC_INTS-1:2]  picmr;  // PICMR bits
`else
wire    [`OR1200_PIC_INTS-1:2]  picmr;  // No PICMR register
`endif
 
//
// PIC Priority Register bits (or no register)
//
`ifdef OR1200_PIC_PICPR
reg     [`OR1200_PIC_INTS-1:2]  picpr;  // PICPR bits
`else
wire    [`OR1200_PIC_INTS-1:2]  picpr;  // No PICPR register
`endif
 
//
// PIC Status Register bits (or no register)
//
`ifdef OR1200_PIC_PICSR
reg     [`OR1200_PIC_INTS-1:0]   picsr;  // PICSR bits
`else
wire    [`OR1200_PIC_INTS-1:0]   picsr;  // No PICSR register
`endif
 
//
// Internal wires & regs
//
wire            picmr_sel;      // PICMR select
wire            picpr_sel;      // PICPR select
wire            picsr_sel;      // PICSR select
wire    [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
reg     [31:0]   spr_dat_o;      // SPR data out
 
//
// PIC registers address decoder
//
assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
assign picpr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICPR)) ? 1'b1 : 1'b0;
assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
 
//
// Write to PICMR
//
`ifdef OR1200_PIC_PICMR
always @(posedge clk or posedge rst)
        if (rst)
//              picmr <= {`OR1200_PIC_INTS-2{1'b0}};
                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
        else if (picmr_sel && spr_write) begin
                picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
        end
`else
assign picpr = (`OR1200_PIC_INTS)'b1;
`endif
 
//
// Write to PICPR
//
`ifdef OR1200_PIC_PICPR
always @(posedge clk or posedge rst)
        if (rst)
                picpr <= {`OR1200_PIC_INTS-2{1'b0}};
        else if (picpr_sel && spr_write) begin
                picpr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
        end
`else
assign picpr = 0;
`endif
 
//
// Write to PICSR, both CPU and external ints
//
`ifdef OR1200_PIC_PICSR
always @(posedge clk or posedge rst)
        if (rst)
                picsr <= {`OR1200_PIC_INTS-2{1'b0}};
        else if (picsr_sel && spr_write) begin
                picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
        end else
                picsr <= #1 picsr | um_ints;
`else
assign picsr = pic_int;
`endif
 
//
// Read PIC registers
//
always @(spr_addr or picmr or picpr or picsr)
        case (spr_addr[`OR1200_PICOFS_BITS])    // synopsys full_case parallel_case
`ifdef OR1200_PIC_READREGS
                `OR1200_PIC_OFS_PICMR: begin
                                        spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
`ifdef OR1200_PIC_UNUSED_ZERO
                                        spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
                                end
                `OR1200_PIC_OFS_PICPR: begin
                                        spr_dat_o[`OR1200_PIC_INTS-1:0] = {picpr, 2'b0};
`ifdef OR1200_PIC_UNUSED_ZERO
                                        spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
                                end
`endif
                default: begin
                                spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
`ifdef OR1200_PIC_UNUSED_ZERO
                                spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
                        end
        endcase
 
//
// Unmasked interrupts
//
assign um_ints = pic_int & {picmr, 2'b11};
 
//
// Generate int_low
//
assign int_low = (um_ints & {~picpr, 2'b10}) ? 1'b1 : 1'b0;
 
//
// Generate int_high
//
assign int_high = (um_ints & {picpr, 2'b01}) ? 1'b1 : 1'b0;
 
//
// Assert pic_wakeup when either intlow or int_high is asserted
//
assign pic_wakeup = int_low | int_high;
 
`else
 
//
// When PIC is not implemented, drive all outputs as would when PIC is disabled
//
assign int_low = pic_int[1];
assign int_high = pic_int[0];
assign pic_wakeup= int_low | int_high;
 
//
// Read PIC registers
//
`ifdef OR1200_PIC_READREGS
assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
`ifdef OR1200_PIC_UNUSED_ZERO
assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
`endif
`endif
 
`endif
 
endmodule

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Blame information for rev 504

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Programmable Interrupt Controller ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PIC according to OR1K architectural specification. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// None ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.8 2001/10/21 17:57:16 lampret`
48			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
49			`//`
50			`// Revision 1.7 2001/10/14 13:12:10 lampret`
51			`// MP3 version.`
52			`//`
53			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
54			`// no message`
55			`//`
56			`// Revision 1.2 2001/08/09 13:39:33 lampret`
57			`// Major clean-up.`
58			`//`
59			`// Revision 1.1 2001/07/20 00:46:21 lampret`
60			`// Development version of RTL. Libraries are missing.`
61			`//`
62			`//`
63
64			`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67			`include "or1200_defines.v"
68
69			`module or1200_pic(`
70			`// RISC Internal Interface`
71			`clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
72			`pic_wakeup, int_low, int_high,`
73
74			`// PIC Interface`
75			`pic_int`
76			`);`
77
78			`//`
79			`// RISC Internal Interface`
80			`//`
81			`input clk; // Clock`
82			`input rst; // Reset`
83			`input spr_cs; // SPR CS`
84			`input spr_write; // SPR Write`
85			`input [31:0] spr_addr; // SPR Address`
86			`input [31:0] spr_dat_i; // SPR Write Data`
87			`output [31:0] spr_dat_o; // SPR Read Data`
88			`output pic_wakeup; // Wakeup to the PM`
89			`output int_low; // Low priority interrupt`
90			`// exception request`
91			`output int_high; // High priority interrupt`
92			`// exception request`
93
94			`//`
95			`// PIC Interface`
96			`//`
97			input [`OR1200_PIC_INTS-1:0] pic_int;// Interrupt inputs
98
99			`ifdef OR1200_PIC_IMPLEMENTED
100
101			`//`
102			`// PIC Mask Register bits (or no register)`
103			`//`
104			`ifdef OR1200_PIC_PICMR
105			reg [`OR1200_PIC_INTS-1:2] picmr; // PICMR bits
106			`else
107			wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register
108			`endif
109
110			`//`
111			`// PIC Priority Register bits (or no register)`
112			`//`
113			`ifdef OR1200_PIC_PICPR
114			reg [`OR1200_PIC_INTS-1:2] picpr; // PICPR bits
115			`else
116			wire [`OR1200_PIC_INTS-1:2] picpr; // No PICPR register
117			`endif
118
119			`//`
120			`// PIC Status Register bits (or no register)`
121			`//`
122			`ifdef OR1200_PIC_PICSR
123			reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits
124			`else
125			wire [`OR1200_PIC_INTS-1:0] picsr; // No PICSR register
126			`endif
127
128			`//`
129			`// Internal wires & regs`
130			`//`
131			`wire picmr_sel; // PICMR select`
132			`wire picpr_sel; // PICPR select`
133			`wire picsr_sel; // PICSR select`
134			wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
135			`reg [31:0] spr_dat_o; // SPR data out`
136
137			`//`
138			`// PIC registers address decoder`
139			`//`
140			assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
141			assign picpr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICPR)) ? 1'b1 : 1'b0;
142			assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
143
144			`//`
145			`// Write to PICMR`
146			`//`
147			`ifdef OR1200_PIC_PICMR
148			`always @(posedge clk or posedge rst)`
149			`if (rst)`
150			// picmr <= {`OR1200_PIC_INTS-2{1'b0}};
151			picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
152			`else if (picmr_sel && spr_write) begin`
153			picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
154			`end`
155			`else
156			assign picpr = (`OR1200_PIC_INTS)'b1;
157			`endif
158
159			`//`
160			`// Write to PICPR`
161			`//`
162			`ifdef OR1200_PIC_PICPR
163			`always @(posedge clk or posedge rst)`
164			`if (rst)`
165			picpr <= {`OR1200_PIC_INTS-2{1'b0}};
166			`else if (picpr_sel && spr_write) begin`
167			picpr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
168			`end`
169			`else
170			`assign picpr = 0;`
171			`endif
172
173			`//`
174			`// Write to PICSR, both CPU and external ints`
175			`//`
176			`ifdef OR1200_PIC_PICSR
177			`always @(posedge clk or posedge rst)`
178			`if (rst)`
179			picsr <= {`OR1200_PIC_INTS-2{1'b0}};
180			`else if (picsr_sel && spr_write) begin`
181			picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] \| um_ints;
182			`end else`
183			`picsr <= #1 picsr \| um_ints;`
184			`else
185			`assign picsr = pic_int;`
186			`endif
187
188			`//`
189			`// Read PIC registers`
190			`//`
191			`always @(spr_addr or picmr or picpr or picsr)`
192			case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys full_case parallel_case
193			`ifdef OR1200_PIC_READREGS
194			`OR1200_PIC_OFS_PICMR: begin
195			spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
196			`ifdef OR1200_PIC_UNUSED_ZERO
197			spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
198			`endif
199			`end`
200			`OR1200_PIC_OFS_PICPR: begin
201			spr_dat_o[`OR1200_PIC_INTS-1:0] = {picpr, 2'b0};
202			`ifdef OR1200_PIC_UNUSED_ZERO
203			spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
204			`endif
205			`end`
206			`endif
207			`default: begin`
208			spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
209			`ifdef OR1200_PIC_UNUSED_ZERO
210			spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
211			`endif
212			`end`
213			`endcase`
214
215			`//`
216			`// Unmasked interrupts`
217			`//`
218			`assign um_ints = pic_int & {picmr, 2'b11};`
219
220			`//`
221			`// Generate int_low`
222			`//`
223			`assign int_low = (um_ints & {~picpr, 2'b10}) ? 1'b1 : 1'b0;`
224
225			`//`
226			`// Generate int_high`
227			`//`
228			`assign int_high = (um_ints & {picpr, 2'b01}) ? 1'b1 : 1'b0;`
229
230			`//`
231			`// Assert pic_wakeup when either intlow or int_high is asserted`
232			`//`
233			`assign pic_wakeup = int_low \| int_high;`
234
235			`else
236
237			`//`
238			`// When PIC is not implemented, drive all outputs as would when PIC is disabled`
239			`//`
240			`assign int_low = pic_int[1];`
241			`assign int_high = pic_int[0];`
242			`assign pic_wakeup= int_low \| int_high;`
243
244			`//`
245			`// Read PIC registers`
246			`//`
247			`ifdef OR1200_PIC_READREGS
248			assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
249			`ifdef OR1200_PIC_UNUSED_ZERO
250			assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
251			`endif
252			`endif
253
254			`endif
255
256			`endmodule`