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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM with byte write signals ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2003/08/26 09:37:02  simons
// Added support for rams with byte write access.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_2048x32_bw(
`ifdef OR1200_BIST
        // RAM BIST
        scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                   scanb_rst,
                        scanb_si,
                        scanb_en,
                        scanb_clk;
output                  scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input   [3:0]           we;     // Write enable input
input                   oe;     // Output enable input
input   [10:0]          addr;   // address bus inputs
input   [31:0]          di;     // input data bus
output  [31:0]          do;     // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
`endif
 
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x32_bw artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bw_bist artisan_ssp(
`else
art_hssp_2048x32_bw artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si),
        .scanb_so(scanb_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef OR1200_BIST
wire scanb_si_ram_0;
wire scanb_si_ram_1;
wire scanb_si_ram_2;
wire scanb_si_ram_3;
wire scanb_so_ram_0;
wire scanb_so_ram_1;
wire scanb_so_ram_2;
wire scanb_so_ram_3;
assign scanb_si_ram_0 = scanb_si;
assign scanb_si_ram_1 = scanb_so_ram_0;
assign scanb_si_ram_2 = scanb_so_ram_1;
assign scanb_si_ram_3 = scanb_so_ram_2;
assign scanb_so = scanb_so_ram_3;
`endif
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_0(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_0(
`else
vs_hdsp_2048x8 vs_ssp_0(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si_ram_0),
        .scanb_so(scanb_so_ram_0),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[7:0]),
        .WEN(~we[0]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[7:0])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_1(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_1(
`else
vs_hdsp_2048x8 vs_ssp_1(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si_ram_1),
        .scanb_so(scanb_so_ram_1),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[15:8]),
        .WEN(~we[1]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[15:8])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_2(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_2(
`else
vs_hdsp_2048x8 vs_ssp_2(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si_ram_2),
        .scanb_so(scanb_so_ram_2),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[23:16]),
        .WEN(~we[2]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[23:16])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_3(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_3(
`else
vs_hdsp_2048x8 vs_ssp_3(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si_ram_3),
        .scanb_so(scanb_so_ram_3),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[31:24]),
        .WEN(~we[3]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[31:24])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[1:0]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[1:0])
);
 
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:2]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[3:2])
);
 
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[5:4]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[5:4])
);
 
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:6]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[7:6])
);
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[9:8]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[9:8])
);
 
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:10]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[11:10])
);
 
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[13:12]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[13:12])
);
 
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:14]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[15:14])
);
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[17:16]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[17:16])
);
 
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:18]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[19:18])
);
 
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[21:20]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[21:20])
);
 
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:22]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[23:22])
);
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[25:24]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[25:24])
);
 
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:26]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[27:26])
);
 
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[29:28]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[29:28])
);
 
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:30]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[31:30])
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [31:0]        mem_0 [10:0];              // RAM content
reg     [31:0]        mem_1 [10:0];              // RAM content
reg     [31:0]        mem_2 [10:0];              // RAM content
reg     [31:0]        mem_3 [10:0];              // RAM content
reg     [31:0]        do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {32{1'b0}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we) begin
                do_reg[7:0]   <= #1 mem_0[addr];
                do_reg[15:8]  <= #1 mem_1[addr];
                do_reg[23:16] <= #1 mem_2[addr];
                do_reg[31:24] <= #1 mem_3[addr];
        end
        else if (ce && we[0])
                mem_0[addr] <= #1 di[7:0];
        else if (ce && we[1])
                mem_1[addr] <= #1 di[15:8];
        else if (ce && we[2])
                mem_2[addr] <= #1 di[23:16];
        else if (ce && we[3])
                mem_3[addr] <= #1 di[31:24];
 
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [or1k/] [tags/] [rel_24/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32_bw.v] - Blame information for rev 1194

Line No.	Rev	Author	Line
1	1186	simons	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM with byte write signals ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// - Altera LPM ////`
27			`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31			`//// - add additional RAMs ////`
32			`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66	1194	dries	`// Revision 1.1 2003/08/26 09:37:02 simons`
67			`// Added support for rams with byte write access.`
68	1186	simons	`//`
69	1194	dries	`//`
70	1186	simons
71			`// synopsys translate_off`
72			`include "timescale.v"
73			`// synopsys translate_on`
74			`include "or1200_defines.v"
75
76			`module or1200_spram_2048x32_bw(`
77			`ifdef OR1200_BIST
78			`// RAM BIST`
79			`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`
80			`endif
81			`// Generic synchronous single-port RAM interface`
82			`clk, rst, ce, we, oe, addr, di, do`
83			`);`
84
85			`ifdef OR1200_BIST
86			`//`
87			`// RAM BIST`
88			`//`
89			`input scanb_rst,`
90			`scanb_si,`
91			`scanb_en,`
92			`scanb_clk;`
93			`output scanb_so;`
94			`endif
95
96			`//`
97			`// Generic synchronous single-port RAM interface`
98			`//`
99			`input clk; // Clock`
100			`input rst; // Reset`
101			`input ce; // Chip enable input`
102			`input [3:0] we; // Write enable input`
103			`input oe; // Output enable input`
104			`input [10:0] addr; // address bus inputs`
105			`input [31:0] di; // input data bus`
106			`output [31:0] do; // output data bus`
107
108			`//`
109			`// Internal wires and registers`
110			`//`
111
112			`ifdef OR1200_ARTISAN_SSP
113			`else
114			`ifdef OR1200_VIRTUALSILICON_SSP
115			`else
116			`ifdef OR1200_BIST
117			`assign scanb_so = scanb_si;`
118			`endif
119			`endif
120			`endif
121
122
123			`ifdef OR1200_ARTISAN_SSP
124
125			`//`
126			`// Instantiation of ASIC memory:`
127			`//`
128			`// Artisan Synchronous Single-Port RAM (ra1sh)`
129			`//`
130			`ifdef UNUSED
131			`art_hssp_2048x32_bw artisan_ssp(`
132			`else
133			`ifdef OR1200_BIST
134			`art_hssp_2048x32_bw_bist artisan_ssp(`
135			`else
136			`art_hssp_2048x32_bw artisan_ssp(`
137			`endif
138			`endif
139			`ifdef OR1200_BIST
140			`// RAM BIST`
141			`.scanb_rst(scanb_rst),`
142			`.scanb_si(scanb_si),`
143			`.scanb_so(scanb_so),`
144			`.scanb_en(scanb_en),`
145			`.scanb_clk(scanb_clk),`
146			`endif
147			`.CLK(clk),`
148			`.CEN(~ce),`
149			`.WEN(~we),`
150			`.A(addr),`
151			`.D(di),`
152			`.OEN(~oe),`
153			`.Q(do)`
154			`);`
155
156			`else
157
158			`ifdef OR1200_AVANT_ATP
159
160			`//`
161			`// Instantiation of ASIC memory:`
162			`//`
163			`// Avant! Asynchronous Two-Port RAM`
164			`//`
165			`avant_atp avant_atp(`
166			`.web(~we),`
167			`.reb(),`
168			`.oeb(~oe),`
169			`.rcsb(),`
170			`.wcsb(),`
171			`.ra(addr),`
172			`.wa(addr),`
173			`.di(di),`
174			`.do(do)`
175			`);`
176
177			`else
178
179			`ifdef OR1200_VIRAGE_SSP
180
181			`//`
182			`// Instantiation of ASIC memory:`
183			`//`
184			`// Virage Synchronous 1-port R/W RAM`
185			`//`
186			`virage_ssp virage_ssp(`
187			`.clk(clk),`
188			`.adr(addr),`
189			`.d(di),`
190			`.we(we),`
191			`.oe(oe),`
192			`.me(ce),`
193			`.q(do)`
194			`);`
195
196			`else
197
198			`ifdef OR1200_VIRTUALSILICON_SSP
199
200			`//`
201			`// Instantiation of ASIC memory:`
202			`//`
203			`// Virtual Silicon Single-Port Synchronous SRAM`
204			`//`
205			`ifdef OR1200_BIST
206			`wire scanb_si_ram_0;`
207			`wire scanb_si_ram_1;`
208			`wire scanb_si_ram_2;`
209			`wire scanb_si_ram_3;`
210			`wire scanb_so_ram_0;`
211			`wire scanb_so_ram_1;`
212			`wire scanb_so_ram_2;`
213			`wire scanb_so_ram_3;`
214			`assign scanb_si_ram_0 = scanb_si;`
215			`assign scanb_si_ram_1 = scanb_so_ram_0;`
216			`assign scanb_si_ram_2 = scanb_so_ram_1;`
217			`assign scanb_si_ram_3 = scanb_so_ram_2;`
218			`assign scanb_so = scanb_so_ram_3;`
219			`endif
220
221			`ifdef UNUSED
222			`vs_hdsp_2048x8 vs_ssp_0(`
223			`else
224			`ifdef OR1200_BIST
225			`vs_hdsp_2048x8_bist vs_ssp_0(`
226			`else
227			`vs_hdsp_2048x8 vs_ssp_0(`
228			`endif
229			`endif
230			`ifdef OR1200_BIST
231			`// RAM BIST`
232			`.scanb_rst(scanb_rst),`
233			`.scanb_si(scanb_si_ram_0),`
234			`.scanb_so(scanb_so_ram_0),`
235			`.scanb_en(scanb_en),`
236			`.scanb_clk(scanb_clk),`
237			`endif
238			`.CK(clk),`
239			`.ADR(addr),`
240			`.DI(di[7:0]),`
241			`.WEN(~we[0]),`
242			`.CEN(~ce),`
243			`.OEN(~oe),`
244			`.DOUT(do[7:0])`
245			`);`
246
247			`ifdef UNUSED
248			`vs_hdsp_2048x8 vs_ssp_1(`
249			`else
250			`ifdef OR1200_BIST
251			`vs_hdsp_2048x8_bist vs_ssp_1(`
252			`else
253			`vs_hdsp_2048x8 vs_ssp_1(`
254			`endif
255			`endif
256			`ifdef OR1200_BIST
257			`// RAM BIST`
258			`.scanb_rst(scanb_rst),`
259			`.scanb_si(scanb_si_ram_1),`
260			`.scanb_so(scanb_so_ram_1),`
261			`.scanb_en(scanb_en),`
262			`.scanb_clk(scanb_clk),`
263			`endif
264			`.CK(clk),`
265			`.ADR(addr),`
266			`.DI(di[15:8]),`
267			`.WEN(~we[1]),`
268			`.CEN(~ce),`
269			`.OEN(~oe),`
270			`.DOUT(do[15:8])`
271			`);`
272
273			`ifdef UNUSED
274			`vs_hdsp_2048x8 vs_ssp_2(`
275			`else
276			`ifdef OR1200_BIST
277			`vs_hdsp_2048x8_bist vs_ssp_2(`
278			`else
279			`vs_hdsp_2048x8 vs_ssp_2(`
280			`endif
281			`endif
282			`ifdef OR1200_BIST
283			`// RAM BIST`
284			`.scanb_rst(scanb_rst),`
285			`.scanb_si(scanb_si_ram_2),`
286			`.scanb_so(scanb_so_ram_2),`
287			`.scanb_en(scanb_en),`
288			`.scanb_clk(scanb_clk),`
289			`endif
290			`.CK(clk),`
291			`.ADR(addr),`
292			`.DI(di[23:16]),`
293			`.WEN(~we[2]),`
294			`.CEN(~ce),`
295			`.OEN(~oe),`
296			`.DOUT(do[23:16])`
297			`);`
298
299			`ifdef UNUSED
300			`vs_hdsp_2048x8 vs_ssp_3(`
301			`else
302			`ifdef OR1200_BIST
303			`vs_hdsp_2048x8_bist vs_ssp_3(`
304			`else
305			`vs_hdsp_2048x8 vs_ssp_3(`
306			`endif
307			`endif
308			`ifdef OR1200_BIST
309			`// RAM BIST`
310			`.scanb_rst(scanb_rst),`
311			`.scanb_si(scanb_si_ram_3),`
312			`.scanb_so(scanb_so_ram_3),`
313			`.scanb_en(scanb_en),`
314			`.scanb_clk(scanb_clk),`
315			`endif
316			`.CK(clk),`
317			`.ADR(addr),`
318			`.DI(di[31:24]),`
319			`.WEN(~we[3]),`
320			`.CEN(~ce),`
321			`.OEN(~oe),`
322			`.DOUT(do[31:24])`
323			`);`
324
325			`else
326
327			`ifdef OR1200_XILINX_RAMB4
328
329			`//`
330			`// Instantiation of FPGA memory:`
331			`//`
332			`// Virtex/Spartan2`
333			`//`
334
335			`//`
336			`// Block 0`
337			`//`
338			`RAMB4_S2 ramb4_s2_0(`
339			`.CLK(clk),`
340			`.RST(rst),`
341			`.ADDR(addr),`
342			`.DI(di[1:0]),`
343			`.EN(ce),`
344			`.WE(we[0]),`
345			`.DO(do[1:0])`
346			`);`
347
348			`//`
349			`// Block 1`
350			`//`
351			`RAMB4_S2 ramb4_s2_1(`
352			`.CLK(clk),`
353			`.RST(rst),`
354			`.ADDR(addr),`
355			`.DI(di[3:2]),`
356			`.EN(ce),`
357			`.WE(we[0]),`
358			`.DO(do[3:2])`
359			`);`
360
361			`//`
362			`// Block 2`
363			`//`
364			`RAMB4_S2 ramb4_s2_2(`
365			`.CLK(clk),`
366			`.RST(rst),`
367			`.ADDR(addr),`
368			`.DI(di[5:4]),`
369			`.EN(ce),`
370			`.WE(we[0]),`
371			`.DO(do[5:4])`
372			`);`
373
374			`//`
375			`// Block 3`
376			`//`
377			`RAMB4_S2 ramb4_s2_3(`
378			`.CLK(clk),`
379			`.RST(rst),`
380			`.ADDR(addr),`
381			`.DI(di[7:6]),`
382			`.EN(ce),`
383			`.WE(we[0]),`
384			`.DO(do[7:6])`
385	1194	dries	`);`
386	1186	simons	`//`
387			`// Block 4`
388			`//`
389			`RAMB4_S2 ramb4_s2_4(`
390			`.CLK(clk),`
391			`.RST(rst),`
392			`.ADDR(addr),`
393			`.DI(di[9:8]),`
394			`.EN(ce),`
395			`.WE(we[1]),`
396			`.DO(do[9:8])`
397			`);`
398
399			`//`
400			`// Block 5`
401			`//`
402			`RAMB4_S2 ramb4_s2_5(`
403			`.CLK(clk),`
404			`.RST(rst),`
405			`.ADDR(addr),`
406			`.DI(di[11:10]),`
407			`.EN(ce),`
408			`.WE(we[1]),`
409			`.DO(do[11:10])`
410			`);`
411
412			`//`
413			`// Block 6`
414			`//`
415			`RAMB4_S2 ramb4_s2_6(`
416			`.CLK(clk),`
417			`.RST(rst),`
418			`.ADDR(addr),`
419			`.DI(di[13:12]),`
420			`.EN(ce),`
421			`.WE(we[1]),`
422			`.DO(do[13:12])`
423			`);`
424
425			`//`
426			`// Block 7`
427			`//`
428			`RAMB4_S2 ramb4_s2_7(`
429			`.CLK(clk),`
430			`.RST(rst),`
431			`.ADDR(addr),`
432			`.DI(di[15:14]),`
433			`.EN(ce),`
434			`.WE(we[1]),`
435			`.DO(do[15:14])`
436	1194	dries	`);`
437	1186	simons	`//`
438			`// Block 8`
439			`//`
440			`RAMB4_S2 ramb4_s2_8(`
441			`.CLK(clk),`
442			`.RST(rst),`
443			`.ADDR(addr),`
444			`.DI(di[17:16]),`
445			`.EN(ce),`
446			`.WE(we[2]),`
447			`.DO(do[17:16])`
448			`);`
449
450			`//`
451			`// Block 9`
452			`//`
453			`RAMB4_S2 ramb4_s2_9(`
454			`.CLK(clk),`
455			`.RST(rst),`
456			`.ADDR(addr),`
457			`.DI(di[19:18]),`
458			`.EN(ce),`
459			`.WE(we[2]),`
460			`.DO(do[19:18])`
461			`);`
462
463			`//`
464			`// Block 10`
465			`//`
466			`RAMB4_S2 ramb4_s2_10(`
467			`.CLK(clk),`
468			`.RST(rst),`
469			`.ADDR(addr),`
470			`.DI(di[21:20]),`
471			`.EN(ce),`
472			`.WE(we[2]),`
473			`.DO(do[21:20])`
474			`);`
475
476			`//`
477			`// Block 11`
478			`//`
479			`RAMB4_S2 ramb4_s2_11(`
480			`.CLK(clk),`
481			`.RST(rst),`
482			`.ADDR(addr),`
483			`.DI(di[23:22]),`
484			`.EN(ce),`
485			`.WE(we[2]),`
486			`.DO(do[23:22])`
487	1194	dries	`);`
488	1186	simons	`//`
489			`// Block 12`
490			`//`
491			`RAMB4_S2 ramb4_s2_12(`
492			`.CLK(clk),`
493			`.RST(rst),`
494			`.ADDR(addr),`
495			`.DI(di[25:24]),`
496			`.EN(ce),`
497			`.WE(we[3]),`
498			`.DO(do[25:24])`
499			`);`
500
501			`//`
502			`// Block 13`
503			`//`
504			`RAMB4_S2 ramb4_s2_13(`
505			`.CLK(clk),`
506			`.RST(rst),`
507			`.ADDR(addr),`
508			`.DI(di[27:26]),`
509			`.EN(ce),`
510			`.WE(we[3]),`
511			`.DO(do[27:26])`
512			`);`
513
514			`//`
515			`// Block 14`
516			`//`
517			`RAMB4_S2 ramb4_s2_14(`
518			`.CLK(clk),`
519			`.RST(rst),`
520			`.ADDR(addr),`
521			`.DI(di[29:28]),`
522			`.EN(ce),`
523			`.WE(we[3]),`
524			`.DO(do[29:28])`
525			`);`
526
527			`//`
528			`// Block 15`
529			`//`
530			`RAMB4_S2 ramb4_s2_15(`
531			`.CLK(clk),`
532			`.RST(rst),`
533			`.ADDR(addr),`
534			`.DI(di[31:30]),`
535			`.EN(ce),`
536			`.WE(we[3]),`
537			`.DO(do[31:30])`
538	1194	dries	`);`
539	1186	simons
540			`else
541
542			`//`
543			`// Generic single-port synchronous RAM model`
544			`//`
545
546			`//`
547			`// Generic RAM's registers and wires`
548			`//`
549			`reg [31:0] mem_0 [10:0]; // RAM content`
550			`reg [31:0] mem_1 [10:0]; // RAM content`
551			`reg [31:0] mem_2 [10:0]; // RAM content`
552			`reg [31:0] mem_3 [10:0]; // RAM content`
553			`reg [31:0] do_reg; // RAM data output register`
554
555			`//`
556			`// Data output drivers`
557			`//`
558			`assign do = (oe) ? do_reg : {32{1'b0}};`
559
560			`//`
561			`// RAM read and write`
562			`//`
563			`always @(posedge clk)`
564			`if (ce && !we) begin`
565			`do_reg[7:0] <= #1 mem_0[addr];`
566			`do_reg[15:8] <= #1 mem_1[addr];`
567			`do_reg[23:16] <= #1 mem_2[addr];`
568			`do_reg[31:24] <= #1 mem_3[addr];`
569	1194	dries	`end`
570	1186	simons	`else if (ce && we[0])`
571			`mem_0[addr] <= #1 di[7:0];`
572			`else if (ce && we[1])`
573			`mem_1[addr] <= #1 di[15:8];`
574			`else if (ce && we[2])`
575			`mem_2[addr] <= #1 di[23:16];`
576			`else if (ce && we[3])`
577			`mem_3[addr] <= #1 di[31:24];`
578
579			`endif // !OR1200_XILINX_RAMB4_S16
580			`endif // !OR1200_VIRTUALSILICON_SSP
581			`endif // !OR1200_VIRAGE_SSP
582			`endif // !OR1200_AVANT_ATP
583			`endif // !OR1200_ARTISAN_SSP
584
585			`endmodule`