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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Blame information for rev 1765

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1 504 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's ALU                                                ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  ALU                                                         ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
//
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// CVS Revision History
45
//
46
// $Log: not supported by cvs2svn $
47 1159 lampret
// Revision 1.10  2002/09/08 05:52:16  lampret
48
// Added optional l.div/l.divu insns. By default they are disabled.
49
//
50 1035 lampret
// Revision 1.9  2002/09/07 19:16:10  lampret
51
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
52
//
53 1033 lampret
// Revision 1.8  2002/09/07 05:42:02  lampret
54
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
55
//
56 1032 lampret
// Revision 1.7  2002/09/03 22:28:21  lampret
57
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
58
//
59 1022 lampret
// Revision 1.6  2002/03/29 16:40:10  lampret
60
// Added a directive to ignore signed division variables that are only used in simulation.
61
//
62 795 lampret
// Revision 1.5  2002/03/29 16:33:59  lampret
63
// Added again just recently removed full_case directive
64
//
65 794 lampret
// Revision 1.4  2002/03/29 15:16:53  lampret
66
// Some of the warnings fixed.
67
//
68 788 lampret
// Revision 1.3  2002/01/28 01:15:59  lampret
69
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
70
//
71 617 lampret
// Revision 1.2  2002/01/14 06:18:22  lampret
72
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
73
//
74 562 lampret
// Revision 1.1  2002/01/03 08:16:15  lampret
75
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
76
//
77 504 lampret
// Revision 1.10  2001/11/12 01:45:40  lampret
78
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
79
//
80
// Revision 1.9  2001/10/21 17:57:16  lampret
81
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
82
//
83
// Revision 1.8  2001/10/19 23:28:45  lampret
84
// Fixed some synthesis warnings. Configured with caches and MMUs.
85
//
86
// Revision 1.7  2001/10/14 13:12:09  lampret
87
// MP3 version.
88
//
89
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
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// no message
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//
92
// Revision 1.2  2001/08/09 13:39:33  lampret
93
// Major clean-up.
94
//
95
// Revision 1.1  2001/07/20 00:46:03  lampret
96
// Development version of RTL. Libraries are missing.
97
//
98
//
99
 
100
// synopsys translate_off
101
`include "timescale.v"
102
// synopsys translate_on
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`include "or1200_defines.v"
104
 
105
module or1200_alu(
106
        a, b, mult_mac_result, macrc_op,
107
        alu_op, shrot_op, comp_op,
108 1032 lampret
        result, flagforw, flag_we,
109
        cyforw, cy_we, carry
110 504 lampret
);
111
 
112
parameter width = `OR1200_OPERAND_WIDTH;
113
 
114
//
115
// I/O
116
//
117
input   [width-1:0]              a;
118
input   [width-1:0]              b;
119
input   [width-1:0]              mult_mac_result;
120
input                           macrc_op;
121
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
122
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
123
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
124
output  [width-1:0]              result;
125
output                          flagforw;
126
output                          flag_we;
127 1032 lampret
output                          cyforw;
128
output                          cy_we;
129
input                           carry;
130 504 lampret
 
131
//
132
// Internal wires and regs
133
//
134
reg     [width-1:0]              result;
135
reg     [width-1:0]              shifted_rotated;
136
reg                             flagforw;
137 617 lampret
reg                             flagcomp;
138 504 lampret
reg                             flag_we;
139 1032 lampret
reg                             cy_we;
140 504 lampret
wire    [width-1:0]              comp_a;
141
wire    [width-1:0]              comp_b;
142
`ifdef OR1200_IMPL_ALU_COMP1
143
wire                            a_eq_b;
144
wire                            a_lt_b;
145
`endif
146 617 lampret
wire    [width-1:0]              result_sum;
147 1032 lampret
`ifdef OR1200_IMPL_ADDC
148
wire    [width-1:0]              result_csum;
149 1033 lampret
wire                            cy_csum;
150 1032 lampret
`endif
151 617 lampret
wire    [width-1:0]              result_and;
152 1033 lampret
wire                            cy_sum;
153
reg                             cyforw;
154 504 lampret
 
155
//
156
// Combinatorial logic
157
//
158
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
159
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
160
`ifdef OR1200_IMPL_ALU_COMP1
161
assign a_eq_b = (comp_a == comp_b);
162
assign a_lt_b = (comp_a < comp_b);
163
`endif
164 1033 lampret
assign {cy_sum, result_sum} = a + b;
165 1032 lampret
`ifdef OR1200_IMPL_ADDC
166 1033 lampret
assign {cy_csum, result_csum} = a + b + carry;
167 1032 lampret
`endif
168 617 lampret
assign result_and = a & b;
169 504 lampret
 
170
//
171
// Simulation check for bad ALU behavior
172
//
173
`ifdef OR1200_WARNINGS
174
// synopsys translate_off
175
always @(result) begin
176
        if (result === 32'bx)
177
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
178
end
179
// synopsys translate_on
180
`endif
181
 
182
//
183
// Central part of the ALU
184
//
185 617 lampret
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
186 1022 lampret
`ifdef OR1200_CASE_DEFAULT
187
        casex (alu_op)          // synopsys parallel_case
188
`else
189
        casex (alu_op)          // synopsys full_case parallel_case
190
`endif
191 504 lampret
                `OR1200_ALUOP_SHROT : begin
192
                                result = shifted_rotated;
193
                end
194
                `OR1200_ALUOP_ADD : begin
195 617 lampret
                                result = result_sum;
196 504 lampret
                end
197 1032 lampret
`ifdef OR1200_IMPL_ADDC
198
                `OR1200_ALUOP_ADDC : begin
199
                                result = result_csum;
200
                end
201
`endif
202 504 lampret
                `OR1200_ALUOP_SUB : begin
203
                                result = a - b;
204
                end
205
                `OR1200_ALUOP_XOR : begin
206
                                result = a ^ b;
207
                end
208
                `OR1200_ALUOP_OR  : begin
209
                                result = a | b;
210
                end
211
                `OR1200_ALUOP_IMM : begin
212
                                result = b;
213
                end
214
                `OR1200_ALUOP_MOVHI : begin
215
                                if (macrc_op) begin
216
                                        result = mult_mac_result;
217
                                end
218
                                else begin
219
                                        result = b << 16;
220
                                end
221
                end
222 1159 lampret
`ifdef OR1200_MULT_IMPLEMENTED
223 1035 lampret
`ifdef OR1200_IMPL_DIV
224
                `OR1200_ALUOP_DIV,
225
                `OR1200_ALUOP_DIVU,
226
`endif
227 504 lampret
                `OR1200_ALUOP_MUL : begin
228
                                result = mult_mac_result;
229
                end
230 1159 lampret
`endif
231 1022 lampret
`ifdef OR1200_CASE_DEFAULT
232
                default: begin
233
`else
234
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND
235
`endif
236 617 lampret
                                result = result_and;
237
                end
238
        endcase
239
end
240
 
241
//
242
// Generate flag and flag write enable
243
//
244
always @(alu_op or result_sum or result_and or flagcomp) begin
245 788 lampret
        casex (alu_op)          // synopsys parallel_case
246 1032 lampret
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
247 617 lampret
                `OR1200_ALUOP_ADD : begin
248
                        flagforw = (result_sum == 32'h0000_0000);
249 1032 lampret
                        flag_we = 1'b1;
250 617 lampret
                end
251 1032 lampret
`ifdef OR1200_IMPL_ADDC
252
                `OR1200_ALUOP_ADDC : begin
253
                        flagforw = (result_csum == 32'h0000_0000);
254
                        flag_we = 1'b1;
255
                end
256
`endif
257 617 lampret
                `OR1200_ALUOP_AND: begin
258
                        flagforw = (result_and == 32'h0000_0000);
259 1032 lampret
                        flag_we = 1'b1;
260 617 lampret
                end
261 1032 lampret
`endif
262 504 lampret
                `OR1200_ALUOP_COMP: begin
263 617 lampret
                        flagforw = flagcomp;
264
                        flag_we = 1'b1;
265 504 lampret
                end
266 617 lampret
                default: begin
267
                        flagforw = 1'b0;
268
                        flag_we = 1'b0;
269 504 lampret
                end
270
        endcase
271
end
272
 
273
//
274 1032 lampret
// Generate SR[CY] write enable
275
//
276 1035 lampret
always @(alu_op or cy_sum
277
`ifdef OR1200_IMPL_ADDC
278
        or cy_csum
279
`endif
280
        ) begin
281 1032 lampret
        casex (alu_op)          // synopsys parallel_case
282
`ifdef OR1200_IMPL_ADDC
283 1033 lampret
                `OR1200_ALUOP_ADD : begin
284
                        cyforw = cy_sum;
285 1032 lampret
                        cy_we = 1'b1;
286
                end
287 1033 lampret
                `OR1200_ALUOP_ADDC: begin
288
                        cyforw = cy_csum;
289
                        cy_we = 1'b1;
290
                end
291 1032 lampret
`endif
292
                default: begin
293 1033 lampret
                        cyforw = 1'b0;
294 1032 lampret
                        cy_we = 1'b0;
295
                end
296
        endcase
297
end
298
 
299
//
300 504 lampret
// Shifts and rotation
301
//
302
always @(shrot_op or a or b) begin
303
        case (shrot_op)         // synopsys parallel_case
304 562 lampret
        `OR1200_SHROTOP_SLL :
305 504 lampret
                                shifted_rotated = (a << b[4:0]);
306
                `OR1200_SHROTOP_SRL :
307
                                shifted_rotated = (a >> b[4:0]);
308 562 lampret
 
309 504 lampret
`ifdef OR1200_IMPL_ALU_ROTATE
310
                `OR1200_SHROTOP_ROR :
311
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
312
`endif
313
                default:
314
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
315
        endcase
316
end
317
 
318
//
319
// First type of compare implementation
320
//
321
`ifdef OR1200_IMPL_ALU_COMP1
322
always @(comp_op or a_eq_b or a_lt_b) begin
323 788 lampret
        case(comp_op[2:0])       // synopsys parallel_case
324 504 lampret
                `OR1200_COP_SFEQ:
325 617 lampret
                        flagcomp = a_eq_b;
326 504 lampret
                `OR1200_COP_SFNE:
327 617 lampret
                        flagcomp = ~a_eq_b;
328 504 lampret
                `OR1200_COP_SFGT:
329 617 lampret
                        flagcomp = ~(a_eq_b | a_lt_b);
330 504 lampret
                `OR1200_COP_SFGE:
331 617 lampret
                        flagcomp = ~a_lt_b;
332 504 lampret
                `OR1200_COP_SFLT:
333 617 lampret
                        flagcomp = a_lt_b;
334 504 lampret
                `OR1200_COP_SFLE:
335 617 lampret
                        flagcomp = a_eq_b | a_lt_b;
336 504 lampret
                default:
337 617 lampret
                        flagcomp = 1'b0;
338 504 lampret
        endcase
339
end
340
`endif
341
 
342
//
343
// Second type of compare implementation
344
//
345
`ifdef OR1200_IMPL_ALU_COMP2
346
always @(comp_op or comp_a or comp_b) begin
347 788 lampret
        case(comp_op[2:0])       // synopsys parallel_case
348 504 lampret
                `OR1200_COP_SFEQ:
349 617 lampret
                        flagcomp = (comp_a == comp_b);
350 504 lampret
                `OR1200_COP_SFNE:
351 617 lampret
                        flagcomp = (comp_a != comp_b);
352 504 lampret
                `OR1200_COP_SFGT:
353 617 lampret
                        flagcomp = (comp_a > comp_b);
354 504 lampret
                `OR1200_COP_SFGE:
355 617 lampret
                        flagcomp = (comp_a >= comp_b);
356 504 lampret
                `OR1200_COP_SFLT:
357 617 lampret
                        flagcomp = (comp_a < comp_b);
358 504 lampret
                `OR1200_COP_SFLE:
359 617 lampret
                        flagcomp = (comp_a <= comp_b);
360 504 lampret
                default:
361 617 lampret
                        flagcomp = 1'b0;
362 504 lampret
        endcase
363
end
364
`endif
365
 
366
endmodule

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