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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2002/03/29 15:16:55  lampret
// Some of the warnings fixed.
//
// Revision 1.6  2002/03/28 19:10:40  lampret
// Optimized cache controller FSM.
//
// Revision 1.1.1.1  2002/03/21 16:55:45  lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.5  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_DCFSM_IDLE       3'd0
`define OR1200_DCFSM_CLOAD      3'd1
`define OR1200_DCFSM_LREFILL3   3'd2
`define OR1200_DCFSM_CSTORE     3'd3
`define OR1200_DCFSM_SREFILL4   3'd4
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module or1200_dc_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level DC
        dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
        burst, tag_we, dc_addr
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           dc_en;
input                           dcqmem_cycstb_i;
input                           dcqmem_ci_i;
input                           dcqmem_we_i;
input   [3:0]                    dcqmem_sel_i;
input                           tagcomp_miss;
input                           biudata_valid;
input                           biudata_error;
input   [31:0]                   start_addr;
output  [31:0]                   saved_addr;
output  [3:0]                    dcram_we;
output                          biu_read;
output                          biu_write;
output                          first_hit_ack;
output                          first_miss_ack;
output                          first_miss_err;
output                          burst;
output                          tag_we;
output  [31:0]                   dc_addr;
 
//
// Internal wires and regs
//
reg     [31:0]                   saved_addr_r;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             hitmiss_eval;
reg                             store;
reg                             load;
reg                             cache_inhibit;
wire                            first_store_hit_ack;
 
//
// Generate of DCRAM write enables
//
assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
 
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
assign biu_write = store;
 
assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
assign saved_addr = saved_addr_r;
 
//
// Assert for cache hit first word ready
// Assert for store cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i | first_store_hit_ack;
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
 
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
                | (state == `OR1200_DCFSM_LREFILL3)
`ifdef OR1200_DC_STORE_REFILL
                | (state == `OR1200_DCFSM_SREFILL4)
`endif
                ;
 
//
// Main DC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_DCFSM_IDLE;
                saved_addr_r <= #1 32'b0;
                hitmiss_eval <= #1 1'b0;
                store <= #1 1'b0;
                load <= #1 1'b0;
                cnt <= #1 3'b000;
                cache_inhibit <= #1 1'b0;
        end
        else
        case (state)    // synopsys parallel_case
                `OR1200_DCFSM_IDLE :
                        if (dc_en & dcqmem_cycstb_i & dcqmem_we_i) begin        // store
                                state <= #1 `OR1200_DCFSM_CSTORE;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                store <= #1 1'b1;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (dc_en & dcqmem_cycstb_i) begin         // load
                                state <= #1 `OR1200_DCFSM_CLOAD;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                                cache_inhibit <= #1 1'b0;
                        end
                        else begin                                                      // idle
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                `OR1200_DCFSM_CLOAD: begin              // load
                        if (dcqmem_cycstb_i & dcqmem_ci_i)
                                cache_inhibit <= #1 1'b1;
                        if (hitmiss_eval)
                                saved_addr_r[31:13] <= #1 start_addr[31:13];
                        if ((hitmiss_eval & !dcqmem_cycstb_i) ||                                        // load aborted (usually caused by DMMU)
                            (biudata_error) ||                                                                          // load terminated with an error
                            ((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin      // load from cache-inhibited area
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (tagcomp_miss & biudata_valid) begin    // load missed, finish current external load and refill
                                state <= #1 `OR1200_DCFSM_LREFILL3;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
                                hitmiss_eval <= #1 1'b0;
                                cnt <= #1 `OR1200_DCLS-2;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (!tagcomp_miss & !dcqmem_ci_i) begin    // load hit, finish immediately
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else                                            // load in-progress
                                hitmiss_eval <= #1 1'b0;
                end
                `OR1200_DCFSM_LREFILL3 : begin
                        if (biudata_valid && (|cnt)) begin              // refill ack, more loads to come
                                cnt <= #1 cnt - 1'd1;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                        end
                end
                `OR1200_DCFSM_CSTORE: begin             // store
                        if (dcqmem_cycstb_i & dcqmem_ci_i)
                                cache_inhibit <= #1 1'b1;
                        if (hitmiss_eval)
                                saved_addr_r[31:13] <= #1 start_addr[31:13];
                        if ((hitmiss_eval & !dcqmem_cycstb_i) ||        // store aborted (usually caused by DMMU)
                            (biudata_error) ||                                          // store terminated with an error
                            ((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin      // store to cache-inhibited area
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
`ifdef OR1200_DC_STORE_REFILL
                        else if (tagcomp_miss & biudata_valid) begin    // store missed, finish write-through and do load refill
                                state <= #1 `OR1200_DCFSM_SREFILL4;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                                cnt <= #1 `OR1200_DCLS-1;
                                cache_inhibit <= #1 1'b0;
                        end
`endif
                        else if (biudata_valid) begin                   // store hit, finish write-through
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else                                            // store write-through in-progress
                                hitmiss_eval <= #1 1'b0;
                        end
`ifdef OR1200_DC_STORE_REFILL
                `OR1200_DCFSM_SREFILL4 : begin
                        if (biudata_valid && (|cnt)) begin              // refill ack, more loads to come
                                cnt <= #1 cnt - 1'd1;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                        end
                end
`endif
                default:
                        state <= #1 `OR1200_DCFSM_IDLE;
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	1171	lampret	`// Revision 1.7 2002/03/29 15:16:55 lampret`
48			`// Some of the warnings fixed.`
49			`//`
50	788	lampret	`// Revision 1.6 2002/03/28 19:10:40 lampret`
51			`// Optimized cache controller FSM.`
52			`//`
53	775	lampret	`// Revision 1.1.1.1 2002/03/21 16:55:45 lampret`
54			`// First import of the "new" XESS XSV environment.`
55			`//`
56			`//`
57			`// Revision 1.5 2002/02/11 04:33:17 lampret`
58			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
59			`//`
60	660	lampret	`// Revision 1.4 2002/02/01 19:56:54 lampret`
61			`// Fixed combinational loops.`
62			`//`
63	636	lampret	`// Revision 1.3 2002/01/28 01:15:59 lampret`
64			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
65			`//`
66	617	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
67			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
68			`//`
69	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
70			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
71			`//`
72	504	lampret	`// Revision 1.9 2001/10/21 17:57:16 lampret`
73			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
74			`//`
75			`// Revision 1.8 2001/10/19 23:28:46 lampret`
76			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
77			`//`
78			`// Revision 1.7 2001/10/14 13:12:09 lampret`
79			`// MP3 version.`
80			`//`
81			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
82			`// no message`
83			`//`
84			`// Revision 1.2 2001/08/09 13:39:33 lampret`
85			`// Major clean-up.`
86			`//`
87			`// Revision 1.1 2001/07/20 00:46:03 lampret`
88			`// Development version of RTL. Libraries are missing.`
89			`//`
90			`//`
91
92			`// synopsys translate_off`
93			`include "timescale.v"
94			`// synopsys translate_on`
95			`include "or1200_defines.v"
96
97			`define OR1200_DCFSM_IDLE 3'd0
98	636	lampret	`define OR1200_DCFSM_CLOAD 3'd1
99	504	lampret	`define OR1200_DCFSM_LREFILL3 3'd2
100	636	lampret	`define OR1200_DCFSM_CSTORE 3'd3
101	504	lampret	`define OR1200_DCFSM_SREFILL4 3'd4
102
103			`//`
104			`// Data cache FSM for cache line of 16 bytes (4x singleword)`
105			`//`
106
107			`module or1200_dc_fsm(`
108			`// Clock and reset`
109			`clk, rst,`
110
111			`// Internal i/f to top level DC`
112	1171	lampret	`dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,`
113	504	lampret	`tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,`
114			`dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,`
115	660	lampret	`burst, tag_we, dc_addr`
116	504	lampret	`);`
117
118			`//`
119			`// I/O`
120			`//`
121			`input clk;`
122			`input rst;`
123			`input dc_en;`
124	1171	lampret	`input dcqmem_cycstb_i;`
125			`input dcqmem_ci_i;`
126			`input dcqmem_we_i;`
127			`input [3:0] dcqmem_sel_i;`
128	504	lampret	`input tagcomp_miss;`
129			`input biudata_valid;`
130			`input biudata_error;`
131			`input [31:0] start_addr;`
132			`output [31:0] saved_addr;`
133			`output [3:0] dcram_we;`
134			`output biu_read;`
135			`output biu_write;`
136			`output first_hit_ack;`
137			`output first_miss_ack;`
138			`output first_miss_err;`
139			`output burst;`
140	660	lampret	`output tag_we;`
141			`output [31:0] dc_addr;`
142	504	lampret
143			`//`
144			`// Internal wires and regs`
145			`//`
146	660	lampret	`reg [31:0] saved_addr_r;`
147	504	lampret	`reg [2:0] state;`
148			`reg [2:0] cnt;`
149			`reg hitmiss_eval;`
150			`reg store;`
151			`reg load;`
152	660	lampret	`reg cache_inhibit;`
153	636	lampret	`wire first_store_hit_ack;`
154	504	lampret
155			`//`
156			`// Generate of DCRAM write enables`
157			`//`
158	1171	lampret	`assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} \| {4{first_store_hit_ack}} & dcqmem_sel_i;`
159	660	lampret	`assign tag_we = biu_read & biudata_valid & !cache_inhibit;`
160	504	lampret
161			`//`
162			`// BIU read and write`
163			`//`
164			`assign biu_read = (hitmiss_eval & tagcomp_miss) \| (!hitmiss_eval & load);`
165			`assign biu_write = store;`
166
167	660	lampret	`assign dc_addr = (biu_read \| biu_write) & !hitmiss_eval ? saved_addr : start_addr;`
168			`assign saved_addr = saved_addr_r;`
169
170	504	lampret	`//`
171			`// Assert for cache hit first word ready`
172	636	lampret	`// Assert for store cache hit first word ready`
173	504	lampret	`// Assert for cache miss first word stored/loaded OK`
174			`// Assert for cache miss first word stored/loaded with an error`
175			`//`
176	1171	lampret	assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i \| first_store_hit_ack;
177			assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
178	660	lampret	assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) \| (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
179			assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) \| (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
180	504	lampret
181			`//`
182			`// Assert burst when doing reload of complete cache line`
183			`//`
184	660	lampret	assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
185	636	lampret	\| (state == `OR1200_DCFSM_LREFILL3)
186			`ifdef OR1200_DC_STORE_REFILL
187			\| (state == `OR1200_DCFSM_SREFILL4)
188			`endif
189			`;`
190	504	lampret
191			`//`
192			`// Main DC FSM`
193			`//`
194			`always @(posedge clk or posedge rst) begin`
195			`if (rst) begin`
196			state <= #1 `OR1200_DCFSM_IDLE;
197	660	lampret	`saved_addr_r <= #1 32'b0;`
198	504	lampret	`hitmiss_eval <= #1 1'b0;`
199			`store <= #1 1'b0;`
200			`load <= #1 1'b0;`
201			`cnt <= #1 3'b000;`
202	660	lampret	`cache_inhibit <= #1 1'b0;`
203	504	lampret	`end`
204			`else`
205			`case (state) // synopsys parallel_case`
206			`OR1200_DCFSM_IDLE :
207	1171	lampret	`if (dc_en & dcqmem_cycstb_i & dcqmem_we_i) begin // store`
208	636	lampret	state <= #1 `OR1200_DCFSM_CSTORE;
209	660	lampret	`saved_addr_r <= #1 start_addr;`
210	504	lampret	`hitmiss_eval <= #1 1'b1;`
211			`store <= #1 1'b1;`
212			`load <= #1 1'b0;`
213	660	lampret	`cache_inhibit <= #1 1'b0;`
214	504	lampret	`end`
215	1171	lampret	`else if (dc_en & dcqmem_cycstb_i) begin // load`
216	636	lampret	state <= #1 `OR1200_DCFSM_CLOAD;
217	660	lampret	`saved_addr_r <= #1 start_addr;`
218	504	lampret	`hitmiss_eval <= #1 1'b1;`
219			`store <= #1 1'b0;`
220			`load <= #1 1'b1;`
221	660	lampret	`cache_inhibit <= #1 1'b0;`
222	504	lampret	`end`
223			`else begin // idle`
224			`hitmiss_eval <= #1 1'b0;`
225			`store <= #1 1'b0;`
226			`load <= #1 1'b0;`
227	660	lampret	`cache_inhibit <= #1 1'b0;`
228	504	lampret	`end`
229	660	lampret	`OR1200_DCFSM_CLOAD: begin // load
230	1171	lampret	`if (dcqmem_cycstb_i & dcqmem_ci_i)`
231	660	lampret	`cache_inhibit <= #1 1'b1;`
232			`if (hitmiss_eval)`
233			`saved_addr_r[31:13] <= #1 start_addr[31:13];`
234	1171	lampret	`if ((hitmiss_eval & !dcqmem_cycstb_i) \|\| // load aborted (usually caused by DMMU)`
235	775	lampret	`(biudata_error) \|\| // load terminated with an error`
236	1171	lampret	`((cache_inhibit \| dcqmem_ci_i) & biudata_valid)) begin // load from cache-inhibited area`
237	504	lampret	state <= #1 `OR1200_DCFSM_IDLE;
238			`hitmiss_eval <= #1 1'b0;`
239			`load <= #1 1'b0;`
240	660	lampret	`cache_inhibit <= #1 1'b0;`
241	504	lampret	`end`
242			`else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill`
243			state <= #1 `OR1200_DCFSM_LREFILL3;
244	1171	lampret	`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;`
245	504	lampret	`hitmiss_eval <= #1 1'b0;`
246			cnt <= #1 `OR1200_DCLS-2;
247	660	lampret	`cache_inhibit <= #1 1'b0;`
248	504	lampret	`end`
249	1171	lampret	`else if (!tagcomp_miss & !dcqmem_ci_i) begin // load hit, finish immediately`
250	504	lampret	state <= #1 `OR1200_DCFSM_IDLE;
251			`hitmiss_eval <= #1 1'b0;`
252			`load <= #1 1'b0;`
253	660	lampret	`cache_inhibit <= #1 1'b0;`
254	504	lampret	`end`
255			`else // load in-progress`
256			`hitmiss_eval <= #1 1'b0;`
257	660	lampret	`end`
258	504	lampret	`OR1200_DCFSM_LREFILL3 : begin
259	775	lampret	`if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
260	1171	lampret	`cnt <= #1 cnt - 1'd1;`
261			`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;`
262	504	lampret	`end`
263			`else if (biudata_valid) begin // last load of line refill`
264			state <= #1 `OR1200_DCFSM_IDLE;
265			`load <= #1 1'b0;`
266			`end`
267			`end`
268	660	lampret	`OR1200_DCFSM_CSTORE: begin // store
269	1171	lampret	`if (dcqmem_cycstb_i & dcqmem_ci_i)`
270	660	lampret	`cache_inhibit <= #1 1'b1;`
271			`if (hitmiss_eval)`
272			`saved_addr_r[31:13] <= #1 start_addr[31:13];`
273	1171	lampret	`if ((hitmiss_eval & !dcqmem_cycstb_i) \|\| // store aborted (usually caused by DMMU)`
274	775	lampret	`(biudata_error) \|\| // store terminated with an error`
275	1171	lampret	`((cache_inhibit \| dcqmem_ci_i) & biudata_valid)) begin // store to cache-inhibited area`
276	504	lampret	state <= #1 `OR1200_DCFSM_IDLE;
277			`hitmiss_eval <= #1 1'b0;`
278			`store <= #1 1'b0;`
279	660	lampret	`cache_inhibit <= #1 1'b0;`
280	504	lampret	`end`
281	636	lampret	`ifdef OR1200_DC_STORE_REFILL
282	504	lampret	`else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill`
283			state <= #1 `OR1200_DCFSM_SREFILL4;
284			`hitmiss_eval <= #1 1'b0;`
285			`store <= #1 1'b0;`
286			`load <= #1 1'b1;`
287			cnt <= #1 `OR1200_DCLS-1;
288	660	lampret	`cache_inhibit <= #1 1'b0;`
289	504	lampret	`end`
290	636	lampret	`endif
291	504	lampret	`else if (biudata_valid) begin // store hit, finish write-through`
292			state <= #1 `OR1200_DCFSM_IDLE;
293			`hitmiss_eval <= #1 1'b0;`
294			`store <= #1 1'b0;`
295	660	lampret	`cache_inhibit <= #1 1'b0;`
296	504	lampret	`end`
297			`else // store write-through in-progress`
298			`hitmiss_eval <= #1 1'b0;`
299	660	lampret	`end`
300	636	lampret	`ifdef OR1200_DC_STORE_REFILL
301	504	lampret	`OR1200_DCFSM_SREFILL4 : begin
302	775	lampret	`if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
303	1171	lampret	`cnt <= #1 cnt - 1'd1;`
304			`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;`
305	504	lampret	`end`
306			`else if (biudata_valid) begin // last load of line refill`
307			state <= #1 `OR1200_DCFSM_IDLE;
308			`load <= #1 1'b0;`
309			`end`
310			`end`
311	636	lampret	`endif
312	504	lampret	`default:`
313			state <= #1 `OR1200_DCFSM_IDLE;
314			`endcase`
315			`end`
316
317			`endmodule`

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