URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_dc_fsm.v] - Blame information for rev 660

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_DCFSM_IDLE       3'd0
`define OR1200_DCFSM_CLOAD      3'd1
`define OR1200_DCFSM_LREFILL3   3'd2
`define OR1200_DCFSM_CSTORE     3'd3
`define OR1200_DCFSM_SREFILL4   3'd4
`define OR1200_DCFSM_ILOAD      3'd5
`define OR1200_DCFSM_ISTORE     3'd6
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module or1200_dc_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level DC
        dc_en, dcdmmu_cycstb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
        burst, tag_we, dc_addr
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           dc_en;
input                           dcdmmu_cycstb_i;
input                           dcdmmu_ci_i;
input                           dcpu_we_i;
input   [3:0]                    dcpu_sel_i;
input                           tagcomp_miss;
input                           biudata_valid;
input                           biudata_error;
input   [31:0]                   start_addr;
output  [31:0]                   saved_addr;
output  [3:0]                    dcram_we;
output                          biu_read;
output                          biu_write;
output                          first_hit_ack;
output                          first_miss_ack;
output                          first_miss_err;
output                          burst;
output                          tag_we;
output  [31:0]                   dc_addr;
 
//
// Internal wires and regs
//
reg     [31:0]                   saved_addr_r;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             hitmiss_eval;
reg                             store;
reg                             load;
reg                             cache_inhibit;
wire                            first_store_hit_ack;
 
//
// Generate of DCRAM write enables
//
assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcpu_sel_i;
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
 
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
assign biu_write = store;
 
assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
assign saved_addr = saved_addr_r;
 
//
// Assert for cache hit first word ready
// Assert for store cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcdmmu_ci_i | first_store_hit_ack;
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcdmmu_ci_i;
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
 
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
                | (state == `OR1200_DCFSM_LREFILL3)
`ifdef OR1200_DC_STORE_REFILL
                | (state == `OR1200_DCFSM_SREFILL4)
`endif
                ;
 
//
// Main DC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_DCFSM_IDLE;
                saved_addr_r <= #1 32'b0;
                hitmiss_eval <= #1 1'b0;
                store <= #1 1'b0;
                load <= #1 1'b0;
                cnt <= #1 3'b000;
                cache_inhibit <= #1 1'b0;
        end
        else
        case (state)    // synopsys parallel_case
                `OR1200_DCFSM_IDLE :
                        if (dc_en & dcdmmu_cycstb_i & dcpu_we_i) begin  // store
                                state <= #1 `OR1200_DCFSM_CSTORE;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                store <= #1 1'b1;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (dc_en & dcdmmu_cycstb_i) begin         // load
                                state <= #1 `OR1200_DCFSM_CLOAD;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                                cache_inhibit <= #1 1'b0;
                        end
                        else begin                                                      // idle
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                `OR1200_DCFSM_CLOAD: begin              // load
                        if (dcdmmu_cycstb_i & dcdmmu_ci_i)
                                cache_inhibit <= #1 1'b1;
                        if (hitmiss_eval)
                                saved_addr_r[31:13] <= #1 start_addr[31:13];
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // load aborted (usually caused by DMMU)
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // load terminated with an error
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if ((cache_inhibit | dcdmmu_ci_i) & biudata_valid) begin   // load from cache-inhibited area
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (tagcomp_miss & biudata_valid) begin    // load missed, finish current external load and refill
                                state <= #1 `OR1200_DCFSM_LREFILL3;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
                                hitmiss_eval <= #1 1'b0;
                                cnt <= #1 `OR1200_DCLS-2;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (!tagcomp_miss & !dcdmmu_ci_i) begin    // load hit, finish immediately
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else                                            // load in-progress
                                hitmiss_eval <= #1 1'b0;
                end
                `OR1200_DCFSM_LREFILL3 : begin
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (biudata_valid && (|cnt)) begin         // refill ack, more loads to come
                                cnt <= #1 cnt - 'd1;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                        end
                end
                `OR1200_DCFSM_CSTORE: begin             // store
                        if (dcdmmu_cycstb_i & dcdmmu_ci_i)
                                cache_inhibit <= #1 1'b1;
                        if (hitmiss_eval)
                                saved_addr_r[31:13] <= #1 start_addr[31:13];
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // store aborted (usually caused by DMMU)
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // store terminated with an error
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if ((cache_inhibit | dcdmmu_ci_i) & biudata_valid) begin   // store to cache-inhibited area
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
`ifdef OR1200_DC_STORE_REFILL
                        else if (tagcomp_miss & biudata_valid) begin    // store missed, finish write-through and do load refill
                                state <= #1 `OR1200_DCFSM_SREFILL4;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                                cnt <= #1 `OR1200_DCLS-1;
                                cache_inhibit <= #1 1'b0;
                        end
`endif
                        else if (biudata_valid) begin                   // store hit, finish write-through
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else                                            // store write-through in-progress
                                hitmiss_eval <= #1 1'b0;
                        end
`ifdef OR1200_DC_STORE_REFILL
                `OR1200_DCFSM_SREFILL4 : begin
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (biudata_valid && (|cnt)) begin         // refill ack, more loads to come
                                cnt <= #1 cnt - 'd1;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                        end
                end
`endif
                default:
                        state <= #1 `OR1200_DCFSM_IDLE;
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	660	lampret	`// Revision 1.4 2002/02/01 19:56:54 lampret`
48			`// Fixed combinational loops.`
49			`//`
50	636	lampret	`// Revision 1.3 2002/01/28 01:15:59 lampret`
51			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
52			`//`
53	617	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
54			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
55			`//`
56	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
57			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
58			`//`
59	504	lampret	`// Revision 1.9 2001/10/21 17:57:16 lampret`
60			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
61			`//`
62			`// Revision 1.8 2001/10/19 23:28:46 lampret`
63			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
64			`//`
65			`// Revision 1.7 2001/10/14 13:12:09 lampret`
66			`// MP3 version.`
67			`//`
68			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
69			`// no message`
70			`//`
71			`// Revision 1.2 2001/08/09 13:39:33 lampret`
72			`// Major clean-up.`
73			`//`
74			`// Revision 1.1 2001/07/20 00:46:03 lampret`
75			`// Development version of RTL. Libraries are missing.`
76			`//`
77			`//`
78
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82			`include "or1200_defines.v"
83
84			`define OR1200_DCFSM_IDLE 3'd0
85	636	lampret	`define OR1200_DCFSM_CLOAD 3'd1
86	504	lampret	`define OR1200_DCFSM_LREFILL3 3'd2
87	636	lampret	`define OR1200_DCFSM_CSTORE 3'd3
88	504	lampret	`define OR1200_DCFSM_SREFILL4 3'd4
89	636	lampret	`define OR1200_DCFSM_ILOAD 3'd5
90			`define OR1200_DCFSM_ISTORE 3'd6
91	504	lampret
92			`//`
93			`// Data cache FSM for cache line of 16 bytes (4x singleword)`
94			`//`
95
96			`module or1200_dc_fsm(`
97			`// Clock and reset`
98			`clk, rst,`
99
100			`// Internal i/f to top level DC`
101	660	lampret	`dc_en, dcdmmu_cycstb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,`
102	504	lampret	`tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,`
103			`dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,`
104	660	lampret	`burst, tag_we, dc_addr`
105	504	lampret	`);`
106
107			`//`
108			`// I/O`
109			`//`
110			`input clk;`
111			`input rst;`
112			`input dc_en;`
113	660	lampret	`input dcdmmu_cycstb_i;`
114	504	lampret	`input dcdmmu_ci_i;`
115			`input dcpu_we_i;`
116			`input [3:0] dcpu_sel_i;`
117			`input tagcomp_miss;`
118			`input biudata_valid;`
119			`input biudata_error;`
120			`input [31:0] start_addr;`
121			`output [31:0] saved_addr;`
122			`output [3:0] dcram_we;`
123			`output biu_read;`
124			`output biu_write;`
125			`output first_hit_ack;`
126			`output first_miss_ack;`
127			`output first_miss_err;`
128			`output burst;`
129	660	lampret	`output tag_we;`
130			`output [31:0] dc_addr;`
131	504	lampret
132			`//`
133			`// Internal wires and regs`
134			`//`
135	660	lampret	`reg [31:0] saved_addr_r;`
136	504	lampret	`reg [2:0] state;`
137			`reg [2:0] cnt;`
138			`reg hitmiss_eval;`
139			`reg store;`
140			`reg load;`
141	660	lampret	`reg cache_inhibit;`
142	636	lampret	`wire first_store_hit_ack;`
143	504	lampret
144			`//`
145			`// Generate of DCRAM write enables`
146			`//`
147	660	lampret	`assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} \| {4{first_store_hit_ack}} & dcpu_sel_i;`
148			`assign tag_we = biu_read & biudata_valid & !cache_inhibit;`
149	504	lampret
150			`//`
151			`// BIU read and write`
152			`//`
153			`assign biu_read = (hitmiss_eval & tagcomp_miss) \| (!hitmiss_eval & load);`
154			`assign biu_write = store;`
155
156	660	lampret	`assign dc_addr = (biu_read \| biu_write) & !hitmiss_eval ? saved_addr : start_addr;`
157			`assign saved_addr = saved_addr_r;`
158
159	504	lampret	`//`
160			`// Assert for cache hit first word ready`
161	636	lampret	`// Assert for store cache hit first word ready`
162	504	lampret	`// Assert for cache miss first word stored/loaded OK`
163			`// Assert for cache miss first word stored/loaded with an error`
164			`//`
165	660	lampret	assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcdmmu_ci_i \| first_store_hit_ack;
166			assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcdmmu_ci_i;
167			assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) \| (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
168			assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) \| (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
169	504	lampret
170			`//`
171			`// Assert burst when doing reload of complete cache line`
172			`//`
173	660	lampret	assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
174	636	lampret	\| (state == `OR1200_DCFSM_LREFILL3)
175			`ifdef OR1200_DC_STORE_REFILL
176			\| (state == `OR1200_DCFSM_SREFILL4)
177			`endif
178			`;`
179	504	lampret
180			`//`
181			`// Main DC FSM`
182			`//`
183			`always @(posedge clk or posedge rst) begin`
184			`if (rst) begin`
185			state <= #1 `OR1200_DCFSM_IDLE;
186	660	lampret	`saved_addr_r <= #1 32'b0;`
187	504	lampret	`hitmiss_eval <= #1 1'b0;`
188			`store <= #1 1'b0;`
189			`load <= #1 1'b0;`
190			`cnt <= #1 3'b000;`
191	660	lampret	`cache_inhibit <= #1 1'b0;`
192	504	lampret	`end`
193			`else`
194			`case (state) // synopsys parallel_case`
195			`OR1200_DCFSM_IDLE :
196	660	lampret	`if (dc_en & dcdmmu_cycstb_i & dcpu_we_i) begin // store`
197	636	lampret	state <= #1 `OR1200_DCFSM_CSTORE;
198	660	lampret	`saved_addr_r <= #1 start_addr;`
199	504	lampret	`hitmiss_eval <= #1 1'b1;`
200			`store <= #1 1'b1;`
201			`load <= #1 1'b0;`
202	660	lampret	`cache_inhibit <= #1 1'b0;`
203	504	lampret	`end`
204	660	lampret	`else if (dc_en & dcdmmu_cycstb_i) begin // load`
205	636	lampret	state <= #1 `OR1200_DCFSM_CLOAD;
206	660	lampret	`saved_addr_r <= #1 start_addr;`
207	504	lampret	`hitmiss_eval <= #1 1'b1;`
208			`store <= #1 1'b0;`
209			`load <= #1 1'b1;`
210	660	lampret	`cache_inhibit <= #1 1'b0;`
211	504	lampret	`end`
212			`else begin // idle`
213			state <= #1 `OR1200_DCFSM_IDLE;
214			`hitmiss_eval <= #1 1'b0;`
215			`store <= #1 1'b0;`
216			`load <= #1 1'b0;`
217	660	lampret	`cache_inhibit <= #1 1'b0;`
218	504	lampret	`end`
219	660	lampret	`OR1200_DCFSM_CLOAD: begin // load
220			`if (dcdmmu_cycstb_i & dcdmmu_ci_i)`
221			`cache_inhibit <= #1 1'b1;`
222			`if (hitmiss_eval)`
223			`saved_addr_r[31:13] <= #1 start_addr[31:13];`
224	617	lampret	`if (!dc_en)`
225	504	lampret	state <= #1 `OR1200_DCFSM_IDLE;
226	660	lampret	`else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // load aborted (usually caused by DMMU)`
227	617	lampret	state <= #1 `OR1200_DCFSM_IDLE;
228	504	lampret	`hitmiss_eval <= #1 1'b0;`
229			`load <= #1 1'b0;`
230	660	lampret	`cache_inhibit <= #1 1'b0;`
231	504	lampret	`end`
232	562	lampret	`else if (biudata_error) begin // load terminated with an error`
233			state <= #1 `OR1200_DCFSM_IDLE;
234			`hitmiss_eval <= #1 1'b0;`
235			`load <= #1 1'b0;`
236	660	lampret	`cache_inhibit <= #1 1'b0;`
237	562	lampret	`end`
238	660	lampret	`else if ((cache_inhibit \| dcdmmu_ci_i) & biudata_valid) begin // load from cache-inhibited area`
239			state <= #1 `OR1200_DCFSM_IDLE;
240			`hitmiss_eval <= #1 1'b0;`
241			`load <= #1 1'b0;`
242			`cache_inhibit <= #1 1'b0;`
243			`end`
244	504	lampret	`else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill`
245			state <= #1 `OR1200_DCFSM_LREFILL3;
246	660	lampret	`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;`
247	504	lampret	`hitmiss_eval <= #1 1'b0;`
248			cnt <= #1 `OR1200_DCLS-2;
249	660	lampret	`cache_inhibit <= #1 1'b0;`
250	504	lampret	`end`
251	660	lampret	`else if (!tagcomp_miss & !dcdmmu_ci_i) begin // load hit, finish immediately`
252	504	lampret	state <= #1 `OR1200_DCFSM_IDLE;
253			`hitmiss_eval <= #1 1'b0;`
254			`load <= #1 1'b0;`
255	660	lampret	`cache_inhibit <= #1 1'b0;`
256	504	lampret	`end`
257			`else // load in-progress`
258			`hitmiss_eval <= #1 1'b0;`
259	660	lampret	`end`
260	504	lampret	`OR1200_DCFSM_LREFILL3 : begin
261	617	lampret	`if (!dc_en)`
262			state <= #1 `OR1200_DCFSM_IDLE;
263			`else if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
264	504	lampret	`cnt <= #1 cnt - 'd1;`
265	660	lampret	`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;`
266	504	lampret	`end`
267			`else if (biudata_valid) begin // last load of line refill`
268			state <= #1 `OR1200_DCFSM_IDLE;
269			`load <= #1 1'b0;`
270			`end`
271			`end`
272	660	lampret	`OR1200_DCFSM_CSTORE: begin // store
273			`if (dcdmmu_cycstb_i & dcdmmu_ci_i)`
274			`cache_inhibit <= #1 1'b1;`
275			`if (hitmiss_eval)`
276			`saved_addr_r[31:13] <= #1 start_addr[31:13];`
277	617	lampret	`if (!dc_en)`
278	504	lampret	state <= #1 `OR1200_DCFSM_IDLE;
279	660	lampret	`else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // store aborted (usually caused by DMMU)`
280	617	lampret	state <= #1 `OR1200_DCFSM_IDLE;
281	504	lampret	`hitmiss_eval <= #1 1'b0;`
282			`store <= #1 1'b0;`
283	660	lampret	`cache_inhibit <= #1 1'b0;`
284	504	lampret	`end`
285	562	lampret	`else if (biudata_error) begin // store terminated with an error`
286			state <= #1 `OR1200_DCFSM_IDLE;
287			`hitmiss_eval <= #1 1'b0;`
288			`store <= #1 1'b0;`
289	660	lampret	`cache_inhibit <= #1 1'b0;`
290	562	lampret	`end`
291	660	lampret	`else if ((cache_inhibit \| dcdmmu_ci_i) & biudata_valid) begin // store to cache-inhibited area`
292			state <= #1 `OR1200_DCFSM_IDLE;
293			`hitmiss_eval <= #1 1'b0;`
294			`store <= #1 1'b0;`
295			`cache_inhibit <= #1 1'b0;`
296			`end`
297	636	lampret	`ifdef OR1200_DC_STORE_REFILL
298	504	lampret	`else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill`
299			state <= #1 `OR1200_DCFSM_SREFILL4;
300			`hitmiss_eval <= #1 1'b0;`
301			`store <= #1 1'b0;`
302			`load <= #1 1'b1;`
303			cnt <= #1 `OR1200_DCLS-1;
304	660	lampret	`cache_inhibit <= #1 1'b0;`
305	504	lampret	`end`
306	636	lampret	`endif
307	504	lampret	`else if (biudata_valid) begin // store hit, finish write-through`
308			state <= #1 `OR1200_DCFSM_IDLE;
309			`hitmiss_eval <= #1 1'b0;`
310			`store <= #1 1'b0;`
311	660	lampret	`cache_inhibit <= #1 1'b0;`
312	504	lampret	`end`
313			`else // store write-through in-progress`
314			`hitmiss_eval <= #1 1'b0;`
315	660	lampret	`end`
316	636	lampret	`ifdef OR1200_DC_STORE_REFILL
317	504	lampret	`OR1200_DCFSM_SREFILL4 : begin
318	617	lampret	`if (!dc_en)`
319			state <= #1 `OR1200_DCFSM_IDLE;
320			`else if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
321	504	lampret	`cnt <= #1 cnt - 'd1;`
322	660	lampret	`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;`
323	504	lampret	`end`
324			`else if (biudata_valid) begin // last load of line refill`
325			state <= #1 `OR1200_DCFSM_IDLE;
326			`load <= #1 1'b0;`
327			`end`
328			`end`
329	636	lampret	`endif
330	504	lampret	`default:`
331			state <= #1 `OR1200_DCFSM_IDLE;
332			`endcase`
333			`end`
334
335			`endmodule`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_dc_fsm.v] - Blame information for rev 660