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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instatiation of DC RAM blocks.                              ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dc_ram(
        // Reset and clock
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // Internal i/f
        addr, en, we, datain, dataout
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                           mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
output                          mbist_so_o;
`endif
 
`ifdef OR1200_NO_DC
 
//
// Data cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`else
 
//
// Instantiation of RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x32_bw dc_ram(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x32_bw dc_ram(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we),
        .oe(1'b1),
        .addr(addr),
        .di(datain),
        .do(dataout)
);
`endif
endmodule

Line No.	Rev	Author	Line
1	1063	lampret
2	504	lampret	`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// OR1200's DC RAMs ////`
5			`//// ////`
6			`//// This file is part of the OpenRISC 1200 project ////`
7			`//// http://www.opencores.org/cores/or1k/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// Instatiation of DC RAM blocks. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	1216	simons	`// Revision 1.2.4.1 2003/12/09 11:46:48 simons`
49			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
50			`//`
51	1214	simons	`// Revision 1.2 2002/10/17 20:04:40 lampret`
52			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
53			`//`
54	1063	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
55			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
56			`//`
57	504	lampret	`// Revision 1.8 2001/10/21 17:57:16 lampret`
58			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
59			`//`
60			`// Revision 1.7 2001/10/14 13:12:09 lampret`
61			`// MP3 version.`
62			`//`
63			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
64			`// no message`
65			`//`
66			`// Revision 1.2 2001/08/09 13:39:33 lampret`
67			`// Major clean-up.`
68			`//`
69			`// Revision 1.1 2001/07/20 00:46:03 lampret`
70			`// Development version of RTL. Libraries are missing.`
71			`//`
72			`//`
73
74			`// synopsys translate_off`
75			`include "timescale.v"
76			`// synopsys translate_on`
77			`include "or1200_defines.v"
78
79			`module or1200_dc_ram(`
80			`// Reset and clock`
81			`clk, rst,`
82
83	1063	lampret	`ifdef OR1200_BIST
84			`// RAM BIST`
85	1214	simons	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
86	1063	lampret	`endif
87
88	504	lampret	`// Internal i/f`
89			`addr, en, we, datain, dataout`
90			`);`
91
92			parameter dw = `OR1200_OPERAND_WIDTH;
93			parameter aw = `OR1200_DCINDX;
94
95			`//`
96			`// I/O`
97			`//`
98			`input clk;`
99			`input rst;`
100			`input [aw-1:0] addr;`
101			`input en;`
102			`input [3:0] we;`
103			`input [dw-1:0] datain;`
104			`output [dw-1:0] dataout;`
105
106	1063	lampret	`ifdef OR1200_BIST
107			`//`
108			`// RAM BIST`
109			`//`
110	1216	simons	`input mbist_si_i;`
111			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
112			`output mbist_so_o;`
113	1063	lampret	`endif
114
115	504	lampret	`ifdef OR1200_NO_DC
116
117			`//`
118			`// Data cache not implemented`
119			`//`
120			`assign dataout = {dw{1'b0}};`
121	1063	lampret	`ifdef OR1200_BIST
122	1214	simons	`assign mbist_so_o = mbist_si_i;`
123	1063	lampret	`endif
124	504	lampret
125			`else
126
127			`//`
128	1216	simons	`// Instantiation of RAM block`
129	1063	lampret	`//`
130	504	lampret	`ifdef OR1200_DC_1W_4KB
131	1216	simons	`or1200_spram_1024x32_bw dc_ram(`
132	504	lampret	`endif
133			`ifdef OR1200_DC_1W_8KB
134	1216	simons	`or1200_spram_2048x32_bw dc_ram(`
135	504	lampret	`endif
136	1063	lampret	`ifdef OR1200_BIST
137			`// RAM BIST`
138	1216	simons	`.mbist_si_i(mbist_si_i),`
139			`.mbist_so_o(mbist_so_o),`
140	1214	simons	`.mbist_ctrl_i(mbist_ctrl_i),`
141	1063	lampret	`endif
142	504	lampret	`.clk(clk),`
143			`.rst(rst),`
144			`.ce(en),`
145	1216	simons	`.we(we),`
146	504	lampret	`.oe(1'b1),`
147			`.addr(addr),`
148	1216	simons	`.di(datain),`
149			`.do(dataout)`
150	504	lampret	`);`
151			`endif
152			`endmodule`

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Blame information for rev 1765