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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  OR1200's definitions                                        ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  Parameters of the OR1200 core                               ////

////                                                              ////

////  To Do:                                                      ////

////   - add parameters that are missing                          ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.12  2002/03/28 19:25:42  lampret

// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.

//

// Revision 1.11  2002/03/28 19:13:17  lampret

// Updated defines.

//

// Revision 1.10  2002/03/14 00:30:24  lampret

// Added alternative for critical path in DU.

//

// Revision 1.9  2002/03/11 01:26:26  lampret

// Fixed async loop. Changed multiplier type for ASIC.

//

// Revision 1.8  2002/02/11 04:33:17  lampret

// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.

//

// Revision 1.7  2002/02/01 19:56:54  lampret

// Fixed combinational loops.

//

// Revision 1.6  2002/01/19 14:10:22  lampret

// Fixed OR1200_XILINX_RAM32X1D.

//

// Revision 1.5  2002/01/18 07:56:00  lampret

// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.

//

// Revision 1.4  2002/01/14 09:44:12  lampret

// Default ASIC configuration does not sample WB inputs.

//

// Revision 1.3  2002/01/08 00:51:08  lampret

// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.

//

// Revision 1.2  2002/01/03 21:23:03  lampret

// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.

//

// Revision 1.1  2002/01/03 08:16:15  lampret

// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.

//

// Revision 1.20  2001/12/04 05:02:36  lampret

// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32

//

// Revision 1.19  2001/11/27 19:46:57  lampret

// Now FPGA and ASIC target are separate.

//

// Revision 1.18  2001/11/23 21:42:31  simons

// Program counter divided to PPC and NPC.

//

// Revision 1.17  2001/11/23 08:38:51  lampret

// Changed DSR/DRR behavior and exception detection.

//

// Revision 1.16  2001/11/20 21:30:38  lampret

// Added OR1200_REGISTERED_INPUTS.

//

// Revision 1.15  2001/11/19 14:29:48  simons

// Cashes disabled.

//

// Revision 1.14  2001/11/13 10:02:21  lampret

// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)

//

// Revision 1.13  2001/11/12 01:45:40  lampret

// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.

//

// Revision 1.12  2001/11/10 03:43:57  lampret

// Fixed exceptions.

//

// Revision 1.11  2001/11/02 18:57:14  lampret

// Modified virtual silicon instantiations.

//

// Revision 1.10  2001/10/21 17:57:16  lampret

// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.

//

// Revision 1.9  2001/10/19 23:28:46  lampret

// Fixed some synthesis warnings. Configured with caches and MMUs.

//

// Revision 1.8  2001/10/14 13:12:09  lampret

// MP3 version.

//

// Revision 1.1.1.1  2001/10/06 10:18:36  igorm

// no message

//

// Revision 1.3  2001/08/17 08:01:19  lampret

// IC enable/disable.

//

// Revision 1.2  2001/08/13 03:36:20  lampret

// Added cfg regs. Moved all defines into one defines.v file. More cleanup.

//

// Revision 1.1  2001/08/09 13:39:33  lampret

// Major clean-up.

//

// Revision 1.2  2001/07/22 03:31:54  lampret

// Fixed RAM's oen bug. Cache bypass under development.

//

// Revision 1.1  2001/07/20 00:46:03  lampret

// Development version of RTL. Libraries are missing.

//

//

//

// Dump VCD

//

//`define OR1200_VCD_DUMP

//

// Generate debug messages during simulation

//

//`define OR1200_VERBOSE

//`define OR1200_ASIC

////////////////////////////////////////////////////////

//

// Typical configuration for an ASIC

//

`ifdef OR1200_ASIC

//

// Target ASIC memories

//

//`define OR1200_ARTISAN_SSP

//`define OR1200_ARTISAN_SDP

//`define OR1200_ARTISAN_STP

`define OR1200_VIRTUALSILICON_SSP

`define OR1200_VIRTUALSILICON_STP_T1

//`define OR1200_VIRTUALSILICON_STP_T2

//

// Do not implement Data cache

//

//`define OR1200_NO_DC

//

// Do not implement Insn cache

//

//`define OR1200_NO_IC

//

// Do not implement Data MMU

//

//`define OR1200_NO_DMMU

//

// Do not implement Insn MMU

//

//`define OR1200_NO_IMMU

//

// Register OR1200 WISHBONE outputs

// (at the moment correct operation

// only with registered outputs)

//

`define OR1200_REGISTERED_OUTPUTS

//

// Register OR1200 WISHBNE inputs

//

//`define OR1200_REGISTERED_INPUTS

//

// Select between ASIC optimized and generic multiplier

//

//`define OR1200_ASIC_MULTP2_32X32

`define OR1200_GENERIC_MULTP2_32X32

//

// Size/type of insn/data cache if implemented

//

// `define OR1200_IC_1W_4KB

`define OR1200_IC_1W_8KB

// `define OR1200_DC_1W_4KB

`define OR1200_DC_1W_8KB

`else

/////////////////////////////////////////////////////////

//

// Typical configuration for an FPGA

//

//

// Target FPGA memories

//

`define OR1200_XILINX_RAMB4

//`define OR1200_XILINX_RAM32X1D

//

// Do not implement Data cache

//

//`define OR1200_NO_DC

//

// Do not implement Insn cache

//

//`define OR1200_NO_IC

//

// Do not implement Data MMU

//

//`define OR1200_NO_DMMU

//

// Do not implement Insn MMU

//

//`define OR1200_NO_IMMU

//

// Register OR1200 WISHBONE outputs

// (at the moment works only with

// registered outputs)

//

`define OR1200_REGISTERED_OUTPUTS

//

// Register OR1200 WISHBONE inputs

//

//`define OR1200_REGISTERED_INPUTS

//

// Select between ASIC and generic multiplier

//

//`define OR1200_ASIC_MULTP2_32X32

`define OR1200_GENERIC_MULTP2_32X32

//

// Size/type of insn/data cache if implemented

// (consider available FPGA memory resources)

//

`define OR1200_IC_1W_4KB

//`define OR1200_IC_1W_8KB

`define OR1200_DC_1W_4KB

//`define OR1200_DC_1W_8KB

`endif

//////////////////////////////////////////////////////////

//

// Do not change below unless you know what you are doing

//

//

// Enable additional synthesis directives if using

// Synopsys synthesis tool

//

//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES

//

// Operand width / register file address width

//

// (DO NOT CHANGE)

//

`define OR1200_OPERAND_WIDTH            32

`define OR1200_REGFILE_ADDR_WIDTH       5

//

// Implement rotate in the ALU

//

//`define OR1200_IMPL_ALU_ROTATE

//

// Type of ALU compare to implement

//

//`define OR1200_IMPL_ALU_COMP1

`define OR1200_IMPL_ALU_COMP2

//

// Select between low-power (larger) multiplier or faster multiplier

//

//`define OR1200_LOWPWR_MULT

//

// Clock synchronization for RISC clk and WB divided clocks

//

// If you plan to run WB:RISC clock 1:1, you can comment these two

//

`define OR1200_CLKDIV_2_SUPPORTED

//`define OR1200_CLKDIV_4_SUPPORTED

//

// Type of register file RAM

//

// `define OR1200_RFRAM_TWOPORT

//

// Type of mem2reg aligner to implement.

//

// Once OR1200_IMPL_MEM2REG2 yielded faster

// circuit, however with today tools it will

// most probably give you slower circuit.

//

`define OR1200_IMPL_MEM2REG1

//`define OR1200_IMPL_MEM2REG2

//

// Simulate l.div and l.divu

//

// If commented, l.div/l.divu will produce undefined result. If enabled,

// div instructions will be simulated, but not synthesized ! OR1200

// does not have a hardware divider.

//

`define OR1200_SIM_ALU_DIV

`define OR1200_SIM_ALU_DIVU

//

// ALUOPs

//

`define OR1200_ALUOP_WIDTH      4

`define OR1200_ALUOP_NOP        4'd4

/* Order defined by arith insns that have two source operands both in regs

   (see binutils/include/opcode/or32.h) */

`define OR1200_ALUOP_ADD        4'd0

`define OR1200_ALUOP_ADDC       4'd1

`define OR1200_ALUOP_SUB        4'd2

`define OR1200_ALUOP_AND        4'd3

`define OR1200_ALUOP_OR         4'd4

`define OR1200_ALUOP_XOR        4'd5

`define OR1200_ALUOP_MUL        4'd6

`define OR1200_ALUOP_SHROT      4'd8

`define OR1200_ALUOP_DIV        4'd9

`define OR1200_ALUOP_DIVU       4'd10

/* Order not specifically defined. */

`define OR1200_ALUOP_IMM        4'd11

`define OR1200_ALUOP_MOVHI      4'd12

`define OR1200_ALUOP_COMP       4'd13

`define OR1200_ALUOP_MTSR       4'd14

`define OR1200_ALUOP_MFSR       4'd15

//

// MACOPs

//

`define OR1200_MACOP_WIDTH      2

`define OR1200_MACOP_NOP        2'b00

`define OR1200_MACOP_MAC        2'b01

`define OR1200_MACOP_MSB        2'b10

//

// Shift/rotate ops

//

`define OR1200_SHROTOP_WIDTH    2

`define OR1200_SHROTOP_NOP      2'd0

`define OR1200_SHROTOP_SLL      2'd0

`define OR1200_SHROTOP_SRL      2'd1

`define OR1200_SHROTOP_SRA      2'd2

`define OR1200_SHROTOP_ROR      2'd3

// Execution cycles per instruction

`define OR1200_MULTICYCLE_WIDTH 2

`define OR1200_ONE_CYCLE                2'd0

`define OR1200_TWO_CYCLES               2'd1

// Operand MUX selects

`define OR1200_SEL_WIDTH                2

`define OR1200_SEL_RF                   2'd0

`define OR1200_SEL_IMM                  2'd1

`define OR1200_SEL_EX_FORW              2'd2

`define OR1200_SEL_WB_FORW              2'd3

//

// BRANCHOPs

//

`define OR1200_BRANCHOP_WIDTH           3

`define OR1200_BRANCHOP_NOP             3'd0

`define OR1200_BRANCHOP_J               3'd1

`define OR1200_BRANCHOP_JR              3'd2

`define OR1200_BRANCHOP_BAL             3'd3

`define OR1200_BRANCHOP_BF              3'd4

`define OR1200_BRANCHOP_BNF             3'd5

`define OR1200_BRANCHOP_RFE             3'd6

//

// LSUOPs

//

// Bit 0: sign extend

// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword

// Bit 3: 0 load, 1 store

`define OR1200_LSUOP_WIDTH              4

`define OR1200_LSUOP_NOP                4'b0000

`define OR1200_LSUOP_LBZ                4'b0010

`define OR1200_LSUOP_LBS                4'b0011

`define OR1200_LSUOP_LHZ                4'b0100

`define OR1200_LSUOP_LHS                4'b0101

`define OR1200_LSUOP_LWZ                4'b0110

`define OR1200_LSUOP_LWS                4'b0111

`define OR1200_LSUOP_LD         4'b0001

`define OR1200_LSUOP_SD         4'b1000

`define OR1200_LSUOP_SB         4'b1010

`define OR1200_LSUOP_SH         4'b1100

`define OR1200_LSUOP_SW         4'b1110

// FETCHOPs

`define OR1200_FETCHOP_WIDTH            1

`define OR1200_FETCHOP_NOP              1'b0

`define OR1200_FETCHOP_LW               1'b1

//

// Register File Write-Back OPs

//

// Bit 0: register file write enable

// Bits 2-1: write-back mux selects

`define OR1200_RFWBOP_WIDTH             3

`define OR1200_RFWBOP_NOP               3'b000

`define OR1200_RFWBOP_ALU               3'b001

`define OR1200_RFWBOP_LSU               3'b011

`define OR1200_RFWBOP_SPRS              3'b101

`define OR1200_RFWBOP_LR                3'b111

// Compare instructions

`define OR1200_COP_SFEQ       3'b000

`define OR1200_COP_SFNE       3'b001

`define OR1200_COP_SFGT       3'b010

`define OR1200_COP_SFGE       3'b011

`define OR1200_COP_SFLT       3'b100

`define OR1200_COP_SFLE       3'b101

`define OR1200_COP_X          3'b111

`define OR1200_SIGNED_COMPARE 'd3

`define OR1200_COMPOP_WIDTH     4

//

// TAGs for instruction bus

//

`define OR1200_ITAG_IDLE        4'h0    // idle bus

`define OR1200_ITAG_NI          4'h1    // normal insn

`define OR1200_ITAG_BE          4'hb    // Bus error exception

`define OR1200_ITAG_PE          4'hc    // Page fault exception

`define OR1200_ITAG_TE          4'hd    // TLB miss exception

//

// TAGs for data bus

//

`define OR1200_DTAG_IDLE        4'h0    // idle bus

`define OR1200_DTAG_ND          4'h1    // normal data

`define OR1200_DTAG_AE          4'ha    // Alignment exception

`define OR1200_DTAG_BE          4'hb    // Bus error exception

`define OR1200_DTAG_PE          4'hc    // Page fault exception

`define OR1200_DTAG_TE          4'hd    // TLB miss exception

//////////////////////////////////////////////

//

// ORBIS32 ISA specifics

//

// SHROT_OP position in machine word

`define OR1200_SHROTOP_POS              7:6

// ALU instructions multicycle field in machine word

`define OR1200_ALUMCYC_POS              9:8

//

// Instruction opcode groups (basic)

//

`define OR1200_OR32_J                 6'b000000

`define OR1200_OR32_JAL               6'b000001

`define OR1200_OR32_BNF               6'b000011

`define OR1200_OR32_BF                6'b000100

`define OR1200_OR32_NOP               6'b000101

`define OR1200_OR32_MOVHI             6'b000110

`define OR1200_OR32_XSYNC             6'b001000

`define OR1200_OR32_RFE               6'b001001

/* */

`define OR1200_OR32_JR                6'b010001

`define OR1200_OR32_JALR              6'b010010

`define OR1200_OR32_MACI              6'b010011

/* */

`define OR1200_OR32_LWZ               6'b100001

`define OR1200_OR32_LBZ               6'b100011

`define OR1200_OR32_LBS               6'b100100

`define OR1200_OR32_LHZ               6'b100101

`define OR1200_OR32_LHS               6'b100110

`define OR1200_OR32_ADDI              6'b100111

`define OR1200_OR32_ADDIC             6'b101000

`define OR1200_OR32_ANDI              6'b101001

`define OR1200_OR32_ORI               6'b101010

`define OR1200_OR32_XORI              6'b101011

`define OR1200_OR32_MULI              6'b101100

`define OR1200_OR32_MFSPR             6'b101101

`define OR1200_OR32_SH_ROTI           6'b101110

`define OR1200_OR32_SFXXI             6'b101111

/* */

`define OR1200_OR32_MTSPR             6'b110000

`define OR1200_OR32_MACMSB            6'b110001

/* */

`define OR1200_OR32_SW                6'b110101

`define OR1200_OR32_SB                6'b110110

`define OR1200_OR32_SH                6'b110111

`define OR1200_OR32_ALU               6'b111000

`define OR1200_OR32_SFXX              6'b111001

/////////////////////////////////////////////////////

//

// Exceptions

//

`define OR1200_EXCEPT_WIDTH 4

`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf

`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he

`define OR1200_EXCEPT_BREAK             `OR1200_EXCEPT_WIDTH'hd

`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc

`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb

`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha

`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9

`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8

`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7

`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6

`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5

`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4

`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3

`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2

`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1

`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0

/////////////////////////////////////////////////////

//

// SPR groups

//

// Bits that define the group

`define OR1200_SPR_GROUP_BITS   15:11

// Width of the group bits

`define OR1200_SPR_GROUP_WIDTH  5

// Bits that define offset inside the group

`define OR1200_SPR_OFS_BITS 10:0

// List of groups

`define OR1200_SPR_GROUP_SYS    5'd00

`define OR1200_SPR_GROUP_DMMU   5'd01

`define OR1200_SPR_GROUP_IMMU   5'd02

`define OR1200_SPR_GROUP_DC     5'd03

`define OR1200_SPR_GROUP_IC     5'd04

`define OR1200_SPR_GROUP_MAC    5'd05

`define OR1200_SPR_GROUP_DU     5'd06

`define OR1200_SPR_GROUP_PM     5'd08

`define OR1200_SPR_GROUP_PIC    5'd09

`define OR1200_SPR_GROUP_TT     5'd10

/////////////////////////////////////////////////////

//

// System group

//

//

// System registers

//

`define OR1200_SPR_CFGR         7'd0

`define OR1200_SPR_RF           6'd32   // 1024 >> 5

`define OR1200_SPR_NPC          11'd16

`define OR1200_SPR_SR           11'd17

`define OR1200_SPR_PPC          11'd18

`define OR1200_SPR_EPCR         11'd32

`define OR1200_SPR_EEAR         11'd48

`define OR1200_SPR_ESR          11'd64

//

// SR bits

//

`define OR1200_SR_WIDTH 16

`define OR1200_SR_SM   0

`define OR1200_SR_TEE  1

`define OR1200_SR_IEE  2

`define OR1200_SR_DCE  3

`define OR1200_SR_ICE  4

`define OR1200_SR_DME  5

`define OR1200_SR_IME  6

`define OR1200_SR_LEE  7

`define OR1200_SR_CE   8

`define OR1200_SR_F    9

`define OR1200_SR_CY   10       // Unused

`define OR1200_SR_OV   11       // Unused

`define OR1200_SR_OVE  12       // Unused

`define OR1200_SR_DSX  13       // Unused

`define OR1200_SR_EPH  14

`define OR1200_SR_FO   15

`define OR1200_SR_CID  31:28    // Unimplemented

// Bits that define offset inside the group

`define OR1200_SPROFS_BITS 10:0

//

// VR, UPR and Configuration Registers

//

// Define if you want configuration registers implemented

`define OR1200_CFGR_IMPLEMENTED

// Define if you want full address decode inside SYS group

`define OR1200_SYS_FULL_DECODE

// Offsets of VR, UPR and CFGR registers

`define OR1200_SPRGRP_SYS_VR            4'h0

`define OR1200_SPRGRP_SYS_UPR           4'h1

`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2

`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3

`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4

`define OR1200_SPRGRP_SYS_DCCFGR        4'h5

`define OR1200_SPRGRP_SYS_ICCFGR        4'h6

`define OR1200_SPRGRP_SYS_DCFGR 4'h7

// VR fields

`define OR1200_VR_REV_BITS              5:0

`define OR1200_VR_RES1_BITS             15:6

`define OR1200_VR_CFG_BITS              23:16

`define OR1200_VR_VER_BITS              31:24

// VR values

`define OR1200_VR_REV                   6'h00

`define OR1200_VR_RES1                  10'h000

`define OR1200_VR_CFG                   8'h00

`define OR1200_VR_VER                   8'h12

// UPR fields

`define OR1200_UPR_UP_BITS              0

`define OR1200_UPR_DCP_BITS             1

`define OR1200_UPR_ICP_BITS             2

`define OR1200_UPR_DMP_BITS             3

`define OR1200_UPR_IMP_BITS             4

`define OR1200_UPR_MP_BITS              5

`define OR1200_UPR_DUP_BITS             6

`define OR1200_UPR_PCUP_BITS            7

`define OR1200_UPR_PMP_BITS             8

`define OR1200_UPR_PICP_BITS            9

`define OR1200_UPR_TTP_BITS             10

`define OR1200_UPR_RES1_BITS            23:11

`define OR1200_UPR_CUP_BITS             31:24

// UPR values

`define OR1200_UPR_UP                   1'b1

`define OR1200_UPR_DCP                  1'b1

`define OR1200_UPR_ICP                  1'b1

`define OR1200_UPR_DMP                  1'b1

`define OR1200_UPR_IMP                  1'b1

`define OR1200_UPR_MP                   1'b1

`define OR1200_UPR_DUP                  1'b1

`define OR1200_UPR_PCUP         1'b0

`define OR1200_UPR_PMP                  1'b1

`define OR1200_UPR_PICP         1'b1

`define OR1200_UPR_TTP                  1'b1

`define OR1200_UPR_RES1         13'h0000

`define OR1200_UPR_CUP                  8'h00

// CPUCFGR fields

`define OR1200_CPUCFGR_NSGF_BITS        3:0

`define OR1200_CPUCFGR_HGF_BITS 4

`define OR1200_CPUCFGR_OB32S_BITS       5

`define OR1200_CPUCFGR_OB64S_BITS       6

`define OR1200_CPUCFGR_OF32S_BITS       7

`define OR1200_CPUCFGR_OF64S_BITS       8

`define OR1200_CPUCFGR_OV64S_BITS       9

`define OR1200_CPUCFGR_RES1_BITS        31:10

// CPUCFGR values

`define OR1200_CPUCFGR_NSGF             4'h0

`define OR1200_CPUCFGR_HGF              1'b0

`define OR1200_CPUCFGR_OB32S            1'b1

`define OR1200_CPUCFGR_OB64S            1'b0

`define OR1200_CPUCFGR_OF32S            1'b0

`define OR1200_CPUCFGR_OF64S            1'b0

`define OR1200_CPUCFGR_OV64S            1'b0

`define OR1200_CPUCFGR_RES1             22'h000000

// DMMUCFGR fields

`define OR1200_DMMUCFGR_NTW_BITS        1:0

`define OR1200_DMMUCFGR_NTS_BITS        4:2

`define OR1200_DMMUCFGR_NAE_BITS        7:5

`define OR1200_DMMUCFGR_CRI_BITS        8

`define OR1200_DMMUCFGR_PRI_BITS        9

`define OR1200_DMMUCFGR_TEIRI_BITS      10

`define OR1200_DMMUCFGR_HTR_BITS        11

`define OR1200_DMMUCFGR_RES1_BITS       31:12

// DMMUCFGR values

`define OR1200_DMMUCFGR_NTW             2'h0

`define OR1200_DMMUCFGR_NTS             3'h5

`define OR1200_DMMUCFGR_NAE             3'h0

`define OR1200_DMMUCFGR_CRI             1'b0

`define OR1200_DMMUCFGR_PRI             1'b0

`define OR1200_DMMUCFGR_TEIRI           1'b1

`define OR1200_DMMUCFGR_HTR             1'b0

`define OR1200_DMMUCFGR_RES1            20'h00000

// IMMUCFGR fields

`define OR1200_IMMUCFGR_NTW_BITS        1:0

`define OR1200_IMMUCFGR_NTS_BITS        4:2

`define OR1200_IMMUCFGR_NAE_BITS        7:5

`define OR1200_IMMUCFGR_CRI_BITS        8

`define OR1200_IMMUCFGR_PRI_BITS        9

`define OR1200_IMMUCFGR_TEIRI_BITS      10

`define OR1200_IMMUCFGR_HTR_BITS        11

`define OR1200_IMMUCFGR_RES1_BITS       31:12

// IMMUCFGR values

`define OR1200_IMMUCFGR_NTW             2'h0

`define OR1200_IMMUCFGR_NTS             3'h5

`define OR1200_IMMUCFGR_NAE             3'h0

`define OR1200_IMMUCFGR_CRI             1'b0

`define OR1200_IMMUCFGR_PRI             1'b0

`define OR1200_IMMUCFGR_TEIRI           1'b1

`define OR1200_IMMUCFGR_HTR             1'b0

`define OR1200_IMMUCFGR_RES1            20'h00000

// DCCFGR fields

`define OR1200_DCCFGR_NCW_BITS          2:0

`define OR1200_DCCFGR_NCS_BITS          6:3

`define OR1200_DCCFGR_CBS_BITS          7

`define OR1200_DCCFGR_CWS_BITS          8

`define OR1200_DCCFGR_CCRI_BITS 9

`define OR1200_DCCFGR_CBIRI_BITS        10

`define OR1200_DCCFGR_CBPRI_BITS        11

`define OR1200_DCCFGR_CBLRI_BITS        12

`define OR1200_DCCFGR_CBFRI_BITS        13

`define OR1200_DCCFGR_CBWBRI_BITS       14

`define OR1200_DCCFGR_RES1_BITS 31:15

// DCCFGR values

`define OR1200_DCCFGR_NCW               3'h0

`define OR1200_DCCFGR_NCS               4'h5