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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Double-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common double-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  double-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.6  2002/03/28 19:25:42  lampret
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
//
// Revision 1.5  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.4  2002/01/23 07:52:36  lampret
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
//
// Revision 1.3  2002/01/19 14:10:22  lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.2  2002/01/15 06:12:22  lampret
// Fixed module name when compiling with OR1200_XILINX_RAM32X1D
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/05 14:48:00  lampret
// Added missing endif
//
// Revision 1.9  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.8  2001/10/22 19:39:56  lampret
// Fixed parameters in generic sprams.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dpram_32x32(
        // Generic synchronous double-port RAM interface
        clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
        clk_b, rst_b, ce_b, we_b, addr_b, di_b
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
 
//
// Generic synchronous double-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SDP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef UNUSED
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
`else
art_hsdp_32x32 artisan_sdp(
`endif
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(1'b1),
        .aa(addr_a),
        .da(32'h00000000),
        .oena(~oe_a),
        .qb(),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(1'b1)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_STP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
        .QA(do_a),
        .QB(),
 
        .ADRA(addr_a),
        .DA(32'h00000000),
        .WEA(1'b0),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(addr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(1'b1),
        .MEB(ce_b),
        .CLKB(clk_b)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_STP_T1
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Two-port R/W SRAM Type 1
//
`ifdef UNUSED
vs_hdtp_64x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
vs_hdtp_64x32 vs_ssp(
`endif
        .P1CK(clk_a),
        .P1CEN(~ce_a),
        .P1WEN(1'b1),
        .P1OEN(~oe_a),
        .P1ADR({1'b0, addr_a}),
        .P1DI(32'h0000_0000),
        .P1DOUT(do_a),
 
        .P2CK(clk_b),
        .P2CEN(~ce_b),
        .P2WEN(~ce_b),
        .P2OEN(1'b1),
        .P2ADR({1'b0, addr_b}),
        .P2DI(di_b),
        .P2DOUT()
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_STP_T2
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Two-port R/W SRAM Type 2
//
`ifdef UNUSED
vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
vs_hdtp_32x32 vs_ssp(
`endif
        .RCK(clk_a),
        .REN(~ce_a),
        .OEN(~oe_a),
        .RADR(addr_a),
        .DOUT(do_a),
 
        .WCK(clk_b),
        .WEN(~ce_b),
        .WADR(addr_b),
        .DI(di_b)
);
 
`else
 
`ifdef OR1200_XILINX_RAM32X1D
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
reg     [4:0]    addr_a_r;
 
always @(posedge clk_a or posedge rst_a)
        if (rst_a)
                addr_a_r <= #1 5'b00000;
        else if (ce_a)
                addr_a_r <= #1 addr_a;
 
//
// Block 0
//
or1200_xcv_ram32x8d xcv_ram32x8d_0 (
        .DPO(do_a[7:0]),
        .SPO(),
        .A(addr_b),
        .D(di_b[7:0]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 1
//
or1200_xcv_ram32x8d xcv_ram32x8d_1 (
        .DPO(do_a[15:8]),
        .SPO(),
        .A(addr_b),
        .D(di_b[15:8]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
 
//
// Block 2
//
or1200_xcv_ram32x8d xcv_ram32x8d_2 (
        .DPO(do_a[23:16]),
        .SPO(),
        .A(addr_b),
        .D(di_b[23:16]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 3
//
or1200_xcv_ram32x8d xcv_ram32x8d_3 (
        .DPO(do_a[31:24]),
        .SPO(),
        .A(addr_b),
        .D(di_b[31:24]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
`else
 
`ifdef OR1200_ALTERA_LPM_XXX
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
altqpram altqpram_component (
        .wraddress_a (addr_a),
        .inclocken_a (ce_a),
        .wraddress_b (addr_b),
        .wren_a (we_a),
        .inclocken_b (ce_b),
        .wren_b (we_b),
        .inaclr_a (rst_a),
        .inaclr_b (rst_b),
        .inclock_a (clk_a),
        .inclock_b (clk_b),
        .data_a (di_a),
        .data_b (di_b),
        .q_a (do_a),
        .q_b (do_b)
);
 
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
        altqpram_component.width_write_a = dw,
        altqpram_component.widthad_write_a = aw,
        altqpram_component.numwords_write_a = dw,
        altqpram_component.width_read_a = dw,
        altqpram_component.widthad_read_a = aw,
        altqpram_component.numwords_read_a = dw,
        altqpram_component.width_write_b = dw,
        altqpram_component.widthad_write_b = aw,
        altqpram_component.numwords_write_b = dw,
        altqpram_component.width_read_b = dw,
        altqpram_component.widthad_read_b = aw,
        altqpram_component.numwords_read_b = dw,
        altqpram_component.indata_reg_a = "INCLOCK_A",
        altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
        altqpram_component.outdata_reg_a = "INCLOCK_A",
        altqpram_component.indata_reg_b = "INCLOCK_B",
        altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
        altqpram_component.outdata_reg_b = "INCLOCK_B",
        altqpram_component.indata_aclr_a = "INACLR_A",
        altqpram_component.wraddress_aclr_a = "INACLR_A",
        altqpram_component.wrcontrol_aclr_a = "INACLR_A",
        altqpram_component.outdata_aclr_a = "INACLR_A",
        altqpram_component.indata_aclr_b = "NONE",
        altqpram_component.wraddress_aclr_b = "NONE",
        altqpram_component.wrcontrol_aclr_b = "NONE",
        altqpram_component.outdata_aclr_b = "INACLR_B",
        altqpram_component.lpm_hint = "USE_ESB=ON";
        //examplar attribute altqpram_component NOOPT TRUE
 
`else
 
//
// Generic double-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do_a = (oe_a) ? do_reg : {dw{1'b0}};
 
//
// RAM read
//
always @(posedge clk_a)
        if (ce_a)
                do_reg <= #1 mem[addr_a];
 
//
// RAM write
//
always @(posedge clk_b)
        if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16_S16
`endif  // !OR1200_XILINX_RAM32X1D
`endif  // !OR1200_VIRTUALSILICON_SSP_T1
`endif  // !OR1200_VIRTUALSILICON_SSP_T2
`endif  // !OR1200_VIRAGE_STP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SDP
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Double-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common double-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// double-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25	1129	lampret	`//// - Altera LPM ////`
26	504	lampret	`//// ////`
27			`//// To Do: ////`
28			`//// - fix Avant! ////`
29			`//// - xilinx rams need external tri-state logic ////`
30	1129	lampret	`//// - add additional RAMs ////`
31	504	lampret	`//// ////`
32			`//// Author(s): ////`
33			`//// - Damjan Lampret, lampret@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65	1171	lampret	`// Revision 1.7 2003/04/07 01:19:07 lampret`
66			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
67			`//`
68	1129	lampret	`// Revision 1.6 2002/03/28 19:25:42 lampret`
69			`// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.`
70			`//`
71	778	lampret	`// Revision 1.5 2002/02/01 19:56:54 lampret`
72			`// Fixed combinational loops.`
73			`//`
74	636	lampret	`// Revision 1.4 2002/01/23 07:52:36 lampret`
75			`// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.`
76			`//`
77	610	lampret	`// Revision 1.3 2002/01/19 14:10:22 lampret`
78			`// Fixed OR1200_XILINX_RAM32X1D.`
79			`//`
80	597	lampret	`// Revision 1.2 2002/01/15 06:12:22 lampret`
81			`// Fixed module name when compiling with OR1200_XILINX_RAM32X1D`
82			`//`
83	573	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
84			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
85			`//`
86	504	lampret	`// Revision 1.10 2001/11/05 14:48:00 lampret`
87			`// Added missing endif`
88			`//`
89			`// Revision 1.9 2001/11/02 18:57:14 lampret`
90			`// Modified virtual silicon instantiations.`
91			`//`
92			`// Revision 1.8 2001/10/22 19:39:56 lampret`
93			`// Fixed parameters in generic sprams.`
94			`//`
95			`// Revision 1.7 2001/10/21 17:57:16 lampret`
96			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
97			`//`
98			`// Revision 1.6 2001/10/14 13:12:09 lampret`
99			`// MP3 version.`
100			`//`
101			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
102			`// no message`
103			`//`
104			`// Revision 1.1 2001/08/09 13:39:33 lampret`
105			`// Major clean-up.`
106			`//`
107			`// Revision 1.2 2001/07/30 05:38:02 lampret`
108			`// Adding empty directories required by HDL coding guidelines`
109			`//`
110			`//`
111
112			`// synopsys translate_off`
113			`include "timescale.v"
114			`// synopsys translate_on`
115			`include "or1200_defines.v"
116
117			`module or1200_dpram_32x32(`
118			`// Generic synchronous double-port RAM interface`
119			`clk_a, rst_a, ce_a, oe_a, addr_a, do_a,`
120			`clk_b, rst_b, ce_b, we_b, addr_b, di_b`
121			`);`
122
123			`//`
124			`// Default address and data buses width`
125			`//`
126			`parameter aw = 5;`
127			`parameter dw = 32;`
128
129			`//`
130			`// Generic synchronous double-port RAM interface`
131			`//`
132			`input clk_a; // Clock`
133			`input rst_a; // Reset`
134			`input ce_a; // Chip enable input`
135			`input oe_a; // Output enable input`
136			`input [aw-1:0] addr_a; // address bus inputs`
137			`output [dw-1:0] do_a; // output data bus`
138			`input clk_b; // Clock`
139			`input rst_b; // Reset`
140			`input ce_b; // Chip enable input`
141			`input we_b; // Write enable input`
142			`input [aw-1:0] addr_b; // address bus inputs`
143			`input [dw-1:0] di_b; // input data bus`
144
145			`//`
146			`// Internal wires and registers`
147			`//`
148
149			`ifdef OR1200_ARTISAN_SDP
150
151			`//`
152			`// Instantiation of ASIC memory:`
153			`//`
154			`// Artisan Synchronous Double-Port RAM (ra2sh)`
155			`//`
156			`ifdef UNUSED
157			`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`
158			`else
159			`art_hsdp_32x32 artisan_sdp(`
160			`endif
161			`.qa(do_a),`
162			`.clka(clk_a),`
163			`.cena(~ce_a),`
164			`.wena(1'b1),`
165			`.aa(addr_a),`
166			`.da(32'h00000000),`
167			`.oena(~oe_a),`
168			`.qb(),`
169			`.clkb(clk_b),`
170			`.cenb(~ce_b),`
171			`.wenb(~we_b),`
172			`.ab(addr_b),`
173			`.db(di_b),`
174			`.oenb(1'b1)`
175			`);`
176
177			`else
178
179			`ifdef OR1200_AVANT_ATP
180
181			`//`
182			`// Instantiation of ASIC memory:`
183			`//`
184			`// Avant! Asynchronous Two-Port RAM`
185			`//`
186			`avant_atp avant_atp(`
187			`.web(~we),`
188			`.reb(),`
189			`.oeb(~oe),`
190			`.rcsb(),`
191			`.wcsb(),`
192			`.ra(addr),`
193			`.wa(addr),`
194			`.di(di),`
195			`.do(do)`
196			`);`
197
198			`else
199
200			`ifdef OR1200_VIRAGE_STP
201
202			`//`
203			`// Instantiation of ASIC memory:`
204			`//`
205			`// Virage Synchronous 2-port R/W RAM`
206			`//`
207			`virage_stp virage_stp(`
208			`.QA(do_a),`
209			`.QB(),`
210
211			`.ADRA(addr_a),`
212			`.DA(32'h00000000),`
213			`.WEA(1'b0),`
214			`.OEA(oe_a),`
215			`.MEA(ce_a),`
216			`.CLKA(clk_a),`
217
218			`.ADRB(addr_b),`
219			`.DB(di_b),`
220			`.WEB(we_b),`
221			`.OEB(1'b1),`
222			`.MEB(ce_b),`
223			`.CLKB(clk_b)`
224			`);`
225
226			`else
227
228	778	lampret	`ifdef OR1200_VIRTUALSILICON_STP_T1
229	504	lampret
230			`//`
231			`// Instantiation of ASIC memory:`
232			`//`
233	778	lampret	`// Virtual Silicon Two-port R/W SRAM Type 1`
234	504	lampret	`//`
235			`ifdef UNUSED
236	636	lampret	`vs_hdtp_64x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
237	504	lampret	`else
238	636	lampret	`vs_hdtp_64x32 vs_ssp(`
239	504	lampret	`endif
240	636	lampret	`.P1CK(clk_a),`
241			`.P1CEN(~ce_a),`
242			`.P1WEN(1'b1),`
243			`.P1OEN(~oe_a),`
244			`.P1ADR({1'b0, addr_a}),`
245			`.P1DI(32'h0000_0000),`
246			`.P1DOUT(do_a),`
247
248			`.P2CK(clk_b),`
249			`.P2CEN(~ce_b),`
250			`.P2WEN(~ce_b),`
251			`.P2OEN(1'b1),`
252			`.P2ADR({1'b0, addr_b}),`
253			`.P2DI(di_b),`
254			`.P2DOUT()`
255	504	lampret	`);`
256
257			`else
258
259	778	lampret	`ifdef OR1200_VIRTUALSILICON_STP_T2
260
261			`//`
262			`// Instantiation of ASIC memory:`
263			`//`
264			`// Virtual Silicon Two-port R/W SRAM Type 2`
265			`//`
266			`ifdef UNUSED
267			`vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
268			`else
269			`vs_hdtp_32x32 vs_ssp(`
270			`endif
271			`.RCK(clk_a),`
272			`.REN(~ce_a),`
273			`.OEN(~oe_a),`
274			`.RADR(addr_a),`
275			`.DOUT(do_a),`
276
277			`.WCK(clk_b),`
278			`.WEN(~ce_b),`
279			`.WADR(addr_b),`
280			`.DI(di_b)`
281			`);`
282
283			`else
284
285	504	lampret	`ifdef OR1200_XILINX_RAM32X1D
286
287			`//`
288			`// Instantiation of FPGA memory:`
289			`//`
290			`// Virtex/Spartan2`
291			`//`
292
293	597	lampret	`reg [4:0] addr_a_r;`
294
295			`always @(posedge clk_a or posedge rst_a)`
296	610	lampret	`if (rst_a)`
297			`addr_a_r <= #1 5'b00000;`
298			`else if (ce_a)`
299	597	lampret	`addr_a_r <= #1 addr_a;`
300
301	504	lampret	`//`
302			`// Block 0`
303			`//`
304	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_0 (`
305	504	lampret	`.DPO(do_a[7:0]),`
306			`.SPO(),`
307			`.A(addr_b),`
308			`.D(di_b[7:0]),`
309	597	lampret	`.DPRA(addr_a_r),`
310	504	lampret	`.WCLK(clk_b),`
311			`.WE(we_b)`
312			`);`
313
314			`//`
315			`// Block 1`
316			`//`
317	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_1 (`
318	504	lampret	`.DPO(do_a[15:8]),`
319			`.SPO(),`
320			`.A(addr_b),`
321			`.D(di_b[15:8]),`
322	597	lampret	`.DPRA(addr_a_r),`
323	504	lampret	`.WCLK(clk_b),`
324			`.WE(we_b)`
325			`);`
326
327
328			`//`
329			`// Block 2`
330			`//`
331	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_2 (`
332	504	lampret	`.DPO(do_a[23:16]),`
333			`.SPO(),`
334			`.A(addr_b),`
335			`.D(di_b[23:16]),`
336	597	lampret	`.DPRA(addr_a_r),`
337	504	lampret	`.WCLK(clk_b),`
338			`.WE(we_b)`
339			`);`
340
341			`//`
342			`// Block 3`
343			`//`
344	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_3 (`
345	504	lampret	`.DPO(do_a[31:24]),`
346			`.SPO(),`
347			`.A(addr_b),`
348			`.D(di_b[31:24]),`
349	597	lampret	`.DPRA(addr_a_r),`
350	504	lampret	`.WCLK(clk_b),`
351			`.WE(we_b)`
352			`);`
353
354			`else
355
356			`ifdef OR1200_XILINX_RAMB4
357
358			`//`
359			`// Instantiation of FPGA memory:`
360			`//`
361			`// Virtex/Spartan2`
362			`//`
363
364			`//`
365			`// Block 0`
366			`//`
367			`RAMB4_S16_S16 ramb4_s16_0(`
368			`.CLKA(clk_a),`
369			`.RSTA(rst_a),`
370			`.ADDRA({3'b000, addr_a}),`
371			`.DIA(16'h0000),`
372			`.ENA(ce_a),`
373			`.WEA(1'b0),`
374			`.DOA(do_a[15:0]),`
375
376			`.CLKB(clk_b),`
377			`.RSTB(rst_b),`
378			`.ADDRB({3'b000, addr_b}),`
379			`.DIB(di_b[15:0]),`
380			`.ENB(ce_b),`
381			`.WEB(we_b),`
382			`.DOB()`
383			`);`
384
385			`//`
386			`// Block 1`
387			`//`
388			`RAMB4_S16_S16 ramb4_s16_1(`
389			`.CLKA(clk_a),`
390			`.RSTA(rst_a),`
391			`.ADDRA({3'b000, addr_a}),`
392			`.DIA(16'h0000),`
393			`.ENA(ce_a),`
394			`.WEA(1'b0),`
395			`.DOA(do_a[31:16]),`
396
397			`.CLKB(clk_b),`
398			`.RSTB(rst_b),`
399			`.ADDRB({3'b000, addr_b}),`
400			`.DIB(di_b[31:16]),`
401			`.ENB(ce_b),`
402			`.WEB(we_b),`
403			`.DOB()`
404			`);`
405
406			`else
407
408	1171	lampret	`ifdef OR1200_ALTERA_LPM_XXX
409	1129	lampret
410	504	lampret	`//`
411	1129	lampret	`// Instantiation of FPGA memory:`
412			`//`
413			`// Altera LPM`
414			`//`
415			`// Added By Jamil Khatib`
416			`//`
417			`altqpram altqpram_component (`
418			`.wraddress_a (addr_a),`
419			`.inclocken_a (ce_a),`
420			`.wraddress_b (addr_b),`
421			`.wren_a (we_a),`
422			`.inclocken_b (ce_b),`
423			`.wren_b (we_b),`
424			`.inaclr_a (rst_a),`
425			`.inaclr_b (rst_b),`
426			`.inclock_a (clk_a),`
427			`.inclock_b (clk_b),`
428			`.data_a (di_a),`
429			`.data_b (di_b),`
430			`.q_a (do_a),`
431			`.q_b (do_b)`
432			`);`
433
434			`defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",`
435			`altqpram_component.width_write_a = dw,`
436			`altqpram_component.widthad_write_a = aw,`
437			`altqpram_component.numwords_write_a = dw,`
438			`altqpram_component.width_read_a = dw,`
439			`altqpram_component.widthad_read_a = aw,`
440			`altqpram_component.numwords_read_a = dw,`
441			`altqpram_component.width_write_b = dw,`
442			`altqpram_component.widthad_write_b = aw,`
443			`altqpram_component.numwords_write_b = dw,`
444			`altqpram_component.width_read_b = dw,`
445			`altqpram_component.widthad_read_b = aw,`
446			`altqpram_component.numwords_read_b = dw,`
447			`altqpram_component.indata_reg_a = "INCLOCK_A",`
448			`altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",`
449			`altqpram_component.outdata_reg_a = "INCLOCK_A",`
450			`altqpram_component.indata_reg_b = "INCLOCK_B",`
451			`altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",`
452			`altqpram_component.outdata_reg_b = "INCLOCK_B",`
453			`altqpram_component.indata_aclr_a = "INACLR_A",`
454			`altqpram_component.wraddress_aclr_a = "INACLR_A",`
455			`altqpram_component.wrcontrol_aclr_a = "INACLR_A",`
456			`altqpram_component.outdata_aclr_a = "INACLR_A",`
457			`altqpram_component.indata_aclr_b = "NONE",`
458			`altqpram_component.wraddress_aclr_b = "NONE",`
459			`altqpram_component.wrcontrol_aclr_b = "NONE",`
460			`altqpram_component.outdata_aclr_b = "INACLR_B",`
461			`altqpram_component.lpm_hint = "USE_ESB=ON";`
462			`//examplar attribute altqpram_component NOOPT TRUE`
463
464			`else
465
466			`//`
467	504	lampret	`// Generic double-port synchronous RAM model`
468			`//`
469
470			`//`
471			`// Generic RAM's registers and wires`
472			`//`
473			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
474			`reg [dw-1:0] do_reg; // RAM data output register`
475
476			`//`
477			`// Data output drivers`
478			`//`
479	1129	lampret	`assign do_a = (oe_a) ? do_reg : {dw{1'b0}};`
480	504	lampret
481			`//`
482			`// RAM read`
483			`//`
484			`always @(posedge clk_a)`
485			`if (ce_a)`
486			`do_reg <= #1 mem[addr_a];`
487
488			`//`
489			`// RAM write`
490			`//`
491			`always @(posedge clk_b)`
492			`if (ce_b && we_b)`
493			`mem[addr_b] <= #1 di_b;`
494
495	1129	lampret	`endif // !OR1200_ALTERA_LPM
496	504	lampret	`endif // !OR1200_XILINX_RAMB4_S16_S16
497			`endif // !OR1200_XILINX_RAM32X1D
498	778	lampret	`endif // !OR1200_VIRTUALSILICON_SSP_T1
499			`endif // !OR1200_VIRTUALSILICON_SSP_T2
500	504	lampret	`endif // !OR1200_VIRAGE_STP

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