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1 504 lampret 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's Debug Unit                                         ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://www.opencores.org/cores/or1k/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Basic OR1200 debug unit.                                    ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - make it smaller and faster                               ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
// CVS Revision History
45 
//
46 
// $Log: not supported by cvs2svn $
47 1252 lampret 
// Revision 1.9.4.3  2004/01/18 10:08:00  simons
48 
// Error fixed.
49 
//
50 1235 simons 
// Revision 1.9.4.2  2004/01/17 21:14:14  simons
51 
// Errors fixed.
52 
//
53 1233 simons 
// Revision 1.9.4.1  2004/01/15 06:46:38  markom
54 
// interface to debug changed; no more opselect; stb-ack protocol
55 
//
56 1226 markom 
// Revision 1.9  2003/01/22 03:23:47  lampret
57 
// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
58 
//
59 1112 lampret 
// Revision 1.8  2002/09/08 19:31:52  lampret
60 
// Fixed a typo, reported by Taylor Su.
61 
//
62 1038 lampret 
// Revision 1.7  2002/07/14 22:17:17  lampret
63 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
64 
//
65 895 lampret 
// Revision 1.6  2002/03/14 00:30:24  lampret
66 
// Added alternative for critical path in DU.
67 
//
68 737 lampret 
// Revision 1.5  2002/02/11 04:33:17  lampret
69 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
70 
//
71 660 lampret 
// Revision 1.4  2002/01/28 01:16:00  lampret
72 
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
73 
//
74 617 lampret 
// Revision 1.3  2002/01/18 07:56:00  lampret
75 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
76 
//
77 589 lampret 
// Revision 1.2  2002/01/14 06:18:22  lampret
78 
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
79 
//
80 562 lampret 
// Revision 1.1  2002/01/03 08:16:15  lampret
81 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
82 
//
83 504 lampret 
// Revision 1.12  2001/11/30 18:58:00  simons
84 
// Trap insn couses break after exits ex_insn.
85 
//
86 
// Revision 1.11  2001/11/23 08:38:51  lampret
87 
// Changed DSR/DRR behavior and exception detection.
88 
//
89 
// Revision 1.10  2001/11/20 21:25:44  lampret
90 
// Fixed dbg_is_o assignment width.
91 
//
92 
// Revision 1.9  2001/11/20 18:46:14  simons
93 
// Break point bug fixed
94 
//
95 
// Revision 1.8  2001/11/18 08:36:28  lampret
96 
// For GDB changed single stepping and disabled trap exception.
97 
//
98 
// Revision 1.7  2001/10/21 18:09:53  lampret
99 
// Fixed sensitivity list.
100 
//
101 
// Revision 1.6  2001/10/14 13:12:09  lampret
102 
// MP3 version.
103 
//
104 
//
105 
 
106 
// synopsys translate_off
107 
`include "timescale.v"
108 
// synopsys translate_on
109 
`include "or1200_defines.v"
110 
 
111 
//
112 
// Debug unit
113 
//
114 
 
115 
module or1200_du(
116 
        // RISC Internal Interface
117 
        clk, rst,
118 1252 lampret 
        dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
119 
        dcpu_dat_dc, icpu_cycstb_i,
120 
        ex_freeze, branch_op, ex_insn, id_pc,
121 895 lampret 
        spr_dat_npc, rf_dataw,
122 
        du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
123 1252 lampret 
        du_read, du_write, du_except, du_hwbkpt,
124 504 lampret 
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
125 
 
126 
        // External Debug Interface
127 1226 markom 
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
128 1235 simons 
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
129 504 lampret 
);
130 
 
131 
parameter dw = `OR1200_OPERAND_WIDTH;
132 
parameter aw = `OR1200_OPERAND_WIDTH;
133 
 
134 
//
135 
// I/O
136 
//
137 
 
138 
//
139 
// RISC Internal Interface
140 
//
141 
input                           clk;            // Clock
142 
input                           rst;            // Reset
143 660 lampret 
input                           dcpu_cycstb_i;  // LSU status
144 504 lampret 
input                           dcpu_we_i;      // LSU status
145 1252 lampret 
input   [31:0]                   dcpu_adr_i;     // LSU addr
146 
input   [31:0]                   dcpu_dat_lsu;   // LSU store data
147 
input   [31:0]                   dcpu_dat_dc;    // LSU load data
148 660 lampret 
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cycstb_i;  // IFETCH unit status
149 504 lampret 
input                           ex_freeze;      // EX stage freeze
150 
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
151 
input   [dw-1:0]         ex_insn;        // EX insn
152 1252 lampret 
input   [31:0]                   id_pc;          // insn fetch EA
153 895 lampret 
input   [31:0]                   spr_dat_npc;    // Next PC (for trace)
154 
input   [31:0]                   rf_dataw;       // ALU result (for trace)
155 504 lampret 
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
156 
output                          du_stall;       // Debug Unit Stall
157 
output  [aw-1:0]         du_addr;        // Debug Unit Address
158 
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
159 
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
160 
output                          du_read;        // Debug Unit Read Enable
161 
output                          du_write;       // Debug Unit Write Enable
162 
input   [12:0]                   du_except;      // Exception masked by DSR
163 1252 lampret 
output                          du_hwbkpt;      // Cause trap exception (HW Breakpoints)
164 504 lampret 
input                           spr_cs;         // SPR Chip Select
165 
input                           spr_write;      // SPR Read/Write
166 
input   [aw-1:0]         spr_addr;       // SPR Address
167 
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
168 
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
169 
 
170 
//
171 
// External Debug Interface
172 
//
173 1226 markom 
input                   dbg_stall_i;    // External Stall Input
174 
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
175 
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
176 
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
177 
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
178 
output                  dbg_bp_o;       // Breakpoint Output
179 
input                   dbg_stb_i;      // External Address/Data Strobe
180 
input                   dbg_we_i;       // External Write Enable
181 
input   [aw-1:0] dbg_adr_i;      // External Address Input
182 
input   [dw-1:0] dbg_dat_i;      // External Data Input
183 
output  [dw-1:0] dbg_dat_o;      // External Data Output
184 1233 simons 
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
185 504 lampret 
 
186 
 
187 
//
188 
// Some connections go directly from the CPU through DU to Debug I/F
189 
//
190 737 lampret 
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
191 
assign dbg_lss_o = 4'b0000;
192 895 lampret 
 
193 
reg     [1:0]                    dbg_is_o;
194 
//
195 
// Show insn activity (temp, must be removed)
196 
//
197 
always @(posedge clk or posedge rst)
198 
        if (rst)
199 
                dbg_is_o <= #1 2'b00;
200 
        else if (!ex_freeze &
201 
                ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
202 
                dbg_is_o <= #1 ~dbg_is_o;
203 
`ifdef UNUSED
204 737 lampret 
assign dbg_is_o = 2'b00;
205 895 lampret 
`endif
206 737 lampret 
`else
207 660 lampret 
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
208 
assign dbg_is_o = {1'b0, icpu_cycstb_i};
209 737 lampret 
`endif
210 504 lampret 
assign dbg_wp_o = 11'b000_0000_0000;
211 
assign dbg_dat_o = du_dat_i;
212 
 
213 
//
214 
// Some connections go directly from Debug I/F through DU to the CPU
215 
//
216 
assign du_stall = dbg_stall_i;
217 
assign du_addr = dbg_adr_i;
218 
assign du_dat_o = dbg_dat_i;
219 1226 markom 
assign du_read = dbg_stb_i && !dbg_we_i;
220 
assign du_write = dbg_stb_i && dbg_we_i;
221 504 lampret 
 
222 1226 markom 
//
223 
// Generate acknowledge -- just delay stb signal
224 
//
225 
reg dbg_ack_o;
226 
always @(posedge clk or posedge rst)
227 
        if (rst)
228 
                dbg_ack_o <= #1 1'b0;
229 
        else
230 
                dbg_ack_o <= #1 dbg_stb_i;
231 
 
232 504 lampret 
`ifdef OR1200_DU_IMPLEMENTED
233 
 
234 
//
235 1252 lampret 
// Debug Mode Register 1
236 504 lampret 
//
237 
`ifdef OR1200_DU_DMR1
238 1252 lampret 
reg     [24:0]                   dmr1;           // DMR1 implemented
239 504 lampret 
`else
240 1252 lampret 
wire    [24:0]                   dmr1;           // DMR1 not implemented
241 504 lampret 
`endif
242 
 
243 
//
244 1252 lampret 
// Debug Mode Register 2
245 504 lampret 
//
246 
`ifdef OR1200_DU_DMR2
247 1252 lampret 
reg     [23:0]                   dmr2;           // DMR2 implemented
248 
`else
249 
wire    [23:0]                   dmr2;           // DMR2 not implemented
250 504 lampret 
`endif
251 
 
252 
//
253 
// Debug Stop Register
254 
//
255 
`ifdef OR1200_DU_DSR
256 
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
257 
`else
258 
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
259 
`endif
260 
 
261 
//
262 
// Debug Reason Register
263 
//
264 
`ifdef OR1200_DU_DRR
265 
reg     [13:0]                   drr;            // DRR implemented
266 
`else
267 
wire    [13:0]                   drr;            // DRR not implemented
268 
`endif
269 
 
270 
//
271 1252 lampret 
// Debug Value Register N
272 
//
273 
`ifdef OR1200_DU_DVR0
274 
reg     [31:0]                   dvr0;
275 
`else
276 
wire    [31:0]                   dvr0;
277 
`endif
278 
 
279 
//
280 
// Debug Value Register N
281 
//
282 
`ifdef OR1200_DU_DVR1
283 
reg     [31:0]                   dvr1;
284 
`else
285 
wire    [31:0]                   dvr1;
286 
`endif
287 
 
288 
//
289 
// Debug Value Register N
290 
//
291 
`ifdef OR1200_DU_DVR2
292 
reg     [31:0]                   dvr2;
293 
`else
294 
wire    [31:0]                   dvr2;
295 
`endif
296 
 
297 
//
298 
// Debug Value Register N
299 
//
300 
`ifdef OR1200_DU_DVR3
301 
reg     [31:0]                   dvr3;
302 
`else
303 
wire    [31:0]                   dvr3;
304 
`endif
305 
 
306 
//
307 
// Debug Value Register N
308 
//
309 
`ifdef OR1200_DU_DVR4
310 
reg     [31:0]                   dvr4;
311 
`else
312 
wire    [31:0]                   dvr4;
313 
`endif
314 
 
315 
//
316 
// Debug Value Register N
317 
//
318 
`ifdef OR1200_DU_DVR5
319 
reg     [31:0]                   dvr5;
320 
`else
321 
wire    [31:0]                   dvr5;
322 
`endif
323 
 
324 
//
325 
// Debug Value Register N
326 
//
327 
`ifdef OR1200_DU_DVR6
328 
reg     [31:0]                   dvr6;
329 
`else
330 
wire    [31:0]                   dvr6;
331 
`endif
332 
 
333 
//
334 
// Debug Value Register N
335 
//
336 
`ifdef OR1200_DU_DVR7
337 
reg     [31:0]                   dvr7;
338 
`else
339 
wire    [31:0]                   dvr7;
340 
`endif
341 
 
342 
//
343 
// Debug Control Register N
344 
//
345 
`ifdef OR1200_DU_DCR0
346 
reg     [7:0]                    dcr0;
347 
`else
348 
wire    [7:0]                    dcr0;
349 
`endif
350 
 
351 
//
352 
// Debug Control Register N
353 
//
354 
`ifdef OR1200_DU_DCR1
355 
reg     [7:0]                    dcr1;
356 
`else
357 
wire    [7:0]                    dcr1;
358 
`endif
359 
 
360 
//
361 
// Debug Control Register N
362 
//
363 
`ifdef OR1200_DU_DCR2
364 
reg     [7:0]                    dcr2;
365 
`else
366 
wire    [7:0]                    dcr2;
367 
`endif
368 
 
369 
//
370 
// Debug Control Register N
371 
//
372 
`ifdef OR1200_DU_DCR3
373 
reg     [7:0]                    dcr3;
374 
`else
375 
wire    [7:0]                    dcr3;
376 
`endif
377 
 
378 
//
379 
// Debug Control Register N
380 
//
381 
`ifdef OR1200_DU_DCR4
382 
reg     [7:0]                    dcr4;
383 
`else
384 
wire    [7:0]                    dcr4;
385 
`endif
386 
 
387 
//
388 
// Debug Control Register N
389 
//
390 
`ifdef OR1200_DU_DCR5
391 
reg     [7:0]                    dcr5;
392 
`else
393 
wire    [7:0]                    dcr5;
394 
`endif
395 
 
396 
//
397 
// Debug Control Register N
398 
//
399 
`ifdef OR1200_DU_DCR6
400 
reg     [7:0]                    dcr6;
401 
`else
402 
wire    [7:0]                    dcr6;
403 
`endif
404 
 
405 
//
406 
// Debug Control Register N
407 
//
408 
`ifdef OR1200_DU_DCR7
409 
reg     [7:0]                    dcr7;
410 
`else
411 
wire    [7:0]                    dcr7;
412 
`endif
413 
 
414 
//
415 
// Debug Watchpoint Counter Register 0
416 
//
417 
`ifdef OR1200_DU_DWCR0
418 
reg     [31:0]                   dwcr0;
419 
`else
420 
wire    [31:0]                   dwcr0;
421 
`endif
422 
 
423 
//
424 
// Debug Watchpoint Counter Register 1
425 
//
426 
`ifdef OR1200_DU_DWCR1
427 
reg     [31:0]                   dwcr1;
428 
`else
429 
wire    [31:0]                   dwcr1;
430 
`endif
431 
 
432 
//
433 504 lampret 
// Internal wires
434 
//
435 
wire                            dmr1_sel;       // DMR1 select
436 1252 lampret 
wire                            dmr2_sel;       // DMR2 select
437 504 lampret 
wire                            dsr_sel;        // DSR select
438 
wire                            drr_sel;        // DRR select
439 1252 lampret 
wire                            dvr0_sel,
440 
                                dvr1_sel,
441 
                                dvr2_sel,
442 
                                dvr3_sel,
443 
                                dvr4_sel,
444 
                                dvr5_sel,
445 
                                dvr6_sel,
446 
                                dvr7_sel;       // DVR selects
447 
wire                            dcr0_sel,
448 
                                dcr1_sel,
449 
                                dcr2_sel,
450 
                                dcr3_sel,
451 
                                dcr4_sel,
452 
                                dcr5_sel,
453 
                                dcr6_sel,
454 
                                dcr7_sel;       // DCR selects
455 
wire                            dwcr0_sel,
456 
                                dwcr1_sel;      // DWCR selects
457 504 lampret 
reg                             dbg_bp_r;
458 1252 lampret 
`ifdef OR1200_DU_HWBKPTS
459 
reg     [31:0]                   match_cond0_ct;
460 
reg     [31:0]                   match_cond1_ct;
461 
reg     [31:0]                   match_cond2_ct;
462 
reg     [31:0]                   match_cond3_ct;
463 
reg     [31:0]                   match_cond4_ct;
464 
reg     [31:0]                   match_cond5_ct;
465 
reg     [31:0]                   match_cond6_ct;
466 
reg     [31:0]                   match_cond7_ct;
467 
reg                             match_cond0_stb;
468 
reg                             match_cond1_stb;
469 
reg                             match_cond2_stb;
470 
reg                             match_cond3_stb;
471 
reg                             match_cond4_stb;
472 
reg                             match_cond5_stb;
473 
reg                             match_cond6_stb;
474 
reg                             match_cond7_stb;
475 
reg                             match0;
476 
reg                             match1;
477 
reg                             match2;
478 
reg                             match3;
479 
reg                             match4;
480 
reg                             match5;
481 
reg                             match6;
482 
reg                             match7;
483 
reg                             wpcntr0_match;
484 
reg                             wpcntr1_match;
485 
reg                             incr_wpcntr0;
486 
reg                             incr_wpcntr1;
487 
reg     [10:0]                   wp;
488 
`endif
489 
wire                            du_hwbkpt;
490 504 lampret 
`ifdef OR1200_DU_READREGS
491 
reg     [31:0]                   spr_dat_o;
492 
`endif
493 
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
494 895 lampret 
`ifdef OR1200_DU_TB_IMPLEMENTED
495 
wire                            tb_enw;
496 
reg     [7:0]                    tb_wadr;
497 
reg [31:0]                       tb_timstmp;
498 
`endif
499 
wire    [31:0]                   tbia_dat_o;
500 
wire    [31:0]                   tbim_dat_o;
501 
wire    [31:0]                   tbar_dat_o;
502 
wire    [31:0]                   tbts_dat_o;
503 504 lampret 
 
504 
//
505 
// DU registers address decoder
506 
//
507 
`ifdef OR1200_DU_DMR1
508 1252 lampret 
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
509 504 lampret 
`endif
510 1252 lampret 
`ifdef OR1200_DU_DMR2
511 
assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
512 
`endif
513 504 lampret 
`ifdef OR1200_DU_DSR
514 1252 lampret 
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
515 504 lampret 
`endif
516 
`ifdef OR1200_DU_DRR
517 1252 lampret 
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
518 504 lampret 
`endif
519 1252 lampret 
`ifdef OR1200_DU_DVR0
520 
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
521 
`endif
522 
`ifdef OR1200_DU_DVR1
523 
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
524 
`endif
525 
`ifdef OR1200_DU_DVR2
526 
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
527 
`endif
528 
`ifdef OR1200_DU_DVR3
529 
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
530 
`endif
531 
`ifdef OR1200_DU_DVR4
532 
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
533 
`endif
534 
`ifdef OR1200_DU_DVR5
535 
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
536 
`endif
537 
`ifdef OR1200_DU_DVR6
538 
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
539 
`endif
540 
`ifdef OR1200_DU_DVR7
541 
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
542 
`endif
543 
`ifdef OR1200_DU_DCR0
544 
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
545 
`endif
546 
`ifdef OR1200_DU_DCR1
547 
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
548 
`endif
549 
`ifdef OR1200_DU_DCR2
550 
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
551 
`endif
552 
`ifdef OR1200_DU_DCR3
553 
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
554 
`endif
555 
`ifdef OR1200_DU_DCR4
556 
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
557 
`endif
558 
`ifdef OR1200_DU_DCR5
559 
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
560 
`endif
561 
`ifdef OR1200_DU_DCR6
562 
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
563 
`endif
564 
`ifdef OR1200_DU_DCR7
565 
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
566 
`endif
567 
`ifdef OR1200_DU_DWCR0
568 
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
569 
`endif
570 
`ifdef OR1200_DU_DWCR1
571 
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
572 
`endif
573 504 lampret 
 
574 
//
575 
// Decode started exception
576 
//
577 
always @(du_except) begin
578 
        except_stop = 14'b0000_0000_0000;
579 
        casex (du_except)
580 617 lampret 
                13'b1_xxxx_xxxx_xxxx:
581 
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
582 
                13'b0_1xxx_xxxx_xxxx: begin
583 589 lampret 
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
584 504 lampret 
                end
585 617 lampret 
                13'b0_01xx_xxxx_xxxx: begin
586 504 lampret 
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
587 
                end
588 617 lampret 
                13'b0_001x_xxxx_xxxx:
589 504 lampret 
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
590 617 lampret 
                13'b0_0001_xxxx_xxxx: begin
591 504 lampret 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
592 
                end
593 617 lampret 
                13'b0_0000_1xxx_xxxx:
594 504 lampret 
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
595 617 lampret 
                13'b0_0000_01xx_xxxx: begin
596 504 lampret 
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
597 
                end
598 617 lampret 
                13'b0_0000_001x_xxxx: begin
599 504 lampret 
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
600 
                end
601 617 lampret 
                13'b0_0000_0001_xxxx:
602 504 lampret 
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
603 617 lampret 
                13'b0_0000_0000_1xxx:
604 504 lampret 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
605 
                13'b0_0000_0000_01xx: begin
606 
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
607 
                end
608 
                13'b0_0000_0000_001x: begin
609 
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
610 
                end
611 
                13'b0_0000_0000_0001:
612 
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
613 
                default:
614 
                        except_stop = 14'b0000_0000_0000;
615 
        endcase
616 
end
617 
 
618 
//
619 
// dbg_bp_o is registered
620 
//
621 
assign dbg_bp_o = dbg_bp_r;
622 
 
623 
//
624 
// Breakpoint activation register
625 
//
626 
always @(posedge clk or posedge rst)
627 
        if (rst)
628 
                dbg_bp_r <= #1 1'b0;
629 
        else if (!ex_freeze)
630 
                dbg_bp_r <= #1 |except_stop
631 
`ifdef OR1200_DU_DMR1_ST
632 617 lampret 
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
633 504 lampret 
`endif
634 
`ifdef OR1200_DU_DMR1_BT
635 
                        | (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
636 
`endif
637 
                        ;
638 
        else
639 562 lampret 
                dbg_bp_r <= #1 |except_stop;
640 504 lampret 
 
641 
//
642 
// Write to DMR1
643 
//
644 
`ifdef OR1200_DU_DMR1
645 
always @(posedge clk or posedge rst)
646 
        if (rst)
647 1252 lampret 
                dmr1 <= 25'h000_0000;
648 504 lampret 
        else if (dmr1_sel && spr_write)
649 1252 lampret 
`ifdef OR1200_DU_HWBKPTS
650 
                dmr1 <= #1 spr_dat_i[24:0];
651 504 lampret 
`else
652 1252 lampret 
                dmr1 <= #1 {1'b0, spr_dat_i[23:22], 22'h00_0000};
653 504 lampret 
`endif
654 1252 lampret 
`else
655 
assign dmr1 = 25'h000_0000;
656 
`endif
657 504 lampret 
 
658 
//
659 1252 lampret 
// Write to DMR2
660 504 lampret 
//
661 
`ifdef OR1200_DU_DMR2
662 1252 lampret 
always @(posedge clk or posedge rst)
663 
        if (rst)
664 
                dmr2 <= 24'h00_0000;
665 
        else if (dmr2_sel && spr_write)
666 
                dmr2 <= #1 spr_dat_i[23:0];
667 
`else
668 
assign dmr2 = 24'h00_0000;
669 504 lampret 
`endif
670 
 
671 
//
672 
// Write to DSR
673 
//
674 
`ifdef OR1200_DU_DSR
675 
always @(posedge clk or posedge rst)
676 
        if (rst)
677 
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
678 
        else if (dsr_sel && spr_write)
679 
                dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
680 
`else
681 
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
682 
`endif
683 
 
684 
//
685 
// Write to DRR
686 
//
687 
`ifdef OR1200_DU_DRR
688 
always @(posedge clk or posedge rst)
689 
        if (rst)
690 
                drr <= 14'b0;
691 
        else if (drr_sel && spr_write)
692 
                drr <= #1 spr_dat_i[13:0];
693 
        else
694 
                drr <= #1 drr | except_stop;
695 
`else
696 
assign drr = 14'b0;
697 
`endif
698 
 
699 
//
700 1252 lampret 
// Write to DVR0
701 
//
702 
`ifdef OR1200_DU_DVR0
703 
always @(posedge clk or posedge rst)
704 
        if (rst)
705 
                dvr0 <= 32'h0000_0000;
706 
        else if (dvr0_sel && spr_write)
707 
                dvr0 <= #1 spr_dat_i[31:0];
708 
`else
709 
assign dvr0 = 32'h0000_0000;
710 
`endif
711 
 
712 
//
713 
// Write to DVR1
714 
//
715 
`ifdef OR1200_DU_DVR1
716 
always @(posedge clk or posedge rst)
717 
        if (rst)
718 
                dvr1 <= 32'h0000_0000;
719 
        else if (dvr1_sel && spr_write)
720 
                dvr1 <= #1 spr_dat_i[31:0];
721 
`else
722 
assign dvr1 = 32'h0000_0000;
723 
`endif
724 
 
725 
//
726 
// Write to DVR2
727 
//
728 
`ifdef OR1200_DU_DVR2
729 
always @(posedge clk or posedge rst)
730 
        if (rst)
731 
                dvr2 <= 32'h0000_0000;
732 
        else if (dvr2_sel && spr_write)
733 
                dvr2 <= #1 spr_dat_i[31:0];
734 
`else
735 
assign dvr2 = 32'h0000_0000;
736 
`endif
737 
 
738 
//
739 
// Write to DVR3
740 
//
741 
`ifdef OR1200_DU_DVR3
742 
always @(posedge clk or posedge rst)
743 
        if (rst)
744 
                dvr3 <= 32'h0000_0000;
745 
        else if (dvr3_sel && spr_write)
746 
                dvr3 <= #1 spr_dat_i[31:0];
747 
`else
748 
assign dvr3 = 32'h0000_0000;
749 
`endif
750 
 
751 
//
752 
// Write to DVR4
753 
//
754 
`ifdef OR1200_DU_DVR4
755 
always @(posedge clk or posedge rst)
756 
        if (rst)
757 
                dvr4 <= 32'h0000_0000;
758 
        else if (dvr4_sel && spr_write)
759 
                dvr4 <= #1 spr_dat_i[31:0];
760 
`else
761 
assign dvr4 = 32'h0000_0000;
762 
`endif
763 
 
764 
//
765 
// Write to DVR5
766 
//
767 
`ifdef OR1200_DU_DVR5
768 
always @(posedge clk or posedge rst)
769 
        if (rst)
770 
                dvr5 <= 32'h0000_0000;
771 
        else if (dvr5_sel && spr_write)
772 
                dvr5 <= #1 spr_dat_i[31:0];
773 
`else
774 
assign dvr5 = 32'h0000_0000;
775 
`endif
776 
 
777 
//
778 
// Write to DVR6
779 
//
780 
`ifdef OR1200_DU_DVR6
781 
always @(posedge clk or posedge rst)
782 
        if (rst)
783 
                dvr6 <= 32'h0000_0000;
784 
        else if (dvr6_sel && spr_write)
785 
                dvr6 <= #1 spr_dat_i[31:0];
786 
`else
787 
assign dvr6 = 32'h0000_0000;
788 
`endif
789 
 
790 
//
791 
// Write to DVR7
792 
//
793 
`ifdef OR1200_DU_DVR7
794 
always @(posedge clk or posedge rst)
795 
        if (rst)
796 
                dvr7 <= 32'h0000_0000;
797 
        else if (dvr7_sel && spr_write)
798 
                dvr7 <= #1 spr_dat_i[31:0];
799 
`else
800 
assign dvr7 = 32'h0000_0000;
801 
`endif
802 
 
803 
//
804 
// Write to DCR0
805 
//
806 
`ifdef OR1200_DU_DCR0
807 
always @(posedge clk or posedge rst)
808 
        if (rst)
809 
                dcr0 <= 8'h00;
810 
        else if (dcr0_sel && spr_write)
811 
                dcr0 <= #1 spr_dat_i[7:0];
812 
`else
813 
assign dcr0 = 8'h00;
814 
`endif
815 
 
816 
//
817 
// Write to DCR1
818 
//
819 
`ifdef OR1200_DU_DCR1
820 
always @(posedge clk or posedge rst)
821 
        if (rst)
822 
                dcr1 <= 8'h00;
823 
        else if (dcr1_sel && spr_write)
824 
                dcr1 <= #1 spr_dat_i[7:0];
825 
`else
826 
assign dcr1 = 8'h00;
827 
`endif
828 
 
829 
//
830 
// Write to DCR2
831 
//
832 
`ifdef OR1200_DU_DCR2
833 
always @(posedge clk or posedge rst)
834 
        if (rst)
835 
                dcr2 <= 8'h00;
836 
        else if (dcr2_sel && spr_write)
837 
                dcr2 <= #1 spr_dat_i[7:0];
838 
`else
839 
assign dcr2 = 8'h00;
840 
`endif
841 
 
842 
//
843 
// Write to DCR3
844 
//
845 
`ifdef OR1200_DU_DCR3
846 
always @(posedge clk or posedge rst)
847 
        if (rst)
848 
                dcr3 <= 8'h00;
849 
        else if (dcr3_sel && spr_write)
850 
                dcr3 <= #1 spr_dat_i[7:0];
851 
`else
852 
assign dcr3 = 8'h00;
853 
`endif
854 
 
855 
//
856 
// Write to DCR4
857 
//
858 
`ifdef OR1200_DU_DCR4
859 
always @(posedge clk or posedge rst)
860 
        if (rst)
861 
                dcr4 <= 8'h00;
862 
        else if (dcr4_sel && spr_write)
863 
                dcr4 <= #1 spr_dat_i[7:0];
864 
`else
865 
assign dcr4 = 8'h00;
866 
`endif
867 
 
868 
//
869 
// Write to DCR5
870 
//
871 
`ifdef OR1200_DU_DCR5
872 
always @(posedge clk or posedge rst)
873 
        if (rst)
874 
                dcr5 <= 8'h00;
875 
        else if (dcr5_sel && spr_write)
876 
                dcr5 <= #1 spr_dat_i[7:0];
877 
`else
878 
assign dcr5 = 8'h00;
879 
`endif
880 
 
881 
//
882 
// Write to DCR6
883 
//
884 
`ifdef OR1200_DU_DCR6
885 
always @(posedge clk or posedge rst)
886 
        if (rst)
887 
                dcr6 <= 8'h00;
888 
        else if (dcr6_sel && spr_write)
889 
                dcr6 <= #1 spr_dat_i[7:0];
890 
`else
891 
assign dcr6 = 8'h00;
892 
`endif
893 
 
894 
//
895 
// Write to DCR7
896 
//
897 
`ifdef OR1200_DU_DCR7
898 
always @(posedge clk or posedge rst)
899 
        if (rst)
900 
                dcr7 <= 8'h00;
901 
        else if (dcr7_sel && spr_write)
902 
                dcr7 <= #1 spr_dat_i[7:0];
903 
`else
904 
assign dcr7 = 8'h00;
905 
`endif
906 
 
907 
//
908 
// Write to DWCR0
909 
//
910 
`ifdef OR1200_DU_DWCR0
911 
always @(posedge clk or posedge rst)
912 
        if (rst)
913 
                dwcr0 <= 32'h0000_0000;
914 
        else if (dwcr0_sel && spr_write)
915 
                dwcr0 <= #1 spr_dat_i[31:0];
916 
        else if (incr_wpcntr0)
917 
                dwcr0[`OR1200_DU_DWCR_COUNT] <= #1 dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
918 
`else
919 
assign dwcr0 = 32'h0000_0000;
920 
`endif
921 
 
922 
//
923 
// Write to DWCR1
924 
//
925 
`ifdef OR1200_DU_DWCR1
926 
always @(posedge clk or posedge rst)
927 
        if (rst)
928 
                dwcr1 <= 32'h0000_0000;
929 
        else if (dwcr1_sel && spr_write)
930 
                dwcr1 <= #1 spr_dat_i[31:0];
931 
        else if (incr_wpcntr1)
932 
                dwcr1[`OR1200_DU_DWCR_COUNT] <= #1 dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
933 
`else
934 
assign dwcr1 = 32'h0000_0000;
935 
`endif
936 
 
937 
//
938 504 lampret 
// Read DU registers
939 
//
940 
`ifdef OR1200_DU_READREGS
941 1112 lampret 
always @(spr_addr or dsr or drr or dmr1 or dmr2
942 1252 lampret 
        or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
943 
        or dvr5 or dvr6 or dvr7
944 
        or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
945 
        or dcr5 or dcr6 or dcr7
946 
        or dwcr0 or dwcr1
947 1038 lampret 
`ifdef OR1200_DU_TB_IMPLEMENTED
948 1112 lampret 
        or tb_wadr or tbia_dat_o or tbim_dat_o
949 
        or tbar_dat_o or tbts_dat_o
950 1038 lampret 
`endif
951 
        )
952 895 lampret 
        casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
953 1252 lampret 
`ifdef OR1200_DU_DVR0
954 
                `OR1200_DU_DVR0:
955 
                        spr_dat_o = dvr0;
956 
`endif
957 
`ifdef OR1200_DU_DVR1
958 
                `OR1200_DU_DVR1:
959 
                        spr_dat_o = dvr1;
960 
`endif
961 
`ifdef OR1200_DU_DVR2
962 
                `OR1200_DU_DVR2:
963 
                        spr_dat_o = dvr2;
964 
`endif
965 
`ifdef OR1200_DU_DVR3
966 
                `OR1200_DU_DVR3:
967 
                        spr_dat_o = dvr3;
968 
`endif
969 
`ifdef OR1200_DU_DVR4
970 
                `OR1200_DU_DVR4:
971 
                        spr_dat_o = dvr4;
972 
`endif
973 
`ifdef OR1200_DU_DVR5
974 
                `OR1200_DU_DVR5:
975 
                        spr_dat_o = dvr5;
976 
`endif
977 
`ifdef OR1200_DU_DVR6
978 
                `OR1200_DU_DVR6:
979 
                        spr_dat_o = dvr6;
980 
`endif
981 
`ifdef OR1200_DU_DVR7
982 
                `OR1200_DU_DVR7:
983 
                        spr_dat_o = dvr7;
984 
`endif
985 
`ifdef OR1200_DU_DCR0
986 
                `OR1200_DU_DCR0:
987 
                        spr_dat_o = {24'h00_0000, dcr0};
988 
`endif
989 
`ifdef OR1200_DU_DCR1
990 
                `OR1200_DU_DCR1:
991 
                        spr_dat_o = {24'h00_0000, dcr1};
992 
`endif
993 
`ifdef OR1200_DU_DCR2
994 
                `OR1200_DU_DCR2:
995 
                        spr_dat_o = {24'h00_0000, dcr2};
996 
`endif
997 
`ifdef OR1200_DU_DCR3
998 
                `OR1200_DU_DCR3:
999 
                        spr_dat_o = {24'h00_0000, dcr3};
1000 
`endif
1001 
`ifdef OR1200_DU_DCR4
1002 
                `OR1200_DU_DCR4:
1003 
                        spr_dat_o = {24'h00_0000, dcr4};
1004 
`endif
1005 
`ifdef OR1200_DU_DCR5
1006 
                `OR1200_DU_DCR5:
1007 
                        spr_dat_o = {24'h00_0000, dcr5};
1008 
`endif
1009 
`ifdef OR1200_DU_DCR6
1010 
                `OR1200_DU_DCR6:
1011 
                        spr_dat_o = {24'h00_0000, dcr6};
1012 
`endif
1013 
`ifdef OR1200_DU_DCR7
1014 
                `OR1200_DU_DCR7:
1015 
                        spr_dat_o = {24'h00_0000, dcr7};
1016 
`endif
1017 504 lampret 
`ifdef OR1200_DU_DMR1
1018 1252 lampret 
                `OR1200_DU_DMR1:
1019 
                        spr_dat_o = {7'h00, dmr1};
1020 504 lampret 
`endif
1021 
`ifdef OR1200_DU_DMR2
1022 1252 lampret 
                `OR1200_DU_DMR2:
1023 
                        spr_dat_o = {8'h00, dmr2};
1024 504 lampret 
`endif
1025 1252 lampret 
`ifdef OR1200_DU_DWCR0
1026 
                `OR1200_DU_DWCR0:
1027 
                        spr_dat_o = dwcr0;
1028 
`endif
1029 
`ifdef OR1200_DU_DWCR1
1030 
                `OR1200_DU_DWCR1:
1031 
                        spr_dat_o = dwcr1;
1032 
`endif
1033 504 lampret 
`ifdef OR1200_DU_DSR
1034 1252 lampret 
                `OR1200_DU_DSR:
1035 504 lampret 
                        spr_dat_o = {18'b0, dsr};
1036 
`endif
1037 
`ifdef OR1200_DU_DRR
1038 1252 lampret 
                `OR1200_DU_DRR:
1039 504 lampret 
                        spr_dat_o = {18'b0, drr};
1040 
`endif
1041 895 lampret 
`ifdef OR1200_DU_TB_IMPLEMENTED
1042 1252 lampret 
                `OR1200_DU_TBADR:
1043 895 lampret 
                        spr_dat_o = {24'h000000, tb_wadr};
1044 1252 lampret 
                `OR1200_DU_TBIA:
1045 895 lampret 
                        spr_dat_o = tbia_dat_o;
1046 1252 lampret 
                `OR1200_DU_TBIM:
1047 895 lampret 
                        spr_dat_o = tbim_dat_o;
1048 1252 lampret 
                `OR1200_DU_TBAR:
1049 895 lampret 
                        spr_dat_o = tbar_dat_o;
1050 1252 lampret 
                `OR1200_DU_TBTS:
1051 895 lampret 
                        spr_dat_o = tbts_dat_o;
1052 
`endif
1053 504 lampret 
                default:
1054 
                        spr_dat_o = 32'h0000_0000;
1055 
        endcase
1056 
`endif
1057 
 
1058 
//
1059 
// DSR alias
1060 
//
1061 
assign du_dsr = dsr;
1062 
 
1063 1252 lampret 
`ifdef OR1200_DU_HWBKPTS
1064 
 
1065 
//
1066 
// Compare To What (Match Condition 0)
1067 
//
1068 
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
1069 
        or dcpu_dat_lsu or dcpu_we_i)
1070 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1071 
                3'b001: match_cond0_ct = id_pc;         // insn fetch EA
1072 
                3'b010: match_cond0_ct = dcpu_adr_i;    // load EA
1073 
                3'b011: match_cond0_ct = dcpu_adr_i;    // store EA
1074 
                3'b100: match_cond0_ct = dcpu_dat_dc;   // load data
1075 
                3'b101: match_cond0_ct = dcpu_dat_lsu;  // store data
1076 
                3'b110: match_cond0_ct = dcpu_adr_i;    // load/store EA
1077 
                default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1078 
        endcase
1079 
 
1080 
//
1081 
// When To Compare (Match Condition 0)
1082 
//
1083 
always @(dcr0 or dcpu_cycstb_i)
1084 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1085 
                3'b000: match_cond0_stb = 1'b0;         //comparison disabled
1086 
                3'b001: match_cond0_stb = 1'b1;         // insn fetch EA
1087 
                default:match_cond0_stb = dcpu_cycstb_i; // any load/store
1088 
        endcase
1089 
 
1090 
//
1091 
// Match Condition 0
1092 
//
1093 
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
1094 
        casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
1095 
                4'b0_xxx,
1096 
                4'b1_000,
1097 
                4'b1_111: match0 = 1'b0;
1098 
                4'b1_001: match0 =
1099 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) ==
1100 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1101 
                4'b1_010: match0 =
1102 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <
1103 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1104 
                4'b1_011: match0 =
1105 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <=
1106 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1107 
                4'b1_100: match0 =
1108 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >
1109 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1110 
                4'b1_101: match0 =
1111 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >=
1112 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1113 
                4'b1_110: match0 =
1114 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) !=
1115 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1116 
        endcase
1117 
 
1118 
//
1119 
// Watchpoint 0
1120 
//
1121 
always @(dmr1 or match0)
1122 
        case (dmr1[`OR1200_DU_DMR1_CW0])
1123 
                2'b00: wp[0] = match0;
1124 
                2'b01: wp[0] = match0;
1125 
                2'b10: wp[0] = match0;
1126 
                2'b11: wp[0] = 1'b0;
1127 
        endcase
1128 
 
1129 
//
1130 
// Compare To What (Match Condition 1)
1131 
//
1132 
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
1133 
        or dcpu_dat_lsu or dcpu_we_i)
1134 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1135 
                3'b001: match_cond1_ct = id_pc;         // insn fetch EA
1136 
                3'b010: match_cond1_ct = dcpu_adr_i;    // load EA
1137 
                3'b011: match_cond1_ct = dcpu_adr_i;    // store EA
1138 
                3'b100: match_cond1_ct = dcpu_dat_dc;   // load data
1139 
                3'b101: match_cond1_ct = dcpu_dat_lsu;  // store data
1140 
                3'b110: match_cond1_ct = dcpu_adr_i;    // load/store EA
1141 
                default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1142 
        endcase
1143 
 
1144 
//
1145 
// When To Compare (Match Condition 1)
1146 
//
1147 
always @(dcr1 or dcpu_cycstb_i)
1148 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1149 
                3'b000: match_cond1_stb = 1'b0;         //comparison disabled
1150 
                3'b001: match_cond1_stb = 1'b1;         // insn fetch EA
1151 
                default:match_cond1_stb = dcpu_cycstb_i; // any load/store
1152 
        endcase
1153 
 
1154 
//
1155 
// Match Condition 1
1156 
//
1157 
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
1158 
        casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
1159 
                4'b0_xxx,
1160 
                4'b1_000,
1161 
                4'b1_111: match1 = 1'b0;
1162 
                4'b1_001: match1 =
1163 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) ==
1164 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1165 
                4'b1_010: match1 =
1166 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <
1167 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1168 
                4'b1_011: match1 =
1169 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <=
1170 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1171 
                4'b1_100: match1 =
1172 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >
1173 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1174 
                4'b1_101: match1 =
1175 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >=
1176 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1177 
                4'b1_110: match1 =
1178 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) !=
1179 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1180 
        endcase
1181 
 
1182 
//
1183 
// Watchpoint 1
1184 
//
1185 
always @(dmr1 or match1 or wp)
1186 
        case (dmr1[`OR1200_DU_DMR1_CW1])
1187 
                2'b00: wp[1] = match1;
1188 
                2'b01: wp[1] = match1 & wp[0];
1189 
                2'b10: wp[1] = match1 | wp[0];
1190 
                2'b11: wp[1] = 1'b0;
1191 
        endcase
1192 
 
1193 
//
1194 
// Compare To What (Match Condition 2)
1195 
//
1196 
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
1197 
        or dcpu_dat_lsu or dcpu_we_i)
1198 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1199 
                3'b001: match_cond2_ct = id_pc;         // insn fetch EA
1200 
                3'b010: match_cond2_ct = dcpu_adr_i;    // load EA
1201 
                3'b011: match_cond2_ct = dcpu_adr_i;    // store EA
1202 
                3'b100: match_cond2_ct = dcpu_dat_dc;   // load data
1203 
                3'b101: match_cond2_ct = dcpu_dat_lsu;  // store data
1204 
                3'b110: match_cond2_ct = dcpu_adr_i;    // load/store EA
1205 
                default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1206 
        endcase
1207 
 
1208 
//
1209 
// When To Compare (Match Condition 2)
1210 
//
1211 
always @(dcr2 or dcpu_cycstb_i)
1212 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1213 
                3'b000: match_cond2_stb = 1'b0;         //comparison disabled
1214 
                3'b001: match_cond2_stb = 1'b1;         // insn fetch EA
1215 
                default:match_cond2_stb = dcpu_cycstb_i; // any load/store
1216 
        endcase
1217 
 
1218 
//
1219 
// Match Condition 2
1220 
//
1221 
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
1222 
        casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
1223 
                4'b0_xxx,
1224 
                4'b1_000,
1225 
                4'b1_111: match2 = 1'b0;
1226 
                4'b1_001: match2 =
1227 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) ==
1228 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1229 
                4'b1_010: match2 =
1230 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <
1231 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1232 
                4'b1_011: match2 =
1233 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <=
1234 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1235 
                4'b1_100: match2 =
1236 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >
1237 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1238 
                4'b1_101: match2 =
1239 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >=
1240 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1241 
                4'b1_110: match2 =
1242 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) !=
1243 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1244 
        endcase
1245 
 
1246 
//
1247 
// Watchpoint 2
1248 
//
1249 
always @(dmr1 or match2 or wp)
1250 
        case (dmr1[`OR1200_DU_DMR1_CW2])
1251 
                2'b00: wp[2] = match2;
1252 
                2'b01: wp[2] = match2 & wp[1];
1253 
                2'b10: wp[2] = match2 | wp[1];
1254 
                2'b11: wp[2] = 1'b0;
1255 
        endcase
1256 
 
1257 
//
1258 
// Compare To What (Match Condition 3)
1259 
//
1260 
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
1261 
        or dcpu_dat_lsu or dcpu_we_i)
1262 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1263 
                3'b001: match_cond3_ct = id_pc;         // insn fetch EA
1264 
                3'b010: match_cond3_ct = dcpu_adr_i;    // load EA
1265 
                3'b011: match_cond3_ct = dcpu_adr_i;    // store EA
1266 
                3'b100: match_cond3_ct = dcpu_dat_dc;   // load data
1267 
                3'b101: match_cond3_ct = dcpu_dat_lsu;  // store data
1268 
                3'b110: match_cond3_ct = dcpu_adr_i;    // load/store EA
1269 
                default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1270 
        endcase
1271 
 
1272 
//
1273 
// When To Compare (Match Condition 3)
1274 
//
1275 
always @(dcr3 or dcpu_cycstb_i)
1276 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1277 
                3'b000: match_cond3_stb = 1'b0;         //comparison disabled
1278 
                3'b001: match_cond3_stb = 1'b1;         // insn fetch EA
1279 
                default:match_cond3_stb = dcpu_cycstb_i; // any load/store
1280 
        endcase
1281 
 
1282 
//
1283 
// Match Condition 3
1284 
//
1285 
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
1286 
        casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
1287 
                4'b0_xxx,
1288 
                4'b1_000,
1289 
                4'b1_111: match3 = 1'b0;
1290 
                4'b1_001: match3 =
1291 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) ==
1292 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1293 
                4'b1_010: match3 =
1294 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <
1295 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1296 
                4'b1_011: match3 =
1297 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <=
1298 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1299 
                4'b1_100: match3 =
1300 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >
1301 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1302 
                4'b1_101: match3 =
1303 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >=
1304 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1305 
                4'b1_110: match3 =
1306 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) !=
1307 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1308 
        endcase
1309 
 
1310 
//
1311 
// Watchpoint 3
1312 
//
1313 
always @(dmr1 or match3 or wp)
1314 
        case (dmr1[`OR1200_DU_DMR1_CW3])
1315 
                2'b00: wp[3] = match3;
1316 
                2'b01: wp[3] = match3 & wp[2];
1317 
                2'b10: wp[3] = match3 | wp[2];
1318 
                2'b11: wp[3] = 1'b0;
1319 
        endcase
1320 
 
1321 
//
1322 
// Compare To What (Match Condition 4)
1323 
//
1324 
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
1325 
        or dcpu_dat_lsu or dcpu_we_i)
1326 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1327 
                3'b001: match_cond4_ct = id_pc;         // insn fetch EA
1328 
                3'b010: match_cond4_ct = dcpu_adr_i;    // load EA
1329 
                3'b011: match_cond4_ct = dcpu_adr_i;    // store EA
1330 
                3'b100: match_cond4_ct = dcpu_dat_dc;   // load data
1331 
                3'b101: match_cond4_ct = dcpu_dat_lsu;  // store data
1332 
                3'b110: match_cond4_ct = dcpu_adr_i;    // load/store EA
1333 
                default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1334 
        endcase
1335 
 
1336 
//
1337 
// When To Compare (Match Condition 4)
1338 
//
1339 
always @(dcr4 or dcpu_cycstb_i)
1340 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1341 
                3'b000: match_cond4_stb = 1'b0;         //comparison disabled
1342 
                3'b001: match_cond4_stb = 1'b1;         // insn fetch EA
1343 
                default:match_cond4_stb = dcpu_cycstb_i; // any load/store
1344 
        endcase
1345 
 
1346 
//
1347 
// Match Condition 4
1348 
//
1349 
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
1350 
        casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
1351 
                4'b0_xxx,
1352 
                4'b1_000,
1353 
                4'b1_111: match4 = 1'b0;
1354 
                4'b1_001: match4 =
1355 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) ==
1356 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1357 
                4'b1_010: match4 =
1358 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <
1359 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1360 
                4'b1_011: match4 =
1361 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <=
1362 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1363 
                4'b1_100: match4 =
1364 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >
1365 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1366 
                4'b1_101: match4 =
1367 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >=
1368 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1369 
                4'b1_110: match4 =
1370 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) !=
1371 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1372 
        endcase
1373 
 
1374 
//
1375 
// Watchpoint 4
1376 
//
1377 
always @(dmr1 or match4 or wp)
1378 
        case (dmr1[`OR1200_DU_DMR1_CW4])
1379 
                2'b00: wp[4] = match4;
1380 
                2'b01: wp[4] = match4 & wp[3];
1381 
                2'b10: wp[4] = match4 | wp[3];
1382 
                2'b11: wp[4] = 1'b0;
1383 
        endcase
1384 
 
1385 
//
1386 
// Compare To What (Match Condition 5)
1387 
//
1388 
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
1389 
        or dcpu_dat_lsu or dcpu_we_i)
1390 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1391 
                3'b001: match_cond5_ct = id_pc;         // insn fetch EA
1392 
                3'b010: match_cond5_ct = dcpu_adr_i;    // load EA
1393 
                3'b011: match_cond5_ct = dcpu_adr_i;    // store EA
1394 
                3'b100: match_cond5_ct = dcpu_dat_dc;   // load data
1395 
                3'b101: match_cond5_ct = dcpu_dat_lsu;  // store data
1396 
                3'b110: match_cond5_ct = dcpu_adr_i;    // load/store EA
1397 
                default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1398 
        endcase
1399 
 
1400 
//
1401 
// When To Compare (Match Condition 5)
1402 
//
1403 
always @(dcr5 or dcpu_cycstb_i)
1404 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1405 
                3'b000: match_cond5_stb = 1'b0;         //comparison disabled
1406 
                3'b001: match_cond5_stb = 1'b1;         // insn fetch EA
1407 
                default:match_cond5_stb = dcpu_cycstb_i; // any load/store
1408 
        endcase
1409 
 
1410 
//
1411 
// Match Condition 5
1412 
//
1413 
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
1414 
        casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
1415 
                4'b0_xxx,
1416 
                4'b1_000,
1417 
                4'b1_111: match5 = 1'b0;
1418 
                4'b1_001: match5 =
1419 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) ==
1420 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1421 
                4'b1_010: match5 =
1422 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <
1423 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1424 
                4'b1_011: match5 =
1425 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <=
1426 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1427 
                4'b1_100: match5 =
1428 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >
1429 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1430 
                4'b1_101: match5 =
1431 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >=
1432 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1433 
                4'b1_110: match5 =
1434 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) !=
1435 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1436 
        endcase
1437 
 
1438 
//
1439 
// Watchpoint 5
1440 
//
1441 
always @(dmr1 or match5 or wp)
1442 
        case (dmr1[`OR1200_DU_DMR1_CW5])
1443 
                2'b00: wp[5] = match5;
1444 
                2'b01: wp[5] = match5 & wp[4];
1445 
                2'b10: wp[5] = match5 | wp[4];
1446 
                2'b11: wp[5] = 1'b0;
1447 
        endcase
1448 
 
1449 
//
1450 
// Compare To What (Match Condition 6)
1451 
//
1452 
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
1453 
        or dcpu_dat_lsu or dcpu_we_i)
1454 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1455 
                3'b001: match_cond6_ct = id_pc;         // insn fetch EA
1456 
                3'b010: match_cond6_ct = dcpu_adr_i;    // load EA
1457 
                3'b011: match_cond6_ct = dcpu_adr_i;    // store EA
1458 
                3'b100: match_cond6_ct = dcpu_dat_dc;   // load data
1459 
                3'b101: match_cond6_ct = dcpu_dat_lsu;  // store data
1460 
                3'b110: match_cond6_ct = dcpu_adr_i;    // load/store EA
1461 
                default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1462 
        endcase
1463 
 
1464 
//
1465 
// When To Compare (Match Condition 6)
1466 
//
1467 
always @(dcr6 or dcpu_cycstb_i)
1468 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1469 
                3'b000: match_cond6_stb = 1'b0;         //comparison disabled
1470 
                3'b001: match_cond6_stb = 1'b1;         // insn fetch EA
1471 
                default:match_cond6_stb = dcpu_cycstb_i; // any load/store
1472 
        endcase
1473 
 
1474 
//
1475 
// Match Condition 6
1476 
//
1477 
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
1478 
        casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
1479 
                4'b0_xxx,
1480 
                4'b1_000,
1481 
                4'b1_111: match6 = 1'b0;
1482 
                4'b1_001: match6 =
1483 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) ==
1484 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1485 
                4'b1_010: match6 =
1486 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <
1487 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1488 
                4'b1_011: match6 =
1489 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <=
1490 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1491 
                4'b1_100: match6 =
1492 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >
1493 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1494 
                4'b1_101: match6 =
1495 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >=
1496 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1497 
                4'b1_110: match6 =
1498 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) !=
1499 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1500 
        endcase
1501 
 
1502 
//
1503 
// Watchpoint 6
1504 
//
1505 
always @(dmr1 or match6 or wp)
1506 
        case (dmr1[`OR1200_DU_DMR1_CW6])
1507 
                2'b00: wp[6] = match6;
1508 
                2'b01: wp[6] = match6 & wp[5];
1509 
                2'b10: wp[6] = match6 | wp[5];
1510 
                2'b11: wp[6] = 1'b0;
1511 
        endcase
1512 
 
1513 
//
1514 
// Compare To What (Match Condition 7)
1515 
//
1516 
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
1517 
        or dcpu_dat_lsu or dcpu_we_i)
1518 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1519 
                3'b001: match_cond7_ct = id_pc;         // insn fetch EA
1520 
                3'b010: match_cond7_ct = dcpu_adr_i;    // load EA
1521 
                3'b011: match_cond7_ct = dcpu_adr_i;    // store EA
1522 
                3'b100: match_cond7_ct = dcpu_dat_dc;   // load data
1523 
                3'b101: match_cond7_ct = dcpu_dat_lsu;  // store data
1524 
                3'b110: match_cond7_ct = dcpu_adr_i;    // load/store EA
1525 
                default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1526 
        endcase
1527 
 
1528 
//
1529 
// When To Compare (Match Condition 7)
1530 
//
1531 
always @(dcr7 or dcpu_cycstb_i)
1532 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1533 
                3'b000: match_cond7_stb = 1'b0;         //comparison disabled
1534 
                3'b001: match_cond7_stb = 1'b1;         // insn fetch EA
1535 
                default:match_cond7_stb = dcpu_cycstb_i; // any load/store
1536 
        endcase
1537 
 
1538 
//
1539 
// Match Condition 7
1540 
//
1541 
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
1542 
        casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
1543 
                4'b0_xxx,
1544 
                4'b1_000,
1545 
                4'b1_111: match7 = 1'b0;
1546 
                4'b1_001: match7 =
1547 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) ==
1548 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1549 
                4'b1_010: match7 =
1550 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <
1551 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1552 
                4'b1_011: match7 =
1553 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <=
1554 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1555 
                4'b1_100: match7 =
1556 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >
1557 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1558 
                4'b1_101: match7 =
1559 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >=
1560 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1561 
                4'b1_110: match7 =
1562 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) !=
1563 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1564 
        endcase
1565 
 
1566 
//
1567 
// Watchpoint 7
1568 
//
1569 
always @(dmr1 or match7 or wp)
1570 
        case (dmr1[`OR1200_DU_DMR1_CW7])
1571 
                2'b00: wp[7] = match7;
1572 
                2'b01: wp[7] = match7 & wp[6];
1573 
                2'b10: wp[7] = match7 | wp[6];
1574 
                2'b11: wp[7] = 1'b0;
1575 
        endcase
1576 
 
1577 
//
1578 
// Increment Watchpoint Counter 0
1579 
//
1580 
always @(wp or dmr2)
1581 
        if (dmr2[`OR1200_DU_DMR2_WCE0])
1582 
                incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
1583 
        else
1584 
                incr_wpcntr0 = 1'b0;
1585 
 
1586 
//
1587 
// Match Condition Watchpoint Counter 0
1588 
//
1589 
always @(dwcr0)
1590 
        if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
1591 
                wpcntr0_match = 1'b1;
1592 
        else
1593 
                wpcntr0_match = 1'b0;
1594 
 
1595 
 
1596 
//
1597 
// Watchpoint 8
1598 
//
1599 
always @(dmr1 or wpcntr0_match or wp)
1600 
        case (dmr1[`OR1200_DU_DMR1_CW8])
1601 
                2'b00: wp[8] = wpcntr0_match;
1602 
                2'b01: wp[8] = wpcntr0_match & wp[7];
1603 
                2'b10: wp[8] = wpcntr0_match | wp[7];
1604 
                2'b11: wp[8] = 1'b0;
1605 
        endcase
1606 
 
1607 
 
1608 
//
1609 
// Increment Watchpoint Counter 1
1610 
//
1611 
always @(wp or dmr2)
1612 
        if (dmr2[`OR1200_DU_DMR2_WCE1])
1613 
                incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
1614 
        else
1615 
                incr_wpcntr1 = 1'b0;
1616 
 
1617 
//
1618 
// Match Condition Watchpoint Counter 1
1619 
//
1620 
always @(dwcr1)
1621 
        if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
1622 
                wpcntr1_match = 1'b1;
1623 
        else
1624 
                wpcntr1_match = 1'b0;
1625 
 
1626 
//
1627 
// Watchpoint 9
1628 
//
1629 
always @(dmr1 or wpcntr1_match or wp)
1630 
        case (dmr1[`OR1200_DU_DMR1_CW9])
1631 
                2'b00: wp[9] = wpcntr1_match;
1632 
                2'b01: wp[9] = wpcntr1_match & wp[8];
1633 
                2'b10: wp[9] = wpcntr1_match | wp[8];
1634 
                2'b11: wp[9] = 1'b0;
1635 
        endcase
1636 
 
1637 
//
1638 
// Watchpoint 10
1639 
//
1640 
always @(dmr1 or dbg_ewt_i or wp)
1641 
        case (dmr1[`OR1200_DU_DMR1_CW10])
1642 
                2'b00: wp[10] = dbg_ewt_i;
1643 
                2'b01: wp[10] = dbg_ewt_i & wp[9];
1644 
                2'b10: wp[10] = dbg_ewt_i | wp[9];
1645 
                2'b11: wp[10] = 1'b0;
1646 
        endcase
1647 
 
1648 
`endif
1649 
 
1650 
//
1651 
// Watchpoints can cause trap exception
1652 
//
1653 
`ifdef OR1200_DU_HWBKPTS
1654 
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]);
1655 
`else
1656 
assign du_hwbkpt = 1'b0;
1657 
`endif
1658 
 
1659 895 lampret 
`ifdef OR1200_DU_TB_IMPLEMENTED
1660 
//
1661 
// Simple trace buffer
1662 
// (right now hardcoded for Xilinx Virtex FPGAs)
1663 
//
1664 
// Stores last 256 instruction addresses, instruction
1665 
// machine words and ALU results
1666 
//
1667 
 
1668 
//
1669 
// Trace buffer write enable
1670 
//
1671 
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
1672 
 
1673 
//
1674 
// Trace buffer write address pointer
1675 
//
1676 
always @(posedge clk or posedge rst)
1677 
        if (rst)
1678 
                tb_wadr <= #1 8'h00;
1679 
        else if (tb_enw)
1680 
                tb_wadr <= #1 tb_wadr + 8'd1;
1681 
 
1682 
//
1683 
// Free running counter (time stamp)
1684 
//
1685 
always @(posedge clk or posedge rst)
1686 
        if (rst)
1687 
                tb_timstmp <= #1 32'h00000000;
1688 
        else if (!dbg_bp_r)
1689 
                tb_timstmp <= #1 tb_timstmp + 32'd1;
1690 
 
1691 
//
1692 
// Trace buffer RAMs
1693 
//
1694 
RAMB4_S16_S16 tbia_ramb4_s16_0(
1695 
        .CLKA(clk),
1696 
        .RSTA(rst),
1697 
        .ADDRA(tb_wadr),
1698 
        .DIA(spr_dat_npc[15:0]),
1699 
        .ENA(1'b1),
1700 
        .WEA(tb_enw),
1701 
        .DOA(),
1702 
 
1703 
        .CLKB(clk),
1704 
        .RSTB(rst),
1705 
        .ADDRB(spr_addr[7:0]),
1706 
        .DIB(16'h0000),
1707 
        .ENB(1'b1),
1708 
        .WEB(1'b0),
1709 
        .DOB(tbia_dat_o[15:0])
1710 
);
1711 
 
1712 
RAMB4_S16_S16 tbia_ramb4_s16_1(
1713 
        .CLKA(clk),
1714 
        .RSTA(rst),
1715 
        .ADDRA(tb_wadr),
1716 
        .DIA(spr_dat_npc[31:16]),
1717 
        .ENA(1'b1),
1718 
        .WEA(tb_enw),
1719 
        .DOA(),
1720 
 
1721 
        .CLKB(clk),
1722 
        .RSTB(rst),
1723 
        .ADDRB(spr_addr[7:0]),
1724 
        .DIB(16'h0000),
1725 
        .ENB(1'b1),
1726 
        .WEB(1'b0),
1727 
        .DOB(tbia_dat_o[31:16])
1728 
);
1729 
 
1730 
RAMB4_S16_S16 tbim_ramb4_s16_0(
1731 
        .CLKA(clk),
1732 
        .RSTA(rst),
1733 
        .ADDRA(tb_wadr),
1734 
        .DIA(ex_insn[15:0]),
1735 
        .ENA(1'b1),
1736 
        .WEA(tb_enw),
1737 
        .DOA(),
1738 
 
1739 
        .CLKB(clk),
1740 
        .RSTB(rst),
1741 
        .ADDRB(spr_addr[7:0]),
1742 
        .DIB(16'h0000),
1743 
        .ENB(1'b1),
1744 
        .WEB(1'b0),
1745 
        .DOB(tbim_dat_o[15:0])
1746 
);
1747 
 
1748 
RAMB4_S16_S16 tbim_ramb4_s16_1(
1749 
        .CLKA(clk),
1750 
        .RSTA(rst),
1751 
        .ADDRA(tb_wadr),
1752 
        .DIA(ex_insn[31:16]),
1753 
        .ENA(1'b1),
1754 
        .WEA(tb_enw),
1755 
        .DOA(),
1756 
 
1757 
        .CLKB(clk),
1758 
        .RSTB(rst),
1759 
        .ADDRB(spr_addr[7:0]),
1760 
        .DIB(16'h0000),
1761 
        .ENB(1'b1),
1762 
        .WEB(1'b0),
1763 
        .DOB(tbim_dat_o[31:16])
1764 
);
1765 
 
1766 
RAMB4_S16_S16 tbar_ramb4_s16_0(
1767 
        .CLKA(clk),
1768 
        .RSTA(rst),
1769 
        .ADDRA(tb_wadr),
1770 
        .DIA(rf_dataw[15:0]),
1771 
        .ENA(1'b1),
1772 
        .WEA(tb_enw),
1773 
        .DOA(),
1774 
 
1775 
        .CLKB(clk),
1776 
        .RSTB(rst),
1777 
        .ADDRB(spr_addr[7:0]),
1778 
        .DIB(16'h0000),
1779 
        .ENB(1'b1),
1780 
        .WEB(1'b0),
1781 
        .DOB(tbar_dat_o[15:0])
1782 
);
1783 
 
1784 
RAMB4_S16_S16 tbar_ramb4_s16_1(
1785 
        .CLKA(clk),
1786 
        .RSTA(rst),
1787 
        .ADDRA(tb_wadr),
1788 
        .DIA(rf_dataw[31:16]),
1789 
        .ENA(1'b1),
1790 
        .WEA(tb_enw),
1791 
        .DOA(),
1792 
 
1793 
        .CLKB(clk),
1794 
        .RSTB(rst),
1795 
        .ADDRB(spr_addr[7:0]),
1796 
        .DIB(16'h0000),
1797 
        .ENB(1'b1),
1798 
        .WEB(1'b0),
1799 
        .DOB(tbar_dat_o[31:16])
1800 
);
1801 
 
1802 
RAMB4_S16_S16 tbts_ramb4_s16_0(
1803 
        .CLKA(clk),
1804 
        .RSTA(rst),
1805 
        .ADDRA(tb_wadr),
1806 
        .DIA(tb_timstmp[15:0]),
1807 
        .ENA(1'b1),
1808 
        .WEA(tb_enw),
1809 
        .DOA(),
1810 
 
1811 
        .CLKB(clk),
1812 
        .RSTB(rst),
1813 
        .ADDRB(spr_addr[7:0]),
1814 
        .DIB(16'h0000),
1815 
        .ENB(1'b1),
1816 
        .WEB(1'b0),
1817 
        .DOB(tbts_dat_o[15:0])
1818 
);
1819 
 
1820 
RAMB4_S16_S16 tbts_ramb4_s16_1(
1821 
        .CLKA(clk),
1822 
        .RSTA(rst),
1823 
        .ADDRA(tb_wadr),
1824 
        .DIA(tb_timstmp[31:16]),
1825 
        .ENA(1'b1),
1826 
        .WEA(tb_enw),
1827 
        .DOA(),
1828 
 
1829 
        .CLKB(clk),
1830 
        .RSTB(rst),
1831 
        .ADDRB(spr_addr[7:0]),
1832 
        .DIB(16'h0000),
1833 
        .ENB(1'b1),
1834 
        .WEB(1'b0),
1835 
        .DOB(tbts_dat_o[31:16])
1836 
);
1837 
 
1838 504 lampret 
`else
1839 895 lampret 
assign tbia_dat_o = 32'h0000_0000;
1840 
assign tbim_dat_o = 32'h0000_0000;
1841 
assign tbar_dat_o = 32'h0000_0000;
1842 
assign tbts_dat_o = 32'h0000_0000;
1843 504 lampret 
 
1844 895 lampret 
`endif  // OR1200_DU_TB_IMPLEMENTED
1845 
 
1846 
`else   // OR1200_DU_IMPLEMENTED
1847 
 
1848 504 lampret 
//
1849 
// When DU is not implemented, drive all outputs as would when DU is disabled
1850 
//
1851 
assign dbg_bp_o = 1'b0;
1852 
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
1853 
 
1854 
//
1855 
// Read DU registers
1856 
//
1857 
`ifdef OR1200_DU_READREGS
1858 
assign spr_dat_o = 32'h0000_0000;
1859 
`ifdef OR1200_DU_UNUSED_ZERO
1860 
`endif
1861 
`endif
1862 
 
1863 
`endif
1864 
 
1865 
endmodule

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